Semiconductor structure and manufacturing method thereof
By forming a rounded side wall structure and interlayer dielectric layer on the gate side wall of the semiconductor structure, the problem of interlayer dielectric layer cracks in the high temperature difference environment is solved, the reliability of the semiconductor structure is improved and the process is simplified.
Patent Information
- Application Number
- CN202411863614.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2025-03-21
AI Technical Summary
In the high temperature difference environment, the existing semiconductor structures cause cracks in the dielectric layer between layers due to different thermal expansion coefficients of materials, and the metal layer penetrates into the gate, causing the device to be short-circuited, resulting in poor reliability.
A semiconductor structure is designed, in which a side wall structure with a rounded morphology on the side wall of the gate electrode is provided on the side wall of the gate electrode. The materials of the interlayer dielectric layer and the side wall structure are the same as the gate material. The side wall structure and the interlayer dielectric layer are formed through a self-alignment process to avoid cracking problems at the top corners.
It effectively avoids interlayer dielectric layer cracks caused by stress in high temperature difference environments, improves the reliability of semiconductor structures, simplifies the process flow, and reduces production costs.
Smart Images
Figure CN119677156A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art
[0002] Before using, MOSFET needs to undergo high temperature difference reliability tests such as temperature cycling (TCT), temperature shock (TS) and power cycling (PCT).
[0003] Figure 1 It is a schematic diagram of the active region cell structure of the existing MOSFET, such as Figure 1 As shown, in a planar MOSFET, an interlayer dielectric layer is provided between the gate and the metal layer. Due to the different thermal expansion coefficients of the gate (made of polysilicon) and the interlayer dielectric layer (made of silicon oxide), a crack S1 appears in the interlayer dielectric layer due to stress in the right-angle or obtuse-angle contact area between the gate and the interlayer dielectric layer under a high temperature difference environment. The metal layer penetrates into the gate through the crack S1, causing a device short circuit, thereby causing device failure. Summary of the invention
[0004] The main purpose of the present application is to provide a semiconductor structure and a method for manufacturing the same, so as to at least solve the problem of poor reliability of the semiconductor structure in the prior art.
[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor structure is provided, comprising: a substrate; an epitaxial layer, located on a surface of one side of the substrate; a plurality of injection regions, located at intervals in the epitaxial layer, the surface of the injection region away from the substrate being a partial surface of the epitaxial layer; a gate, located on a side of the epitaxial layer away from the substrate and between two adjacent injection regions, the orthographic projection of the gate in the epitaxial layer overlapping with the two adjacent injection regions respectively; a sidewall structure, located on the sidewall of the gate, the end of the sidewall structure away from the epitaxial layer having a rounded morphology; an interlayer dielectric layer, located on the surface of the gate and the sidewall structure away from the epitaxial layer and on the sidewall of the sidewall structure; a metal layer, located on the surface of the interlayer dielectric layer away from the epitaxial layer, on the sidewall of the interlayer dielectric layer and on the partial surface of the injection region away from the substrate.
[0006] Optionally, an end of the interlayer dielectric layer away from the epitaxial layer has a rounded corner morphology.
[0007] Optionally, the injection region includes: a body region, located in the epitaxial layer, the surface of the body region away from the substrate is a partial surface of the epitaxial layer, and the conductivity type of the body region is different from the conductivity type of the epitaxial layer; a first well region, located in the body region, the conductivity type of the first well region is different from the conductivity type of the body region, and the surface of the first well region away from the substrate is a partial surface of the epitaxial layer; a second well region, located in the epitaxial layer, the second well region is adjacent to the first well region, and at least part of the second well region is located in the body region, the surface of the second well region away from the substrate is a partial surface of the epitaxial layer, the conductivity type of the second well region is the same as the conductivity type of the body region, and the doping concentration of the second well region is greater than the doping concentration of the body region, wherein the orthographic projection of the gate in the epitaxial layer overlaps with two adjacent first well regions and two adjacent body regions respectively.
[0008] Optionally, the material of the spacer structure is the same as that of the gate, or the material of the spacer structure is the same as that of the interlayer dielectric layer.
[0009] According to another aspect of the present application, a method for manufacturing the semiconductor structure is provided, comprising: providing a substrate, the substrate comprising a substrate, an epitaxial layer, a plurality of injection regions and a gate, the substrate and the epitaxial layer being stacked in sequence, a plurality of the injection regions being located at intervals in the epitaxial layer, the surface of the injection region away from the substrate being a partial surface of the epitaxial layer, the gate being located on a side of the epitaxial layer away from the substrate and between two adjacent injection regions, the orthographic projection of the gate in the epitaxial layer overlapping with two adjacent injection regions respectively; forming a sacrificial layer on the exposed surface of the substrate, and removing part of the sacrificial layer by a self-alignment process so that the surface of the gate away from the epitaxial layer is exposed, forming a sidewall structure located on the sidewall of the gate, the end of the sidewall structure away from the epitaxial layer having a rounded morphology; forming an interlayer dielectric layer on the exposed surface of the gate and the exposed surface of the sidewall structure; forming a metal layer covering the exposed surface of the interlayer dielectric layer and the exposed surface of each of the injection regions.
[0010] Optionally, the substrate further includes an initial gate oxide layer, which is located between the epitaxial layer and the gate and covers the surface of the epitaxial layer away from the substrate, and a sacrificial layer is formed on the exposed surface of the substrate, including: using chemical vapor deposition to deposit a first material on the exposed surface of the gate and on the surface of the initial gate oxide layer away from the epitaxial layer to form the sacrificial layer, wherein the first material is the same as the material of the gate.
[0011] Optionally, the first material includes polysilicon, and a portion of the sacrificial layer is removed by a self-alignment process so that the gate is exposed away from the surface of the epitaxial layer to form a sidewall structure located on the sidewall of the gate, including: introducing a first mixed gas into a reaction chamber where the substrate with the sacrificial layer is formed, and controlling the temperature of the reaction chamber to 25-300°C to perform anisotropic etching of the sacrificial layer to obtain the sidewall structure, the first mixed gas includes CF4, SF6, Cl2 and HCl, and the etching pressure is 5-30mt.
[0012] Optionally, the substrate further includes a gate oxide layer, the gate oxide layer is located between the epitaxial layer and the gate, the orthographic projection of the gate oxide layer in the epitaxial layer coincides with the orthographic projection of the gate in the epitaxial layer, and a sacrificial layer is formed on the exposed surface of the substrate, including: using chemical vapor deposition to deposit a first material on the exposed surface of the gate and on the sidewalls of the gate oxide layer to form the sacrificial layer, the first material being the same as the material of the interlayer dielectric layer.
[0013] Optionally, the first material includes one of undoped silicate glass, borophosphosilicate glass and phosphosilicate glass, the substrate on which the sacrificial layer is formed is an intermediate structure, and a self-alignment process is used to remove part of the sacrificial layer so that the gate is exposed away from the surface of the epitaxial layer to form a sidewall structure located on the sidewall of the gate, including: introducing a second mixed gas into a reaction chamber where the substrate on which the sacrificial layer is formed is located, and controlling the temperature of the reaction chamber to 25 to 300°C to perform anisotropic etching of the sacrificial layer to obtain the sidewall structure located on the sidewall of the gate and the sidewall of the gate oxide layer, the second mixed gas includes CF4, SF6, CHF3, He, Ar and O2.
[0014] Optionally, a substrate is provided, comprising: providing the stacked substrate and the epitaxial layer, the conductivity type of the epitaxial layer is the same as the conductivity type of the substrate; forming a plurality of spaced body regions in the epitaxial layer, the surface of the body region away from the substrate is a partial surface of the epitaxial layer, and the conductivity type of the body region is different from the conductivity type of the epitaxial layer; forming a first well region in the body region, the conductivity type of the first well region is different from the conductivity type of the body region, and the surface of the first well region away from the substrate is a partial surface of the epitaxial layer; forming a plurality of second well regions in the epitaxial layer, the second well regions corresponding one-to-one with the first well region The epitaxial layer is adjacent to the second well region, and at least part of the second well region is located in the body region, the surface of the second well region away from the substrate is a partial surface of the epitaxial layer, the conductivity type of the second well region is the same as the conductivity type of the body region, the doping concentration of the second well region is greater than the doping concentration of the body region, and the first well region, the second well region and the body region constitute the injection region; a gate layer is formed on the side of the epitaxial layer away from the substrate; the gate layer is patterned to obtain a plurality of spaced gates, and the orthographic projections of the gates in the epitaxial layer overlap with two adjacent first well regions and two adjacent body regions respectively.
[0015] The technical solution of the present application is applied, the substrate and the epitaxial layer are stacked, the gate is located on the side of the epitaxial layer away from the substrate, a plurality of first injection regions are arranged at intervals in the epitaxial layer, the gate is located between two adjacent injection regions and its orthographic projection in the epitaxial layer overlaps with the two adjacent injection regions respectively; a sidewall structure with rounded ends is provided on the sidewall of the gate, an interlayer dielectric layer is provided on the surface of the gate and the sidewall structure, and a metal layer is covered on the surface of the interlayer dielectric layer and each injection region. The present application provides a sidewall structure with rounded tops on the two sidewalls of the gate, which avoids the problem of cracks in the top corners of the gate and the interlayer dielectric layer due to stress in a high temperature difference environment, and ensures the high reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The drawings constituting part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0017] Figure 1 A schematic diagram of the cell structure of a MOSFET active region in the prior art is shown;
[0018] Figure 2 A schematic diagram of a semiconductor structure provided according to an embodiment of the present application is shown;
[0019] Figure 3 A schematic diagram of another semiconductor structure provided according to an embodiment of the present application is shown;
[0020] Figure 4 A schematic flow chart of a method for manufacturing a semiconductor structure provided according to an embodiment of the present application is shown;
[0021] Figure 5 A schematic diagram of a structure obtained after each process step of a method for manufacturing a semiconductor structure provided in an embodiment of the present application is shown;
[0022] Figure 6 A schematic diagram of a structure obtained after each process step according to a method for manufacturing another semiconductor structure provided in an embodiment of the present application is shown.
[0023] The above drawings include the following reference numerals:
[0024] 10. Substrate; 11. Epitaxial layer; 12. Initial gate oxide layer; 13. Injection region; 14. Gate; 15. Sacrificial layer; 16. Sidewall structure; 17. Interlayer dielectric layer; 18. Gate oxide layer; 19. Metal layer; 20. Body region; 21. First well region; 22. Second well region. DETAILED DESCRIPTION
[0025] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0026] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.
[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the accompanying drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0028] As introduced in the background technology, there is a technical problem in the prior art that the reliability of the semiconductor structure is poor. To solve the above technical problem, an embodiment of the present application provides a semiconductor structure and a method for manufacturing the same.
[0029] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.
[0030] The embodiment of the present application provides a semiconductor structure, such as Figure 2 or Figure 3 As shown, the semiconductor structure comprises:
[0031] Substrate 10;
[0032] Specifically, the material of the substrate 10 may be silicon carbide, or other materials such as silicon.
[0033] An epitaxial layer 11 is located on one side surface of the substrate 10;
[0034] A plurality of implantation regions 13 are spaced apart in the epitaxial layer 11, and a surface of the implantation region 13 away from the substrate 10 is a partial surface of the epitaxial layer 11;
[0035] A gate 14 is located on a side of the epitaxial layer 11 away from the substrate 10 and between two adjacent injection regions 13, and an orthographic projection of the gate 14 in the epitaxial layer 11 overlaps with the two adjacent injection regions 13 respectively;
[0036] Specifically, the orthographic projection partially overlaps with two adjacent injection regions 13. There may be a plurality of gate electrodes 14, and the plurality of gate electrodes 14 are arranged at intervals.
[0037] A sidewall structure 16 is located on the sidewall of the gate 14, and the end of the sidewall structure 16 away from the epitaxial layer 11 has a rounded shape;
[0038] Specifically, the sidewall structure is disposed on both sidewalls of the gate 14 .
[0039] An interlayer dielectric layer 17, located on the surface of the gate 14 and the spacer structure 16 away from the epitaxial layer 11 and on the sidewall of the spacer structure 16;
[0040] The metal layer 19 is located on the surface of the interlayer dielectric layer 17 away from the epitaxial layer 11 , on the sidewall of the interlayer dielectric layer 17 , and on a portion of the surface of the implantation region 13 away from the substrate 10 .
[0041] Through the embodiment, the substrate and the epitaxial layer are stacked, the gate is located on the side of the epitaxial layer away from the substrate, a plurality of first injection regions are arranged at intervals in the epitaxial layer, the gate is located between two adjacent injection regions and its orthographic projection in the epitaxial layer overlaps with the two adjacent injection regions respectively; a sidewall structure with a rounded corner at the end is provided on the sidewall of the gate, an interlayer dielectric layer is provided on the surface of the gate and the sidewall structure, and a metal layer is covered on the surface of the interlayer dielectric layer and each injection region. The application provides a sidewall structure with a rounded corner at the top on the two sidewalls of the gate, which avoids the problem of cracks in the top corners of the gate and the interlayer dielectric layer due to stress in a high temperature difference environment, and ensures the high reliability of the semiconductor structure.
[0042] In order to further solve the problem that cracks appear on the top corners of the gate and the interlayer dielectric layer due to stress in a high temperature difference environment, resulting in poor reliability of the semiconductor structure, an optional solution is as follows: Figure 2 or Figure 3 As shown, the end of the interlayer dielectric layer 17 away from the epitaxial layer 11 has a rounded morphology. In the present application, a sidewall structure with a rounded top is provided on the two side walls of the gate, and the top of the interlayer dielectric layer formed on the sidewall structure also has a rounded morphology. The rounded sidewall structure and the interlayer dielectric layer can relieve the stress of the semiconductor structure in a high temperature difference environment, thereby further avoiding the problem of cracks inside the semiconductor structure caused by stress, and the metal layer infiltrating the gate through the cracks to cause a short circuit in the semiconductor structure, further improving the reliability of the semiconductor structure.
[0043] In an exemplary embodiment, Figure 2 or Figure 3As shown, the injection region includes: a body region 20, located in the epitaxial layer 11, the surface of the body region 20 away from the substrate 10 is a partial surface of the epitaxial layer 11, and the conductivity type of the body region 20 is different from the conductivity type of the epitaxial layer 11; a first well region 21, located in the body region 20, the conductivity type of the first well region 21 is different from the conductivity type of the body region 20, and the surface of the first well region 21 away from the substrate 10 is a partial surface of the epitaxial layer 11; a second well region 22, located in the epitaxial layer 11, The second well region 22 is adjacent to the first well region 21, and at least part of the second well region 22 is located in the body region 20, the surface of the second well region 22 away from the substrate 10 is a partial surface of the epitaxial layer 11, the conductivity type of the second well region 22 is the same as the conductivity type of the body region 20, and the doping concentration of the second well region 22 is greater than the doping concentration of the body region 20, wherein the positive projection of the gate 14 in the epitaxial layer 11 overlaps with the two adjacent first well regions 21 and the two adjacent body regions 20 respectively. This embodiment provides an electrode region of a vertical conductive double diffusion power device, so that the current in the structure flows in a direction from the substrate to the epitaxial layer, and the structure has the characteristics of low on-resistance, high switching speed, and high breakdown voltage, and can be applied to high and medium voltage power devices.
[0044] The semiconductor structure of the present application may be a triode, a MOS or an IGBT. When the semiconductor structure is a triode or an IGBT, the first well region may be an emitter region; when the semiconductor structure is a MOS, the first well region may be a source region.
[0045] In some embodiments, Figure 2 As shown, the semiconductor structure further includes: a gate oxide layer 18 located on a portion of the surface of the epitaxial layer 11 away from the substrate 10 , and the gate 14 and the spacer structure 16 are located on a surface of the gate oxide layer 18 away from the epitaxial layer 11 .
[0046] In other embodiments, Figure 3 As shown, the semiconductor structure also includes: a gate oxide layer 18, located on a portion of the surface of the epitaxial layer 11 away from the substrate 10, the gate 14 is located on the surface of the gate oxide layer 18 away from the epitaxial layer 11, and the sidewall structure 16 is located on the sidewalls of the gate 14 and the sidewalls of the gate oxide layer 18.
[0047] In some embodiments, Figure 2 As shown, the material of the spacer structure 16 is the same as that of the gate 14. For example, the materials of the spacer structure 16 and the gate 14 are both polysilicon. Of course, the materials of the spacer structure 16 and the gate 14 can also be other semiconductor conductive materials.
[0048] In other embodiments, Figure 3 As shown, the material of the sidewall structure 16 is the same as the material of the interlayer dielectric layer 17. For example, the material of the sidewall structure 16 and the interlayer dielectric layer 17 are both one of undoped silicate glass, borophosphosilicate glass and phosphosilicate glass. Of course, the material of the sidewall structure 16 and the interlayer dielectric layer 17 can also be other dielectric materials.
[0049] In a specific embodiment, the semiconductor structure is a silicon carbide power device, the substrate is an N-type substrate, the substrate is a conductive silicon carbide substrate, and the resistivity is 10 to 50 mR.cm -1 The epitaxial layer is an N-type epitaxial layer, the material of the epitaxial layer is silicon carbide material, and the doping concentration is 1E15-1E17 cm -3 ; The first well region is an N-type region, the body region is a P-type region, and the second well region is a P-type region.
[0050] Of course, the doping types of the substrate, the epitaxial layer, the first well region, the body region, and the second well region are not limited to the types described.
[0051] The materials of the semiconductor structure of the present application include but are not limited to silicon, silicon carbide, gallium nitride and diamond.
[0052] The embodiment of the present application also provides a method for manufacturing the semiconductor structure. Figure 4 FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application. Figure 4 As shown, the method comprises the following steps:
[0053] Step S201, providing a substrate, such as Figure 5 or Figure 6 As shown, the base includes a substrate 10, an epitaxial layer 11, a plurality of injection regions 13 and a gate 14, the substrate 10 and the epitaxial layer 11 are stacked in sequence, a plurality of the injection regions 13 are spaced apart in the epitaxial layer 11, a surface of the injection region 13 away from the substrate 10 is a partial surface of the epitaxial layer 11, the gate 14 is located on a side of the epitaxial layer 11 away from the substrate 10 and between two adjacent injection regions 13, and an orthographic projection of the gate 14 in the epitaxial layer 11 overlaps with two adjacent injection regions 13 respectively;
[0054] Specifically, the orthographic projection partially overlaps with two adjacent injection regions 13. There may be a plurality of gate electrodes 14, and the plurality of gate electrodes 14 are arranged at intervals.
[0055] Step S202, as Figure 5 or Figure 6As shown, a sacrificial layer 15 is formed on the exposed surface of the substrate, and a portion of the sacrificial layer 15 is removed by a self-alignment process, so that the surface of the gate 14 away from the epitaxial layer 11 is exposed, and a sidewall structure is formed on the sidewall of the gate 14, and the end of the sidewall structure 16 away from the epitaxial layer 11 has a rounded morphology;
[0056] Specifically, the sacrificial layer 15 covers the exposed surface of the gate 14 .
[0057] Step S203, as Figure 5 or Figure 6 As shown, an interlayer dielectric layer 17 is formed on the exposed surface of the gate 14 and the exposed surface of the spacer structure 16;
[0058] Specifically, since the end of the spacer structure 16 has a rounded shape, the end of the interlayer dielectric layer 17 formed on the spacer structure 16 away from the epitaxial layer 11 also has a rounded shape.
[0059] Step S204, as Figure 5 or Figure 6 As shown, a metal layer 19 is formed to cover the exposed surface of the interlayer dielectric layer 17 and the exposed surface of each of the injection regions 13, and the following is obtained: Figure 2 or Figure 3 The semiconductor structure is shown.
[0060] Specifically, the metal layer 19 forms an ohmic contact with the injection region 13 to achieve electrical connection.
[0061] Through the described embodiment, a base including a substrate, an epitaxial layer, a plurality of injection regions and a gate is first provided, wherein the substrate and the epitaxial layer are stacked, the gate is located on a side of the epitaxial layer away from the substrate, the plurality of injection regions are spaced in the epitaxial layer, the gate is located between two adjacent injection regions and its orthographic projection in the epitaxial layer overlaps with the two adjacent injection regions respectively; then a sacrificial layer is formed on the exposed surface of the substrate, and then a portion of the sacrificial layer is removed by a self-alignment process to form a sidewall structure located on the sidewall of the gate and having a rounded corner morphology at the end; then an interlayer dielectric layer is covered on the exposed surface of the gate and the sidewall structure; finally, a metal layer covering the interlayer dielectric layer and the exposed surface of each injection region is formed. The present application forms a sidewall structure with a rounded top shape on the two side walls of the gate through a self-alignment process, which not only avoids the problem of cracks in the top corners of the gate and the interlayer dielectric layer due to stress in a high temperature difference environment, but also ensures the high reliability of the semiconductor structure. Since the self-alignment process does not require an additional mask, nor does it require glue coating, exposure and development process processing, the process is simple and easy to implement. The present application also solves the problem in the prior art that a high-temperature reflow process is needed to process the top corner of the interlayer dielectric layer into a rounded corner, resulting in high process difficulty for the semiconductor structure.
[0062] Specifically, in the present application, the interlayer dielectric layer 17 is formed on the exposed surface of the gate 14 and the exposed surface of the sidewall structure 16. Since the end of the sidewall structure 16 away from the epitaxial layer 11 has a rounded shape, the top of the interlayer dielectric layer 17 formed on the sidewall structure 16 also has a rounded shape. The sidewall structure and the interlayer dielectric layer with rounded shapes can relieve the stress of the semiconductor structure in a high temperature difference environment, thereby further avoiding the problem of cracks inside the semiconductor structure caused by stress, and the metal layer penetrating into the gate through the cracks to cause a short circuit in the semiconductor structure, further improving the reliability of the semiconductor structure.
[0063] In some exemplary embodiments, the thickness of the sacrificial layer may be 0.3-0.5 μm.
[0064] According to an optional solution of the present application, Figure 5 As shown, the substrate also includes an initial gate oxide layer 12, which is located between the epitaxial layer 11 and the gate 14 and covers the surface of the epitaxial layer 11 away from the substrate 10, and a sacrificial layer is formed on the exposed surface of the substrate, including: using chemical vapor deposition to deposit a first material on the exposed surface of the gate 14 and on the surface of the initial gate oxide layer 12 away from the epitaxial layer 11 to form the sacrificial layer 15, wherein the first material is the same as the material of the gate 14. In the embodiment, a relatively uniform, dense and high-quality sacrificial layer film can be obtained by chemical vapor deposition at relatively low temperature and pressure, further ensuring that the production cost of the semiconductor structure is low; in addition, since the material of the sacrificial layer is the same as the gate material, the sidewall structure obtained after the self-alignment process is the same as the material of the gate, and the gate and the sidewall structures on the two side walls together constitute the gate structure of the semiconductor structure. The top angle of the gate structure is relatively smooth, and this morphology is conducive to the rounding effect of the interlayer dielectric layer, which can reduce the sharp corner effect of the gate, further avoiding the problem of cracking of the interlayer dielectric layer of the semiconductor structure at the corner of the gate under high temperature difference testing, further reducing the failure rate of the semiconductor structure under reliability tests such as TCT / TS / PCT, and further improving the stability of the semiconductor structure.
[0065] Furthermore, the first material includes polysilicon, and a part of the sacrificial layer is removed by a self-alignment process, so that the gate is exposed away from the surface of the epitaxial layer, and a sidewall structure is formed on the sidewall of the gate, including: introducing a first mixed gas into the reaction chamber where the substrate with the sacrificial layer is formed, and controlling the temperature of the reaction chamber to 25-300°C to perform anisotropic etching of the sacrificial layer to obtain the sidewall structure, the first mixed gas includes CF4, SF6, Cl2 and HCl, and the etching pressure is 5-30mt. Through the anisotropic etching process, and using fluorine-based compounds and chlorine-based compound gases to dry-etch the sacrificial layer including polysilicon, a gate structure with a rounded corner morphology on the top can be obtained without a mask, the process cost and process difficulty are low, and the uniformity of the two sidewall structures obtained is good, so that the electrical parameters of the semiconductor structure are highly consistent.
[0066] In a more specific embodiment, the materials of the sacrificial layer and the gate are both polysilicon.
[0067] In another alternative, Figure 6 As shown, the substrate also includes a gate oxide layer 18, and the gate oxide layer 18 is located between the epitaxial layer 11 and the gate 14. The orthographic projection of the gate oxide layer 18 in the epitaxial layer 11 coincides with the orthographic projection of the gate 14 in the epitaxial layer 11, that is, the size of the gate oxide layer 18 is the same as the size of the gate 14. A sacrificial layer is formed on the exposed surface of the substrate, including: using a chemical vapor deposition method to deposit a first material on the exposed surface of the gate 14 and on the sidewall of the gate oxide layer 18 to form the sacrificial layer 15, and the first material is the same as the material of the interlayer dielectric layer 17. In the embodiment, a relatively uniform, dense and high-quality sacrificial layer film can be obtained by chemical vapor deposition at a relatively low temperature and pressure, further ensuring that the production cost of the semiconductor structure is low; in addition, since the material of the sacrificial layer is the same as the material of the interlayer dielectric layer, the sidewall structure obtained after the self-alignment process is the same as the material of the interlayer dielectric layer, which is equivalent to forming a double-eared interlayer dielectric structure on the two side walls of the gate. The double-eared interlayer dielectric structure is equivalent to rounding the two corners of the gate, which can reduce the sharp corner effect of the gate, and further avoid the problem of cracking of the interlayer dielectric layer of the semiconductor structure at the corner of the gate under high temperature difference testing, thereby further reducing the failure rate of the semiconductor structure under reliability tests such as TCT / TS / PCT, and further improving the stability of the semiconductor structure.
[0068] Further, the first material includes one of undoped silicate glass, borophosphosilicate glass and phosphosilicate glass, the substrate formed with the sacrificial layer is an intermediate structure, and a part of the sacrificial layer is removed by a self-alignment process, so that the gate is exposed away from the surface of the epitaxial layer, and a sidewall structure located on the sidewall of the gate is formed, including: introducing a second mixed gas into the reaction chamber where the substrate formed with the sacrificial layer is located, and controlling the temperature of the reaction chamber to 25-300°C to perform anisotropic etching of the sacrificial layer to obtain the sidewall structure located on the sidewall of the gate and the sidewall of the gate oxide layer, the second mixed gas includes CF4, SF6, CHF3, He, Ar and O2. Through the anisotropic etching process, the sacrificial layer including undoped silicate glass, borophosphosilicate glass or phosphosilicate glass is dry-etched by using fluorine-based compound gas, inert gas and auxiliary etching gas oxygen, and a sidewall structure with a rounded corner morphology on the top can be obtained without a mask, and the process cost and process difficulty are low, and the consistency of the obtained two sidewall structures is high.
[0069] In a more specific embodiment, the sacrificial layer and the gate are made of the same material, which are undoped silicate glass, borophosphosilicate glass or phosphosilicate glass.
[0070] In some further exemplary embodiments of the present application, Figure 5 or Figure 6As shown, a substrate is provided, comprising: providing the stacked substrate 10 and the epitaxial layer 11, the conductivity type of the epitaxial layer 11 is the same as the conductivity type of the substrate 10; forming a plurality of spaced body regions 20 in the epitaxial layer 11, the surface of the body region 20 away from the substrate 10 is a partial surface of the epitaxial layer 11, and the conductivity type of the body region 20 is different from the conductivity type of the epitaxial layer 11; forming a first well region 21 in the body region 20, the conductivity type of the first well region 21 is different from the conductivity type of the body region 20, and the surface of the first well region 21 away from the substrate 10 is a partial surface of the epitaxial layer 11; forming a plurality of second well regions 22 in the epitaxial layer 11, the second well regions 22 are adjacent to the first well regions 21 one by one , and at least part of the second well region 22 is located in the body region 20, the surface of the second well region 22 away from the substrate 10 is part of the surface of the epitaxial layer 11, the conductivity type of the second well region 22 is the same as the conductivity type of the body region 20, the doping concentration of the second well region 22 is greater than the doping concentration of the body region 20, and the first well region 21, the second well region 22 and the body region 20 constitute the injection region 13; a gate layer (not shown in the figure) is formed on the side of the epitaxial layer 11 away from the substrate 10; the gate layer is patterned to obtain a plurality of gates 14 arranged at intervals, and the orthographic projections of the gates 14 in the epitaxial layer 11 overlap with two adjacent first well regions 21 and two adjacent body regions 20. In the embodiment, the electrode region of the vertical conductive double diffusion power device is formed by two diffusion doping processes, and the current in the structure flows in the direction from the substrate to the epitaxial layer. The structure has the characteristics of small on-resistance, high switching speed and high breakdown voltage, and can be applied to high and medium voltage power devices.
[0071] Specifically, the interlayer dielectric layer, the gate, the gate oxide layer, the sidewall structure, the body regions on both sides of the gate, the second well region and the first well region constitute a cellular structure, and the semiconductor structure may include a plurality of cellular structures. The second well regions in two adjacent cellular structures are adjacent, or two adjacent cellular structures share one second well region.
[0072] The doping concentration of the substrate is greater than the doping concentration of the epitaxial layer. By adjusting the doping concentration and thickness of the epitaxial layer, the withstand voltage and on-resistance of the semiconductor structure can be regulated. Specifically, the lower the doping concentration and the greater the thickness of the epitaxial layer, the higher the withstand voltage and the greater the on-resistance of the semiconductor structure; conversely, the higher the doping concentration and the smaller the thickness, the lower the withstand voltage and the smaller the on-resistance of the semiconductor structure. In addition, the doping concentration of the first well region is greater than the doping concentration of the epitaxial layer, and the doping concentration of the first well region can be greater than or equal to the doping concentration of the substrate.
[0073] In this embodiment, the body region, the first well region and the second well region are obtained by ion implantation of the epitaxial layer at a temperature of 500°C using a mask. The body region, the first well region and the second well region are all made of silicon carbide material, and the junction depth is 0.2-2μm. The initial gate oxide layer can be obtained by thermal diffusion oxidation of the epitaxial layer at a temperature of 1200-1300°C, or by a deposition process. The gate layer can be obtained by chemical vapor deposition, and the thickness of the gate layer can be 0.3-0.5μm. The orthographic projection of the gate obtained by patterning the gate layer using a mask in the epitaxial layer covers the channel of the body region and also overlaps with the first well region. The overlap width of the orthographic projection and the first well region is 0.1-0.5μm, and the overlap width is the overlap width along the arrangement direction of the first well region.
[0074] The semiconductor structure of the present application may be a triode, a MOS or an IGBT. When the semiconductor structure is a triode or an IGBT, the first well region may be an emitter region; when the semiconductor structure is a MOS, the first well region may be a source region.
[0075] Optionally, an interlayer dielectric layer is formed on the exposed surface of the gate and the exposed surface of the sidewall structure, including: forming an initial dielectric layer on the exposed surface of the gate and the exposed surface of the sidewall structure by chemical vapor deposition; removing part of the initial dielectric layer by photolithography and etching processes to form a plurality of grooves, wherein the grooves expose part of the surface of the first well region away from the substrate and the surface of the second well region away from the substrate, and the remaining initial dielectric layer forms a plurality of interlayer dielectric layers.
[0076] In the embodiment, the initial dielectric layer is deposited by a chemical vapor deposition process to obtain an initial dielectric layer of good quality, and then the initial dielectric layer stacked on the surface of the second well region away from the substrate and on the partial surface of the first well region away from the substrate is selectively removed by a photolithography and etching process, so that the partial surface of the first well region away from the substrate is exposed, which is convenient for the subsequent formation of a metal layer in contact with the first well region. The removed initial dielectric layer forms an interlayer dielectric layer covering the gate and the sidewall structure, and the interlayer dielectric layer serves to isolate the gate from the metal layer, thereby preventing the gate from contacting the metal layer and causing a short circuit in the semiconductor structure. In addition, the rounded morphology of the sidewall structure is conducive to the uniform growth of metal material in the groove, reducing the process difficulty of the metal layer, ensuring that the groove can be completely filled with metal material, reducing the holes in the groove, and thus ensuring that the obtained metal layer has a good morphology.
[0077] In some other optional schemes, forming a metal layer covering the exposed surface of the interlayer dielectric layer and the exposed surface of each of the injection regions includes: using physical vapor deposition to deposit metal material on the surface of the interlayer dielectric layer away from the gate, on the sidewall of the gate oxide layer, and in the plurality of the grooves, so that the surface of the metal material away from the epitaxial layer is a plane, thereby obtaining the metal layer. The metal layer is used as an electrode metal wire of the semiconductor structure, and a metal layer with high hardness, wear resistance and corrosion resistance can be obtained through physical vapor deposition process.
[0078] In the case where the semiconductor structure is a MOS, the metal layer can be used as a source lead of the semiconductor structure. The method may also include: depositing a metal material on a surface of the substrate away from the epitaxial layer by physical vapor deposition to obtain a drain lead of the semiconductor structure. The method also includes: depositing a metal material on a side of the substrate away from the epitaxial layer by physical vapor deposition to form a second metal layer. The second metal layer serves as another electrode metal line of the semiconductor structure.
[0079] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.
[0080] From the above description, it can be seen that the embodiments described in this application achieve the following technical effects:
[0081] 2) In the semiconductor structure of the present application, the substrate and the epitaxial layer are stacked, the gate is located on the side of the epitaxial layer away from the substrate, a plurality of first injection regions are arranged at intervals in the epitaxial layer, the gate is located between two adjacent injection regions and its orthographic projection in the epitaxial layer overlaps with the two adjacent injection regions respectively; a sidewall structure with rounded ends is provided on the sidewall of the gate, an interlayer dielectric layer is provided on the surface of the gate and the sidewall structure, and a metal layer is covered on the surface of the interlayer dielectric layer and each injection region. The present application provides a sidewall structure with rounded tops on the two sidewalls of the gate, which avoids the problem of cracks at the top corners of the gate and the interlayer dielectric layer due to stress in a high temperature difference environment, and ensures the high reliability of the semiconductor structure.
[0082] 2) In the manufacturing method of the semiconductor structure of the present application, first, a base including a substrate, an epitaxial layer, a plurality of injection regions and a gate is provided, wherein the substrate and the epitaxial layer are stacked, the gate is located on a side of the epitaxial layer away from the substrate, a plurality of injection regions are spaced in the epitaxial layer, the gate is located between two adjacent injection regions and its orthographic projection in the epitaxial layer overlaps with the two adjacent injection regions respectively; then, a sacrificial layer is formed on the exposed surface of the substrate, and then a portion of the sacrificial layer is removed by a self-alignment process to form a sidewall structure located on the sidewall of the gate and having a rounded corner morphology at the end; then, an interlayer dielectric layer is covered on the exposed surface of the gate and the sidewall structure; finally, a metal layer covering the interlayer dielectric layer and the exposed surface of each injection region is formed. The present application forms a sidewall structure with a rounded top shape on the two side walls of the gate through a self-alignment process, which not only avoids the problem of cracks in the top corners of the gate and the interlayer dielectric layer due to stress in a high temperature difference environment, but also ensures the high reliability of the semiconductor structure. Since the self-alignment process does not require an additional mask, nor does it require glue coating, exposure and development process processing, the process is simple and easy to implement. The present application also solves the problem in the prior art that a high-temperature reflow process is needed to process the top corner of the interlayer dielectric layer into a rounded corner, resulting in high process difficulty for the semiconductor structure.
[0083] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A semiconductor structure, characterized in that: include: substrate; An epitaxial layer, located on one side surface of the substrate; A plurality of implantation regions are spaced apart in the epitaxial layer, and the surface of the implantation region away from the substrate is a partial surface of the epitaxial layer; A gate, located at a side of the epitaxial layer away from the substrate and between two adjacent injection regions, wherein an orthographic projection of the gate in the epitaxial layer overlaps with the two adjacent injection regions respectively; A sidewall structure, located on a sidewall of the gate, wherein an end of the sidewall structure away from the epitaxial layer has a rounded shape; An interlayer dielectric layer, located on the surface of the gate and the sidewall structure away from the epitaxial layer and on the sidewall of the sidewall structure; The metal layer is located on the surface of the interlayer dielectric layer away from the epitaxial layer, on the sidewall of the interlayer dielectric layer, and on a portion of the surface of the implantation region away from the substrate.
2. The semiconductor structure according to claim 1, characterized in that: The end of the interlayer dielectric layer away from the epitaxial layer has a rounded shape.
3. The semiconductor structure according to claim 1, characterized in that: The injection region comprises: A body region, located in the epitaxial layer, wherein a surface of the body region away from the substrate is a partial surface of the epitaxial layer, and a conductivity type of the body region is different from a conductivity type of the epitaxial layer; A first well region is located in the body region, the conductivity type of the first well region is different from the conductivity type of the body region, and the surface of the first well region away from the substrate is a partial surface of the epitaxial layer; a second well region, located in the epitaxial layer, the second well region is adjacent to the first well region, and at least a portion of the second well region is located in the body region, a surface of the second well region away from the substrate is a partial surface of the epitaxial layer, a conductivity type of the second well region is the same as a conductivity type of the body region, and a doping concentration of the second well region is greater than a doping concentration of the body region, The orthographic projection of the gate in the epitaxial layer overlaps with two adjacent first well regions and two adjacent body regions respectively.
4. The semiconductor structure according to claim 1, characterized in that The material of the spacer structure is the same as that of the gate, or the material of the spacer structure is the same as that of the interlayer dielectric layer.
5. A method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: include: Providing a substrate, the substrate comprising a substrate, an epitaxial layer, a plurality of injection regions and a gate, the substrate and the epitaxial layer are stacked in sequence, the plurality of injection regions are spaced apart in the epitaxial layer, the surface of the injection region away from the substrate is a partial surface of the epitaxial layer, the gate is located on a side of the epitaxial layer away from the substrate and between two adjacent injection regions, and the orthographic projection of the gate in the epitaxial layer overlaps with the two adjacent injection regions respectively; A sacrificial layer is formed on the exposed surface of the substrate, and a portion of the sacrificial layer is removed by a self-alignment process, so that the surface of the gate away from the epitaxial layer is exposed, and a sidewall structure is formed on the sidewall of the gate, wherein the end of the sidewall structure away from the epitaxial layer has a rounded morphology; forming an interlayer dielectric layer on an exposed surface of the gate and an exposed surface of the spacer structure; A metal layer is formed to cover the exposed surface of the interlayer dielectric layer and the exposed surfaces of each of the implantation regions.
6. The method according to claim 5, characterized in that The substrate further includes an initial gate oxide layer, the initial gate oxide layer is located between the epitaxial layer and the gate and covers the surface of the epitaxial layer away from the substrate, and a sacrificial layer is formed on the exposed surface of the substrate, including: A first material is deposited on the exposed surface of the gate and on the surface of the initial gate oxide layer away from the epitaxial layer by chemical vapor deposition to form the sacrificial layer, wherein the first material is the same as that of the gate.
7. The method according to claim 6, characterized in that The first material includes polysilicon, and a portion of the sacrificial layer is removed by a self-alignment process so that the gate is exposed away from the surface of the epitaxial layer, forming a sidewall structure located on the sidewall of the gate, including: A first mixed gas is introduced into the reaction chamber where the substrate with the sacrificial layer is formed, and the temperature of the reaction chamber is controlled to be 25-300°C to perform anisotropic etching of the sacrificial layer to obtain the side wall structure, wherein the first mixed gas includes CF4, SF6, Cl2 and HCl, and the etching pressure is 5-30mt.
8. The method according to claim 5, characterized in that The substrate further includes a gate oxide layer, the gate oxide layer is located between the epitaxial layer and the gate, the orthographic projection of the gate oxide layer in the epitaxial layer coincides with the orthographic projection of the gate in the epitaxial layer, and a sacrificial layer is formed on the exposed surface of the substrate, including: A first material is deposited on the exposed surface of the gate and on the sidewall of the gate oxide layer by chemical vapor deposition to form the sacrificial layer, wherein the first material is the same as the material of the interlayer dielectric layer.
9. The method according to claim 8, characterized in that The first material includes one of undoped silicate glass, borophosphosilicate glass and phosphosilicate glass, the substrate on which the sacrificial layer is formed is an intermediate structure, and a portion of the sacrificial layer is removed by a self-alignment process so that the gate is exposed away from the surface of the epitaxial layer, forming a sidewall structure located on the sidewall of the gate, including: A second mixed gas is introduced into the reaction chamber where the substrate with the sacrificial layer is formed, and the temperature of the reaction chamber is controlled to be 25-300°C to perform anisotropic etching of the sacrificial layer to obtain the sidewall structure located on the sidewall of the gate and the sidewall of the gate oxide layer, wherein the second mixed gas includes CF4, SF6, CHF3, He, Ar and O2.
10. The method according to any one of claims 5 to 9, characterized in that A substrate is provided, comprising: Providing the stacked substrate and the epitaxial layer, wherein the conductivity type of the epitaxial layer is the same as that of the substrate; forming a plurality of spaced body regions in the epitaxial layer, wherein the surface of the body region away from the substrate is a partial surface of the epitaxial layer, and the conductivity type of the body region is different from the conductivity type of the epitaxial layer; forming a first well region in the body region, wherein the conductivity type of the first well region is different from the conductivity type of the body region, and a surface of the first well region away from the substrate is a partial surface of the epitaxial layer; A plurality of second well regions are formed in the epitaxial layer, the second well regions are adjacent to the first well regions in a one-to-one correspondence, and at least a portion of the second well regions is located in the body region, a surface of the second well region away from the substrate is a partial surface of the epitaxial layer, a conductivity type of the second well region is the same as a conductivity type of the body region, a doping concentration of the second well region is greater than a doping concentration of the body region, and the first well region, the second well region and the body region constitute the injection region; forming a gate layer on a side of the epitaxial layer away from the substrate; The gate layer is patterned to obtain a plurality of gates arranged at intervals, wherein the orthographic projections of the gates in the epitaxial layer overlap with two adjacent first well regions and two adjacent body regions respectively.