Chip burning method and system

Abstract

The invention relates to a chip burning method which is applied to a chip on each level of burning seat. The first programming interface of each stage of burning seat is connected with the second programming interface or burning equipment of the previous stage of burning seat to form a cascade burning link; the method comprises the following steps: receiving burning data through a first programming interface of the burning seat at the level; writing the burning data into a storage space of a home terminal; a cascade burning program in the burning data is loaded from the storage space of the home terminal; and executing a cascade burning program, and issuing the burning data through the second programming interface of the burning seat at the same level, so that the burning data is issued step by step along the cascade burning link, and the burning of the chips on the burning seats at all levels in the cascade burning link is further realized. By adopting the method, the chip burning cost can be reduced.

Description

Technical Field

[0001] This application relates to the field of chip programming technology, and in particular to a chip programming method and system. Background Technology

[0002] In the chip manufacturing process, the chip programming stage is crucial. In this stage, by burning the written program code into the chip, the chip can be endowed with various functions such as controlling peripheral circuits, processing sensor data, performing logical judgments, or interacting with users.

[0003] In traditional technology, chips are programmed in parallel through multiple channels using a programming device. However, the number of channels supported by the programming device is fixed, and the number of programmable chips can only be expanded by adding more programming devices. Therefore, to program chips in batches, a large number of programming devices are often required, resulting in high chip programming costs. Summary of the Invention

[0004] Therefore, it is necessary to provide a chip programming method and system that can reduce costs in response to the above-mentioned technical problems.

[0005] In a first aspect, this application provides a chip programming method applied to chips on each programming socket; the first programming interface of each programming socket is connected to the second programming interface of the upper-level programming socket or a programming device to form a cascaded programming link; the method includes: Receive programming data through the first programming interface of this programming socket; Write the programmed data into the local storage space; Load the cascaded burning program from the burning data in the storage space of the local terminal; The cascaded programming program is executed, and the programming data is sent down through the second programming interface of the current programming socket, so that the programming data is sent down step by step along the cascaded programming link, thereby realizing the programming of the chips on each programming socket in the cascaded programming link.

[0006] Secondly, this application also provides a chip programming system, the system including a programming device and chips on each programming socket; wherein, the first programming interface of the first programming socket is connected to the programming device, and the first programming interface of each subsequent programming socket is connected to the second programming interface of the next higher programming socket, forming a cascaded programming link; the system is used to implement the steps in the above method.

[0007] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method.

[0008] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the above-described method.

[0009] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps in the above-described method.

[0010] In the aforementioned chip programming method, system, computer equipment, storage medium, and computer program product, the chip on each programming socket receives programming data through the first programming interface of its own programming socket. Since the first programming interface of each programming socket is connected to the second programming interface of the next higher programming socket or programming device, forming a cascaded programming link, the programming data originates from the chip or programming device on the next higher programming socket. The chip on each programming socket writes the programming data into its own storage space, thus completing the programming process. Furthermore, the chip on each programming socket loads the cascaded programming program from its own storage space, enabling cascaded programming capability. Therefore, the chip on each programming socket executes the cascaded programming program and sends programming data through the second programming interface of its own programming socket, allowing the programming data to be sent down level by level along the cascaded programming link, thereby achieving programming of the chips on each programming socket in the cascaded programming link. By using cascading programming programs in the programming data, the chips on each programming socket are given the ability to program the chips on the next programming socket. Because the chips on each programming socket have the ability to program the chips on the next programming socket, the number of programmable chips can be expanded simply by adding cascading programming sockets in the cascading programming chain. This eliminates the need for a large number of programming devices and greatly reduces the cost of chip programming. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic flowchart of a chip programming method provided in an embodiment of this application.

[0013] Figure 2 This is a schematic diagram of each interface of a programming socket at each stage, provided for an embodiment of this application.

[0014] Figure 3 This is a simplified flowchart illustrating a chip programming method provided in an embodiment of this application.

[0015] Figure 4A This is a structural block diagram of a chip programming system provided in an embodiment of this application.

[0016] Figure 4B This is a structural block diagram of another chip programming system provided in an embodiment of this application.

[0017] Figure 5 This is an internal structural diagram of a programming device provided in an embodiment of this application.

[0018] Figure 6 This is an internal structure diagram of a host computer provided in an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0020] In one exemplary embodiment, such as Figure 1 As shown, a schematic flowchart of a chip programming method is provided. Taking the application of this method to the chip on each programming socket as an example, the method includes the following steps 102 to 108.

[0021] Step 102: Receive programming data through the first programming interface of the current programming socket; wherein, the first programming interface of each programming socket is connected to the second programming interface of the upper-level programming socket or the programming device to form a cascaded programming link.

[0022] It can be understood that the first programming interface of each programming socket is used to receive programming data. The second programming interface of each programming socket is used to send programming data. For each programming socket, the upper-level programming socket refers to the programming socket whose first programming interface is connected to; it is also the programming socket that is closer to the programming device and connected to the current programming socket in the cascaded programming chain. The first programming interface of the first-level programming socket is connected to the programming device. The programming device is a device specifically used for programming chips.

[0023] For example, for the chip on the first-level programming socket, the chip can receive programming data sent by the programming device through the first programming interface of the programming socket. For the chips on each subsequent programming socket, the chip can receive programming data sent by the chip on the previous programming socket through the second programming interface of the previous programming socket through the first programming interface of the programming socket.

[0024] In some embodiments, the first programming interface or the second programming interface may be, but is not limited to, at least one of the following: a Joint Test Action Group (JTAG) interface, a Serial Wire Debug (SWD) interface, a Universal Asynchronous Receiver Transmitter (UART) interface, or a Universal Serial Bus (USB) interface.

[0025] In some embodiments, a programming device can be connected to at least one programming socket. Each programming socket has a first programming interface that supports connection to a higher-level programming socket or programming device. Each programming socket has at least two second programming interfaces that support connection to at least two lower-level programming sockets. Therefore, in a cascaded programming chain, a programming device can be connected to the first programming interface of at least one first-level programming socket, each programming socket can be connected to at least two lower-level programming sockets, and each programming socket after the first level is connected to a higher-level programming socket.

[0026] In a cascaded programming chain, the programming device can program at least one chip on a primary programming socket, and the chip on each programming socket can further program at least two chips on lower programming sockets. Obviously, simply adding cascaded programming sockets to the cascaded programming chain can expand the number of programmable chips. Compared to adding programming devices to expand the number of programmable chips, this greatly reduces the cost of chip programming.

[0027] Step 104: Write the burned data into the local storage space.

[0028] For example, the chip on each programming socket can use a bootloader to write programming data into its local storage space. This storage space can be space within flash memory.

[0029] Step 106: Load the cascading programming program from the programming data in the local storage space.

[0030] For example, the chip on each programming socket can use a bootloader to load the cascaded programming program from the programming data in the local storage space.

[0031] In some embodiments, the chip on each programming socket can extract the cascade programming program from the programming data in its local storage space and load the cascade programming program into a buffer area. The buffer area can be a region in random access memory (RAM).

[0032] Step 108: Execute the cascade programming program and send programming data through the second programming interface of the current programming socket so that the programming data is sent down level by level along the cascade programming link, thereby realizing the programming of the chips on each programming socket in the cascade programming link.

[0033] For example, the chip on each programming socket can jump from the bootloader to the cascaded programming program in the buffer area and execute the cascaded programming program. Using the cascaded programming program, programming data is sent to the second programming interface of the current programming socket, and then the programming data is transmitted to the first programming interface of the next programming socket through the second programming interface of the current programming socket. This allows the chip on the next programming socket to receive programming data based on the first programming interface of the next programming socket, thereby realizing the programming of the chip on the next programming socket.

[0034] In the above chip programming method, the chip on each programming socket receives programming data through the first programming interface of that socket. Since the first programming interface of each programming socket is connected to the second programming interface of the next higher programming socket or the programming device, forming a cascaded programming link, the programming data comes from the chip or programming device on the next higher programming socket. The chip on each programming socket writes the programming data into its local storage space, thus realizing programming at that end. Then, the chip on each programming socket loads the cascaded programming program from its local storage space, enabling it to have cascaded programming capabilities. Therefore, the chip on each programming socket executes the cascaded programming program and sends programming data through the second programming interface of that socket, so that the programming data is sent down level by level along the cascaded programming link, thereby realizing the programming of the chips on each programming socket in the cascaded programming link. By using cascading programming programs in the programming data, the chips on each programming socket are given the ability to program the chips on the next programming socket. Because the chips on each programming socket have the ability to program the chips on the next programming socket, the number of programmable chips can be expanded simply by adding cascading programming sockets in the cascading programming chain. This eliminates the need for a large number of programming devices and greatly reduces the cost of chip programming.

[0035] In some embodiments, the first communication interface of each programming socket is connected to the second communication interface of the upper-level programming socket or a host computer to form a cascaded communication link. After sending programming data through the second programming interface of the current programming socket, the method further includes: receiving downstream chip data through the second communication interface of the current programming socket; the downstream chip data comes from the chips on each level of programming socket downstream of the current programming socket in the cascaded communication link; and reporting the downstream chip data through the first communication interface of the current programming socket so that the downstream chip data is reported to the host computer level by level along the cascaded communication link.

[0036] Among them, each level of programming socket downstream of the current programming socket refers to a programming socket located in the branch where the current programming socket is located in the cascaded programming link, and which is farther away from the programming device or host computer than the current programming socket.

[0037] For example, each programming socket has a first communication interface, a second communication interface, a first programming interface, and a second programming interface. The first communication interface of the first programming socket is connected to the host computer, and the first programming interface of the first programming socket is connected to the programming device. The first communication interface of each subsequent programming socket is connected to the second communication interface of the preceding programming socket, and the first programming interface of each subsequent programming socket is connected to the second programming interface of the preceding programming socket, forming a cascaded programming link and a cascaded communication link.

[0038] The cascaded programming program can include a communication subroutine. The chip on each programming socket can use the communication subroutine to receive data from the downstream chip through the second communication interface of the programming socket at that level, and to report data from the downstream chip through the first communication interface of the programming socket at that level, so that the data from the downstream chip is reported to the host computer level by level along the cascaded communication link.

[0039] In some embodiments, the first communication interface or the second communication interface may be, but is not limited to, at least one of a Universal Asynchronous Receiver Transmitter (UART) interface, a Universal Serial Bus (USB) interface, or an Ethernet interface. The communication subroutine may be responsible for implementing the communication protocol rules of the first communication interface and the second communication interface.

[0040] In some embodiments, the cascade programming program may include a communication subroutine and a programming subroutine. The communication subroutine is used for data flow control of the cascaded communication link. The programming subroutine is used for data flow control of the cascaded programming link. It can be understood that the communication subroutine enables the chip on each programming socket to communicate with the chips on each programming socket in the cascaded communication link and with the host computer. The programming subroutine enables the chip on each programming socket to further program the chips on the next programming socket in the cascaded programming link.

[0041] In some embodiments, the host computer may be, but is not limited to, a computer device.

[0042] In this embodiment, the first communication interface of each programming socket is connected to the second communication interface of the next higher programming socket or a host computer, forming a cascaded communication link. The second communication interface of the current programming socket receives downstream chip data; this downstream chip data originates from chips on each subsequent programming socket downstream of the current programming socket in the cascaded communication link. The first communication interface of the current programming socket reports downstream chip data, ensuring that downstream chip data is reported to the host computer level by level along the cascaded communication link. The cascaded communication link and the cascaded programming link are two isolated links, allowing for simultaneous reporting of downstream chip data while programming data is being sent down in the cascaded programming link, thus ensuring efficient chip programming.

[0043] In some embodiments, downstream chip data includes lower-level chip data used to characterize the programming status of chips on lower-level programming sockets; receiving downstream chip data through the second communication interface of the current programming socket includes: sending a current-level read command through the second communication interface of the current programming socket; and receiving lower-level chip data reported by chips on lower-level programming sockets in response to the current-level read command through the second communication interface of the current programming socket.

[0044] Among them, the lower-level programming socket refers to the programming socket that is farther away from the programming device or host computer than the programming socket of this level in the cascaded programming link, but is connected to the programming socket of this level.

[0045] For example, the chip on each programming socket can use a communication subroutine to send a read command through the second communication interface of the programming socket, and receive data from the chip on the next lower-level programming socket in response to the read command through the second communication interface of the programming socket, and also report data from the next lower-level chip through the first communication interface of the programming socket. It can be understood that the data from the next lower-level chip reported by the programming socket is considered downstream chip data from the perspective of the chip on the next higher-level programming socket.

[0046] In some embodiments, the chip on each programming socket can receive read commands from the upper level through the first communication interface of the programming socket using a communication subroutine, and report its own chip data in response to the upper level read commands through the first communication interface of the programming socket. It can be understood that, for the chip on the upper level programming socket, the upper level read command is the same as the current level read command.

[0047] In this embodiment, downstream chip data includes lower-level chip data used to characterize the programming status of chips on lower-level programming sockets. A read command is sent through the second communication interface of the current programming socket, and the lower-level chip data reported by the chips on the lower-level programming sockets in response to the read command is received through the second communication interface of the current programming socket. This allows for the collection and reporting of data from chips on lower-level programming sockets by chips on each level of the programming socket, ultimately aggregating the data on the host computer. This enables timely feedback on the programming status of chips on each level of the programming socket, ensuring efficient chip programming.

[0048] In some embodiments, each programming socket has at least two sets of interfaces, each set of interfaces including a second programming interface and a second communication interface; the same lower-level programming socket is connected to the same set of interfaces of each programming socket; sending programming data through the second programming interface of the current programming socket includes: for each set of interfaces, sending programming data through the second programming interface in the current set of interfaces; sending a read command for the current level through the second communication interface of the current programming socket includes: sending a read command for the current level through the second communication interface in the current set of interfaces; receiving lower-level chip data reported by the chip on the lower-level programming socket in response to the read command for the current level through the second communication interface of the current programming socket includes: receiving lower-level chip data reported by the chip on the lower-level programming socket in response to the read command for the current level through the second communication interface in the current set of interfaces.

[0049] Specifically, for each programming socket, the first programming interface of the lower-level programming socket is connected to the second programming interface in a set of interfaces of the same level programming socket, and the first communication interface of the lower-level programming socket is connected to the second communication interface in that set of interfaces. It can be understood that since the first communication interface of the first-level programming socket is connected to the host computer, and the first programming interface of the first-level programming socket is connected to the programming device, each subsequent programming socket will be connected to the same set of interfaces of the higher-level programming socket. That is, for each subsequent programming socket, the first programming interface of the current level programming socket is connected to the second programming interface in a set of interfaces of the higher-level programming socket, and the first communication interface of the current level programming socket is connected to the second communication interface in that set of interfaces of the higher-level programming socket.

[0050] In some embodiments, such as Figure 2 The diagram shows a schematic of the interfaces for each programming socket. Each programming socket has at least two sets of interfaces. Each set of interfaces includes a second programming interface and a second communication interface. The second programming interface and the second communication interface in each set of interfaces can be adjacent, for example, Figure 2 The second programming interface x1 and the second communication interface y1 are in the same group, as are the second programming interface xn and the second communication interface yn. Each programming socket has one first programming interface X and one first communication interface Y. It can be understood that setting only one first programming interface and one first communication interface per programming socket is to ensure the uniqueness of the uplink path, thereby ensuring the reliability of data reported by the chip on each programming socket during the chip programming process. Setting at least two sets of interfaces per programming socket is to ensure the scalability of the downlink path, thereby enabling the chip on each programming socket to batch program the chips on the next programming socket, ensuring the efficiency of chip programming.

[0051] In some embodiments, the chip on each programming socket can traverse at least two sets of interfaces. For the interface in this set that is traversed, programming data is sent through the second programming interface in this set of interfaces.

[0052] In this embodiment, each programming socket has at least two sets of interfaces, each set including a second programming interface and a second communication interface. Lower-level programming sockets are connected to the same set of interfaces. For each set of interfaces, programming data is sent through the second programming interface; a read command is sent through the second communication interface; and lower-level chip data reported by the chip on the lower-level programming socket in response to the read command is received through the second communication interface. This ensures that the chip on each programming socket can program and communicate with the chip on the lower-level programming socket through a single set of interfaces, guaranteeing the accuracy of chip programming.

[0053] In some embodiments, the programming data includes the number of programming permissions; the cascaded programming program includes a programming subroutine; for each group of interfaces, programming data is sent through the second programming interface in this group of interfaces, including: if the number of programming permissions is greater than zero, the programming subroutine is used to traverse each group of interfaces of this level programming socket, and programming data is sent through the second programming interface in this group of interfaces traversed; downstream chip data is reported through the first communication interface of this level programming socket, including: if the data of the lower-level chip indicates successful programming, the number of programming permissions is decremented by 1, and the data of the lower-level chip is reported through the first communication interface of this level programming socket; after reporting the data of the lower-level chip, if the traversal is not finished, the step of traversing each group of interfaces of this level programming socket using the programming subroutine if the number of programming permissions is greater than zero is returned.

[0054] The programming permission count indicates the number of chips that each programming socket has the permission to program. It can be understood that each time a chip in a lower-level programming socket is successfully programmed, the programming permission count is decremented by 1. That is, programming permission counts are only consumed when a chip is successfully programmed. This avoids wasting programming permission counts on faulty chips in lower-level programming sockets, thus conserving programming permission resources.

[0055] For example, the chip on each programming socket can determine whether the number of programming permissions stored on the local end is greater than zero. If so, it calls the programming subroutine to traverse each group of interfaces on the current programming socket and sends programming data through the second programming interface in the traversed group. It can be understood that the programming capability of the chip on each programming socket is based on the programming subroutine. If the number of programming permissions is greater than zero, the programming subroutine can be called to perform the function of programming downwards; if the number of programming permissions is not greater than zero, the call to the programming subroutine is restricted.

[0056] The chip on each programming socket can send a read command to the current level via the second communication interface in its group, and receive data from the chip on the next lower programming socket in response to the read command through the same second communication interface. The data from the next lower chip and the programming data are matched. If a match is found, programming is successful, the programming permission count is decremented by 1, and the data from the next lower chip is reported through the first communication interface of the current programming socket. After reporting the data from the next lower chip, if the traversal of all groups of interfaces on the current programming socket is not yet complete, the process returns to check if the number of programming permission counts stored locally is greater than zero. If so, the programming subroutine is used to traverse all groups of interfaces on the current programming socket.

[0057] In this embodiment, the programming data includes programming permission counts, which can limit the programming capability of chips on each programming socket, ensuring security. Furthermore, the programming permission counts can also serve as a metric for successfully programmed chips, ensuring the reliability of batch programming. The cascaded programming program includes programming subroutines. If the programming permission count is greater than zero, the programming subroutine traverses each group of interfaces on the current programming socket, sending programming data through the second programming interface in the traversed group. If the data from the next-level chip indicates successful programming, the programming permission count is decremented by 1. Programming permission counts are only consumed when a chip is successfully programmed, preventing wasted counts on failed programming and conserving programming permission resources. The data from the next-level chip is reported through the first communication interface of the current programming socket, enabling timely feedback on the programming status of chips on each programming socket and ensuring efficient chip programming. After reporting the data of the lower-level chip, if the traversal is not finished, return. If the number of programming permissions is greater than zero, use the programming subroutine to traverse the steps of each group of interfaces of the current programming socket to ensure that the chips on each programming socket can fully program the chips on the lower-level programming socket.

[0058] In some embodiments, the chip on each programming socket can report permission-related information through the first communication interface of its respective programming socket, so that the permission-related information is reported to the host computer level by level along the cascading communication link. The permission-related information may include permission deficiency information.

[0059] In some embodiments, the method further includes: if the number of burning permissions is not greater than zero, then reporting insufficient permission information through the first communication interface of the current burning socket, so that the insufficient permission information is reported to the host computer level by level along the cascaded communication link; and receiving new burning permission counts from the host computer and sent down along the cascaded communication link through the first communication interface of the current burning socket.

[0060] For example, the chip on each programming socket can determine whether the number of programming permission attempts is greater than zero. If not, it reports insufficient permission information through the first communication interface of its own programming socket, so that the insufficient permission information is reported to the host computer level by level along the cascading communication link. After receiving the insufficient permission information, the host computer can issue a new number of programming permission attempts through the cascading communication link, so that the chip on each programming socket can receive the new number of programming permission attempts through the first communication interface of its own programming socket.

[0061] In this embodiment, if the number of programming permissions is not greater than zero, the insufficient permission information is reported through the first communication interface of the current programming socket, so that the insufficient permission information is reported to the host computer level by level along the cascaded communication link; through the first communication interface of the current programming socket, the new number of programming permissions sent from the host computer along the cascaded communication link can be received, so as to realize that when the permissions are insufficient, the new number of programming permissions allocated by the host computer can be obtained, thereby ensuring sufficient number of programming permissions during the process of programming the chip on the next programming socket, thus ensuring the efficiency of chip programming.

[0062] In some embodiments, sending programming data through the second programming interface in the traversed group of interfaces includes: sending an initialization command through the second programming interface in the traversed group of interfaces to instruct the chip on the lower-level programming socket connected to the second programming interface to enter programming mode and return response data; if response data is received through the second programming interface in the group of interfaces, then sending programming data through the second programming interface in the group of interfaces; if no response data is received and the traversal is not finished, then returning to the step of traversing each group of interfaces of the current programming socket using a programming subroutine if the number of programming permission attempts is greater than zero.

[0063] The response data is the data used to respond to the initialization command.

[0064] It is understandable that, since each programming socket has at least two sets of interfaces, and it is unknown which set of interfaces is connected to the next programming socket with the chip installed, the chip on each programming socket needs to send an initialization command based on the second programming interface in each set of interfaces to detect whether the second programming interface is connected to the next programming socket with the chip installed before it can further program the chip on the next programming socket.

[0065] In some embodiments, the chip on each programming socket can receive an initialization command through the first programming interface of the programming socket and return response data through the first programming interface of the programming socket.

[0066] In this embodiment, an initialization command is sent through the second programming interface in the current group of interfaces to instruct the chip on the lower-level programming socket connected to the second programming interface to enter the programming mode and return response data. If response data is received through the second programming interface in the current group of interfaces, programming data is sent through the second programming interface in the current group of interfaces. If no response data is received and the traversal is not finished, the process returns if the number of programming permission attempts is greater than zero. Then, the programming subroutine is used to traverse each group of interfaces of the current programming socket. Programming data is sent only when a chip on the lower-level programming socket is detected, which can avoid resource waste.

[0067] In some embodiments, the method further includes: after the traversal is completed, reporting the end information of the current level's programming through the first communication interface of the current programming socket, so that the end information of the current level's programming is reported to the host computer level by level along the cascading communication link; receiving the current level's programming stop command from the host computer and sent along the cascading communication link through the first communication interface of the current programming socket; and responding to the current level's programming stop command by setting the programming subroutine to an unexecutable state.

[0068] The current programming completion information indicates that the chip in the current programming socket has finished programming the chip in the next programming socket. The unexecutable state refers to the state where the programming subroutine cannot be executed.

[0069] For example, after the chip on each programming socket has completed traversing all groups of interfaces on that programming socket, it reports the programming completion information of that level through the first communication interface of that programming socket. This allows the programming completion information of that level to be reported to the host computer level by level through the chips on each of the upstream programming sockets. The host computer can issue a programming stop command for that level through the cascaded communication link, instructing the chip on that programming socket to set the programming subroutine to an unexecutable state by modifying the status flag bit after receiving the programming stop command through the first communication interface of that programming socket.

[0070] In this embodiment, after the traversal is completed, the end-of-programming information of this level is reported through the first communication interface of the current programming socket, so that the end-of-programming information of this level is reported to the host computer level by level along the cascading communication link; the end-of-programming stop command of this level is received from the host computer and sent down along the cascading communication link through the first communication interface of the current programming socket; in response to the end-of-programming stop command of this level, the programming subroutine is set to an unexecutable state, and the programming subroutine is restricted in a timely manner after the end-of-programming of this level, thus ensuring security.

[0071] In some embodiments, reporting downstream chip data through the first communication interface of the local programming socket includes: if the data of the lower-level chip indicates a programming failure, returning to the step of sending programming data through the second programming interface of the local programming socket, until the repeated programming stop condition is met, and then reporting the lower-level chip data through the first communication interface of the local programming socket.

[0072] For example, the chip on each programming socket can match the data of the next-level chip with the programming data. If the matching fails, it means that the programming has failed. The process returns to the second programming interface of the programming socket to send the programming data. This process continues until the number of loops reaches the number of repeated programming attempts or the data of the next-level chip indicates that the programming has been successful. Then, the data of the next-level chip is reported through the first communication interface of the programming socket.

[0073] In this embodiment, if the lower-level chip data characterization fails to be programmed, the process returns to the step of sending programming data through the second programming interface of the current programming socket until the repeated programming stop condition is met. Then, the lower-level chip data is reported through the first communication interface of the current programming socket. This can improve the programming success rate of the chip on the lower-level programming socket through a limited number of repeated programming attempts.

[0074] In some embodiments, such as Figure 3 The diagram shows a simplified flowchart of the chip programming method.

[0075] Step 302: The chip on the first programming socket receives programming data from the programming device through the first programming interface of the programming socket; the chips on each subsequent programming socket receive programming data from the chip on the previous programming socket through the first programming interface of the programming socket.

[0076] Step 304: The chip on each programming socket uses the bootloader to write programming data into the local storage space; the cascading programming program is extracted from the programming data in the local storage space and loaded into the buffer area; the bootloader jumps to the cascading programming program in the buffer area and executes the cascading programming program.

[0077] Step 306: If the number of programming permissions for the chip on each programming socket is greater than zero, the programming subroutine will traverse each group of interfaces of the current programming socket and send an initialization command through the second programming interface in the traversed group of interfaces to instruct the chip on the next programming socket connected to the second programming interface to enter the programming mode and return response data.

[0078] Step 308: If the chip on each programming socket receives response data through the second programming interface in this group, then the programming data is sent out through the second programming interface in this group; if no response data is received and the traversal of each group of interfaces is not finished, then return to the step of traversing each group of interfaces of this programming socket using the programming subroutine if the number of programming permission attempts is greater than zero.

[0079] Step 310: After the chip on each programming socket sends the programming data, it sends the reading command for this level through the second communication interface in this group interface; and receives the data of the lower-level chip reported by the chip on the lower-level programming socket in response to the reading command for this level through the second communication interface in this group interface.

[0080] Step 312: If the data representation of the lower-level chip is successfully programmed, the programming permission count is decremented by 1, and the lower-level chip data is reported through the first communication interface of the programming socket. If the data representation of the lower-level chip fails to program, the process returns to the step of sending programming data through the second programming interface of the programming socket, until the repeated programming stop condition is met, and then the lower-level chip data is reported through the first communication interface of the programming socket.

[0081] Step 314: After the chip on each programming socket reports the data of the next-level chip, if the traversal of each group of interfaces is not finished, return to the step of traversing each group of interfaces of the current programming socket using the programming subroutine if the number of programming permission counts is greater than zero.

[0082] Step 316: After the chips on each programming socket have finished traversing each group of interfaces, they report the programming completion information of this level through the first communication interface of this programming socket, so that the programming completion information of this level is reported to the host computer level by level along the cascading communication link; through the first communication interface of this programming socket, it receives the programming stop command of this level from the host computer and sent down along the cascading communication link; in response to the programming stop command of this level, it sets the programming subroutine to an unexecutable state.

[0083] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0084] Based on the same inventive concept, this application also provides a chip programming system for implementing the chip programming method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more chip programming system embodiments provided below can be found in the limitations of the chip programming method described above, and will not be repeated here.

[0085] In one exemplary embodiment, such as Figure 4A As shown, a chip programming system 400 is provided, including: a programming device 402 and a chip 404 on each programming socket; wherein, the first programming interface of the first programming socket is connected to the programming device, and the first programming interface of each subsequent programming socket is connected to the second programming interface of the next higher programming socket, forming a cascaded programming link.

[0086] In some embodiments, such as Figure 4B As shown, the system also includes a host computer 406; wherein, the first communication interface of the first-level programming socket is connected to the host computer 406, and the first communication interface of each subsequent programming socket is connected to the second communication interface of the next higher-level programming socket, forming a cascaded communication link.

[0087] In some embodiments, the programming device 402 is used to send programming data to the chip on the primary programming socket.

[0088] In some embodiments, the chip 404 on each programming socket is used to receive programming data through the first programming interface of the programming socket; write the programming data into the local storage space; load the cascade programming program from the programming data in the local storage space; execute the cascade programming program; and send programming data through the second programming interface of the programming socket, so that the programming data is sent down step by step along the cascade programming link, thereby realizing the programming of the chips on each programming socket in the cascade programming link.

[0089] In some embodiments, the chip 404 on each programming socket is used to receive downstream chip data through the second communication interface of the programming socket; the downstream chip data comes from the chips on each programming socket downstream of the current programming socket in the cascaded communication link; the downstream chip data is reported through the first communication interface of the current programming socket so that the downstream chip data is reported to the host computer level by level along the cascaded communication link; the host computer 406 is used to receive the downstream chip data through the cascaded communication link.

[0090] In some embodiments, downstream chip data includes downstream chip data used to characterize the programming status of chips on downstream programming sockets; each chip 404 on each programming socket is used to send a read command for this level through the second communication interface of the programming socket; and to receive downstream chip data reported by chips on downstream programming sockets in response to the read command for this level through the second communication interface of the programming socket.

[0091] In some embodiments, each programming socket has at least two sets of interfaces, each set of interfaces including a second programming interface and a second communication interface; the same lower-level programming socket is connected to the same set of interfaces of each programming socket; the chip 404 on each programming socket is used to send programming data through the second programming interface in the set of interfaces for each set of interfaces; send a read command for the current level through the second communication interface in the set of interfaces; and receive lower-level chip data reported by the chip on the lower-level programming socket in response to the read command for the current level through the second communication interface in the set of interfaces.

[0092] In some embodiments, the programming data includes the number of programming permissions; the cascaded programming program includes a programming subroutine; the chip 404 on each programming socket is used to, if the number of programming permissions is greater than zero, use the programming subroutine to traverse each group of interfaces of the current programming socket and send programming data through the second programming interface in the traversed group of interfaces; if the data of the lower-level chip indicates successful programming, decrement the number of programming permissions by 1 and report the data of the lower-level chip through the first communication interface of the current programming socket; after reporting the data of the lower-level chip, if the traversal is not finished, return to the step of traversing each group of interfaces of the current programming socket using the programming subroutine if the number of programming permissions is greater than zero.

[0093] In some embodiments, the chip 404 on each programming socket is used to report insufficient permission information through the first communication interface of the programming socket if the number of programming permission attempts is not greater than zero, so that the insufficient permission information is reported to the host computer level by level along the cascading communication link; the host computer 406 is used to issue new programming permission attempts through the cascading communication link; the chip 404 on each programming socket is used to receive new programming permission attempts issued by the host computer along the cascading communication link through the first communication interface of the programming socket.

[0094] In some embodiments, the chip 404 on each programming socket is used to send an initialization command through the second programming interface in the traversed group of interfaces to instruct the chip on the next programming socket connected to the second programming interface to enter the programming mode and return response data; if response data is received through the second programming interface in the group of interfaces, programming data is sent through the second programming interface in the group of interfaces; if no response data is received and the traversal is not finished, the step of traversing each group of interfaces of the current programming socket using the programming subroutine if the number of programming permission counts is greater than zero is returned.

[0095] In some embodiments, the chip 404 on each programming socket is used to report the end of programming for that level through the first communication interface of the programming socket after traversal, so that the end of programming for that level is reported to the host computer level by level along the cascading communication link; the host computer 406 is used to issue a programming stop command for that level through the cascading communication link; the chip 404 on each programming socket is used to receive the programming stop command for that level issued by the host computer along the cascading communication link through the first communication interface of the programming socket; and in response to the programming stop command for that level, set the programming subroutine to an unexecutable state.

[0096] In some embodiments, the chip 404 on each programming socket is used to return to the step of sending programming data through the second programming interface of the current programming socket when the programming of the lower-level chip data characterization fails, until the repeated programming stop condition is met, and then report the lower-level chip data through the first communication interface of the current programming socket.

[0097] Each component in the aforementioned chip programming system can be implemented entirely or partially through software, hardware, or a combination thereof. These components can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the corresponding operations of each component.

[0098] In one exemplary embodiment, a programming device is provided, the internal structure of which can be shown in the following diagram. Figure 5 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it sends the programmed data to the chip on the primary programming socket.

[0099] In one exemplary embodiment, a host computer is provided, which may be a terminal, and its internal structure diagram may be as follows. Figure 6As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it responds to various information reported by the cascaded communication link. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0100] Those skilled in the art will understand that Figure 5 or Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0101] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0102] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0103] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0104] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0105] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A chip programming method, characterized in that, A chip applied to each programming socket; the first programming interface of each programming socket is connected to the second programming interface of the upper-level programming socket or a programming device to form a cascaded programming link; the method includes: Receive programming data through the first programming interface of this programming socket; Write the programmed data into the local storage space; Load the cascaded burning program from the burning data in the storage space of the local terminal; The cascaded programming program is executed, and the programming data is sent down through the second programming interface of the current programming socket, so that the programming data is sent down step by step along the cascaded programming link, thereby realizing the programming of the chips on each programming socket in the cascaded programming link.

2. The method according to claim 1, characterized in that, The first communication interface of each programming socket is connected to the second communication interface of the upper-level programming socket or a host computer, forming a cascaded communication link; after the programming data is sent through the second programming interface of the current programming socket, the process further includes: The downstream chip data is received through the second communication interface of the programming socket at this level; the downstream chip data comes from the chips on each programming socket downstream of the programming socket at each level in the cascaded communication link. The downstream chip data is reported through the first communication interface of the local programming socket, so that the downstream chip data is reported to the host computer level by level along the cascaded communication link.

3. The method according to claim 2, characterized in that, The downstream chip data includes downstream chip data used to characterize the programming status of chips on the next-level programming socket; receiving downstream chip data through the second communication interface of the current programming socket includes: Send the read command for this level through the second communication interface of the local programming socket; The lower-level chip data reported by the chip on the lower-level programming socket in response to the read command of the current level is received through the second communication interface of the current level programming socket.

4. The method according to claim 3, characterized in that, Each programming socket has at least two sets of interfaces, each set of interfaces including a second programming interface and a second communication interface; the same lower-level programming socket is connected to the same set of interfaces of each programming socket; the sending of programming data through the second programming interface of the programming socket includes: For each group of interfaces, the burning data is sent through the second programming interface in this group of interfaces; Sending the local read command through the second communication interface of the local programming socket includes: Send the current level read command through the second communication interface in this group of interfaces; The step of receiving data from the lower-level chip reported by the chip on the lower-level programming socket in response to the read command of the current programming socket through the second communication interface of the current programming socket includes: The second communication interface in this group receives the data from the lower-level chip reported by the chip on the lower-level programming socket in response to the read command of this level.

5. The method according to claim 4, characterized in that, The programming data includes the number of programming permissions; the cascaded programming program includes programming subroutines; for each group of interfaces, the programming data is sent through the second programming interface in this group of interfaces, including: If the number of burning permissions is greater than zero, the burning subroutine will traverse each group of interfaces of the current burning socket and send the burning data through the second programming interface in the traversed group of interfaces. The reporting of downstream chip data through the first communication interface of the local programming socket includes: If the lower-level chip data representation is successfully programmed, the programming permission count is decremented by 1, and the lower-level chip data is reported through the first communication interface of the programming socket. After reporting the data of the lower-level chip, if the traversal is not finished, return to the step of traversing each group of interfaces of the current programming socket using the programming subroutine if the number of programming permission counts is greater than zero.

6. The method according to claim 5, characterized in that, The method further includes: If the number of programming permission attempts is not greater than zero, then the permission insufficiency information is reported through the first communication interface of the programming socket at this level, so that the permission insufficiency information is reported to the host computer level by level along the cascaded communication link; The first communication interface of the local programming socket receives new programming permission counts from the host computer and sent along the cascaded communication link.

7. The method according to claim 5, characterized in that, The step of sending the programming data through the second programming interface in this group of interfaces includes: An initialization command is sent through the second programming interface in this group of interfaces to instruct the chip on the lower-level programming socket connected to the second programming interface to enter the programming mode and return response data. If the response data is received through the second programming interface in this group of interfaces, the burning data is sent out through the second programming interface in this group of interfaces. If the response data is not received and the traversal is not finished, then return to the step of traversing each group of interfaces of the current programming socket using the programming subroutine if the number of programming permission attempts is greater than zero.

8. The method according to claim 5, characterized in that, The method further includes: After the traversal is completed, the programming completion information of this level is reported through the first communication interface of the programming socket, so that the programming completion information of this level is reported to the host computer level by level along the cascaded communication link; The local programming socket receives a local programming stop command from the host computer and sent along the cascaded communication link through its first communication interface. In response to the current level's programming stop command, the programming subroutine is set to an unexecutable state.

9. The method according to any one of claims 3 to 8, characterized in that, The reporting of downstream chip data through the first communication interface of the local programming socket includes: If the lower-level chip data characterization fails to be programmed, the process returns to the step of sending the programming data through the second programming interface of the current programming socket until the repeated programming stop condition is met, at which point the lower-level chip data is reported through the first communication interface of the current programming socket.

10. A chip programming system, characterized in that, The system includes a programming device and chips on each programming socket; wherein, the first programming interface of the first programming socket is connected to the programming device, and the first programming interface of each subsequent programming socket is connected to the second programming interface of the next higher programming socket, forming a cascaded programming link; the system is used to implement the steps of the method according to any one of claims 1 to 9.

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