TFT-LCD (Thin Film Transistor Liquid Crystal Display) array substrate structure capable of reducing metal short circuit risk

Abstract

The utility model provides a TFT-LCD (Thin Film Transistor Liquid Crystal Display) array substrate structure capable of reducing metal short circuit risk, which comprises a substrate, a gate metal layer, a gate insulating layer and a semiconductor layer are sequentially prepared on the substrate in a patterning manner, an isolating layer is prepared on the semiconductor layer and is SiOx, two ILD (Inter-Line Distortion) via holes are formed in the isolating layer through a yellow light process, and the two ILD via holes are communicated with the gate metal layer. An ILD via hole is formed in the semiconductor layer and exposes the semiconductor layer, a pixel electrode layer and a source and drain electrode layer are prepared on the isolation layer in sequence, the pixel electrode layer and the source and drain electrode layer are designed on the same layer, a source electrode and a drain electrode of the source and drain electrode layer are in lap joint with the semiconductor layer through the ILD via hole, the source electrode is further in lap joint with the pixel electrode layer, and the isolation layer is arranged on the isolation layer. A flat layer is further prepared above the source and drain electrode layer, the flat layer covers the source and drain electrode layer and the pixel electrode layer, and a common electrode layer is prepared on the flat layer. According to the utility model, the risk of metal short circuit between the gate metal layer and the source-drain electrode layer can be effectively reduced.

Description

Technical Field

[0001] The utility model relates to the field of a TFT-LCD array substrate structure, in particular to a TFT-LCD array substrate structure capable of reducing the risk of metal short circuit. Background Art

[0002] TFT-LCD (Thin Film Transistor Liquid Crystal Display) is still the mainstream technology in the display industry due to its low production cost, high yield rate, mature process technology, etc. Metal oxide TFT (IGZO-TFT) technology has gradually developed, and its field effect mobility is 20 to 30 times that of a-Si TFT, which can achieve ultra-high resolution. At the same time, it has the advantages of small leakage current and low temperature process, and is widely favored in industrial production.

[0003] like Figure 1 The structure of the TFT array substrate 100' in the prior art is shown. The display area (AA area) of the array substrate 100' generally adopts a 7MaskMid-Com architecture. The structure of the display area of ​​the array substrate 100' includes, from bottom to top, a substrate 1', a gate metal layer 2', a gate insulating layer 3', a semiconductor layer 4', a source-drain electrode layer 5', a passivation layer 6', a common electrode layer 7', a planar layer 8' and a pixel electrode layer 9'. The gate metal layer 2' usually uses a three-layer metal structure of Mo / Al / Mo, in which the metal Al will expand due to high temperature in the subsequent process, thereby forming a bulge. In severe cases, the top Mo of the gate metal layer 2' and the gate insulation layer 3' will be broken, resulting in a short circuit between the gate metal layer 2' and the source and drain electrode layer 5'. In addition, in the structure of the existing array substrate 100', there is a flat layer 8' between the pixel electrode layer 9' and the common electrode layer 7'. In actual production, such as Figure 2 As shown, the metal Taper angle α of the gate metal layer 2' is generally difficult to control below 60°. When α of the gate metal layer 2' is greater than 90° to form an obtuse angle, the metal coverage of the gate insulating layer 3' on the gate metal layer 2' becomes poor, and cracks are easily formed in the gate insulating layer 3' at the Taper angle. When the source 51' metal (source) (data line) in the source-drain electrode layer 5' climbs the gate metal layer 2' Taper, it is easy to cause a short circuit between the gate metal layer 2' and the source-drain electrode layer 5' due to poor film morphology at the climbing location and cracks in the gate insulating layer 3', and the source routing is very likely to be broken due to abnormal climbing, which will cause defects such as bright spots and reduce the production yield. Summary of the invention

[0004] The technical problem to be solved by the utility model is to provide a TFT-LCD array substrate structure, which can effectively reduce the risk of metal short circuit between a gate metal layer and a source-drain electrode layer.

[0005] The utility model is implemented as follows: a TFT-LCD array substrate structure for reducing the risk of metal short circuit, which is divided into a display area and a non-display area, the display area structure includes a substrate, a gate metal layer, a gate insulating layer and a semiconductor layer are sequentially patterned on the substrate, an isolation layer is prepared on the semiconductor layer, the isolation layer is SiOx, two ILD vias are opened on the isolation layer by yellow light process, the ILD vias are located on the semiconductor layer and expose the semiconductor layer, a pixel electrode layer and a source-drain electrode layer are sequentially prepared on the isolation layer, the pixel electrode layer and the source-drain electrode layer are designed in the same layer, the source and drain of the source-drain electrode layer are overlapped with the semiconductor layer through the ILD vias respectively, and the source is also overlapped with the pixel electrode layer, a flat layer is also prepared above the source-drain electrode layer, the flat layer covers the source-drain electrode layer and the pixel electrode layer, and a common electrode layer is prepared on the flat layer.

[0006] Furthermore, the gate insulating layer is SiOx.

[0007] Furthermore, the isolation layer and the planarization layer are both made of insulating materials.

[0008] Furthermore, the semiconductor layer is IGZO.

[0009] Furthermore, the source-drain electrode layer is Mo, Mo / Al / Mo or Ti / Al / Ti.

[0010] The advantages of the utility model are as follows: the utility model increases the distance between the two metal layers by preparing two insulating layers, namely a gate insulating layer and an isolation layer, between the gate metal layer and the source-drain electrode layer, which can effectively reduce the risk of short circuit between the gate metal layer and the source-drain electrode layer caused by the thermal expansion of the metal Al in the gate metal layer and the lifting of the insulating layer due to the thermal effect in the subsequent process. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0012] Figure 1 The figure is a schematic diagram of the display area structure of a TFT-LCD array substrate in the prior art.

[0013] Figure 2 The present invention is a schematic diagram of the Taper angle structure of the gate metal layer in the display area of ​​the TFT-LCD array substrate in the prior art.

[0014] Figure 3 The utility model is a schematic diagram of the opening structure of the isolation layer in the display area of ​​a TFT-LCD array substrate for reducing the risk of metal short circuit.

[0015] Figure 4The utility model is a schematic diagram of the structure of preparing source-drain electrode layer in the display area of ​​a TFT-LCD array substrate for reducing the risk of metal short circuit.

[0016] Figure 5 The utility model is a schematic diagram of the display area structure of a TFT-LCD array substrate for reducing the risk of metal short circuit.

[0017] Explanation of the accompanying drawings: array substrate 100', substrate 1', gate metal layer 2', gate insulating layer 3', semiconductor layer 4', source-drain electrode layer 5', source 51', passivation layer 6', common electrode layer 7', planarization layer 8', pixel electrode layer 9', Taper angle α, array substrate 100, substrate 1, gate metal layer 2, gate insulating layer 3, semiconductor layer 4, isolation layer 5, ILD via 51, pixel electrode layer 6, source-drain electrode layer 7, source 71, drain 72, planarization layer 8, common electrode layer 9. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0019] like Figures 3 to 5 As shown, a TFT-LCD array substrate 100 structure for reducing the risk of metal short circuit is divided into a display area and a non-display area. The display area structure includes a substrate 1, on which a gate metal layer 2, a gate insulating layer 3 and a semiconductor layer 4 are patterned in sequence, wherein the gate metal layer 2 is Mo / Al / Mo, the gate insulating layer 3 is made of SiOx material, and the semiconductor layer 4 is IGZO; an isolation layer 5 is prepared on the semiconductor layer 4 by a PECVD process, and the isolation layer 5 is SiOx. Two ILD vias 51 are opened on the isolation layer 5 by a yellow light process, and the ILD vias 51 are located on the semiconductor layer 4 , and the semiconductor layer 4 is exposed, and a pixel electrode layer 6 and a source-drain electrode layer 7 are sequentially prepared on the isolation layer 4, the source-drain electrode layer 7 is Mo, Mo / Al / Mo or Ti / Al / Ti, the pixel electrode layer 6 and the source-drain electrode layer 7 are designed in the same layer, the source 71 and the drain 72 of the source-drain electrode layer 7 are overlapped with the semiconductor layer 4 through the ILD via 51 respectively, and the source 71 is also overlapped with the pixel electrode layer 6, and a flat layer 8 is also prepared above the source-drain electrode layer 7, the flat layer 8 covers the source-drain electrode layer 7 and the pixel electrode layer 6, a common electrode layer 9 is prepared on the flat layer 8, and the isolation layer 5 and the flat layer 8 are both insulating materials.

[0020] An isolation layer 5 is plated on the semiconductor layer 4, and a hole is opened in it through a yellow light process to define the metal area of ​​the source-drain electrode layer 7. The source-drain electrode layer 7 is connected to the semiconductor layer 4 through an ILD via 51. The isolation layer 5 can play a certain flattening role, and by preparing two insulating layers, the gate insulating layer 3 and the isolation layer 5, between the gate metal layer 2 and the source-drain electrode layer 7, the distance between the two metal layers is increased, which can effectively reduce the risk of short circuit between the gate metal layer 2 and the source-drain electrode layer 7 caused by the gate metal layer 2Al being heated and expanded due to subsequent thermal effects, which lifts up the gate insulating layer 3. And because the metal distance between the gate metal layer 2 and the source-drain electrode layer 7 is large, the risk of short circuit at the taper angle of the gate metal layer 2 will also be reduced, and the parasitic capacitance between the gate metal layer and the source-drain electrode layer can be reduced at the same time.

[0021] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A TFT-LCD array substrate structure for reducing the risk of metal short circuit, which is divided into a display area and a non-display area, wherein the display area structure comprises a substrate, on which a gate metal layer, a gate insulating layer and a semiconductor layer are sequentially patterned, Features: An isolation layer is prepared on the semiconductor layer, and the isolation layer is SiOx. Two ILD vias are opened on the isolation layer through a yellow light process. The ILD vias are located on the semiconductor layer and expose the semiconductor layer. A pixel electrode layer and a source-drain electrode layer are sequentially prepared on the isolation layer. The pixel electrode layer and the source-drain electrode layer are designed on the same layer. The source and drain of the source-drain electrode layer are overlapped with the semiconductor layer through the ILD vias respectively, and the source is also overlapped with the pixel electrode layer. A flat layer is also prepared above the source-drain electrode layer, and the flat layer covers the source-drain electrode layer and the pixel electrode layer. A common electrode layer is prepared on the flat layer.

2. A TFT-LCD array substrate structure for reducing metal short circuit risk according to claim 1, Features: The gate insulating layer is SiOx.

3. A TFT-LCD array substrate structure for reducing metal short circuit risk according to claim 1, Features: The isolation layer and the planarization layer are both made of insulating materials.

4. A TFT-LCD array substrate structure for reducing metal short circuit risk according to claim 1, Features: The semiconductor layer is IGZO.

5. The TFT-LCD array substrate structure for reducing metal short circuit risk according to claim 1, Features: The source-drain electrode layer is Mo, Mo / Al / Mo or Ti / Al / Ti.

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