Computer system, system on chip and electronic equipment

Abstract

The embodiment of the utility model provides a computer system, which is characterized by comprising a processor and a plurality of types of peripheral equipment connected with the processor, the processor comprises multiple types of peripheral ports, and one type of peripheral port is connected with one type of peripheral equipment; the multiple types of peripheral ports comprise a first part of peripheral ports and a second part of peripheral ports, the first part of peripheral ports are at least one type of peripheral ports in the multiple types of peripheral ports, and the second part of peripheral ports are other types of peripheral ports except the first part of peripheral ports in the multiple types of peripheral ports; the first part peripheral port is directly connected with a connected peripheral device through a bus; and the second part peripheral port is connected with the connected peripheral equipment through the intermediate connection equipment. According to the computer system provided by the embodiment of the invention, the processor supports connection with different types of peripheral equipment, so that the normal work of the processor is ensured.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a computer system, a system-on-a-chip, and an electronic device. Background Technology

[0002] A computer system can consist of a processor and peripheral devices connected to the processor. These peripheral devices interact with the processor to assist it in performing various tasks and functions. There can be various types of peripheral devices connected to the processor, and how to enable the processor to support connections to different types of peripheral devices to ensure its normal operation has become a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0003] In view of this, embodiments of this application provide a computer system, a system-on-a-chip, and an electronic device that enable the processor to support the connection of different types of peripheral devices to ensure the normal operation of the processor.

[0004] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0005] In a first aspect, embodiments of this application provide a computer system, including: a processor and various peripheral devices connected to the processor;

[0006] The processor includes multiple types of peripheral ports, each type of peripheral port connecting to a type of peripheral device; the multiple types of peripheral ports include a first part of peripheral ports and a second part of peripheral ports, wherein the first part of peripheral ports is at least one type of peripheral port among the multiple types of peripheral ports, and the second part of peripheral ports is other types of peripheral ports among the multiple types of peripheral ports excluding the first part of peripheral ports;

[0007] The first part of the peripheral ports is directly connected to the connected peripheral devices via a bus; the second part of the peripheral ports is connected to the connected peripheral devices via an intermediate connection device.

[0008] Optionally, the intermediate connection device includes: a connector;

[0009] The peripheral devices connected to the second part of the peripheral port are located on the connector.

[0010] Optionally, the intermediate connection device includes: a bus switching chip for allocating the bus, and a remote management control chip connected to the bus switching chip;

[0011] The remote management and control chip is connected between the second part of the peripheral port and the peripheral device; the bus switching chip is connected between the second part of the peripheral port and the remote management and control chip, as well as between the remote management and control chip and the peripheral device.

[0012] Optionally, the intermediate connection device further includes: a level conversion chip;

[0013] The level conversion chip is connected between the remote management control chip and the bus switching chip.

[0014] Optionally, the remote management control chip includes: an adapter interface, a management module, and a bus interface; wherein, the adapter interface is adapted to at least some interfaces in the second part of the peripheral ports, the management module is adapted to at least some peripheral devices connected to the second part of the peripheral ports, and the bus interface is adapted to the bus switching chip.

[0015] Optionally, the second peripheral port is a management port, and the interfaces in the management port include: a first UART interface, a first PCIe interface, a first eSPI interface, a first USB interface, and a first SPI interface; the bus switching chip includes a first bus switching chip and a second bus switching chip;

[0016] The management module of the remote management and control chip includes: a VGA display module connected to the display device, and a network module connected to a remote host computer;

[0017] The adapter interfaces of the remote management and control chip include: a second PCIe interface connected to the first PCIe interface via a PCIe bus, a second eSPI interface connected to the first eSPI interface via an eSPI bus, and a second USB interface connected to the first USB interface via a USB bus.

[0018] The bus interface of the remote management control chip includes a second UART interface and a second SPI interface; wherein the first UART interface and the second UART interface are connected to the first bus switching chip, and the first bus switching chip is also connected to a UART device; the first SPI interface and the second SPI interface are connected to the second bus switching chip, and the second bus switching chip is also connected to a BIOS Flash chip.

[0019] Optionally, the first peripheral port includes a power port; the power port includes an SVI interface and a core power supply; the peripheral device includes a VR chip;

[0020] The SVI interface is directly connected to the VR chip via the SVI bus.

[0021] Optionally, the first peripheral port includes a memory port; the memory port includes a memory channel; the peripheral device includes memory chips;

[0022] The memory channel is directly connected to the memory chip via a memory bus.

[0023] Optionally, the second peripheral port includes a memory port; the memory port includes a memory channel; the peripheral device includes a memory module;

[0024] The memory channel is connected to the memory module via the connector.

[0025] Optionally, the first peripheral port includes a first I / O port; the first I / O port includes a first I / O interface; the peripheral device includes a first I / O device;

[0026] The first IO interface is directly connected to the first IO device via an IO bus.

[0027] Optionally, the second peripheral port includes a first I / O port; the first I / O port includes a first I / O interface; the peripheral device includes a first I / O device;

[0028] The remote management and control chip is connected between the first IO interface and the first IO device; the bus switching chip is connected between the first IO interface and the remote management and control chip, and between the remote management and control chip and the first IO device.

[0029] Optionally, the second peripheral port includes a USB port; the USB port includes a USB interface; the peripheral device is a USB device adapted to the USB interface;

[0030] The USB interface is connected to the USB device via the connector.

[0031] Optionally, the second part of the peripheral ports includes a storage port; the peripheral device includes a storage device;

[0032] The storage port is connected to the storage device through a second I / O port; the second I / O port is directly connected to the storage device via a bus, or connected to the storage device via a connector.

[0033] Optionally, the second peripheral port includes a network port; the network port is connected to a peripheral device via a second I / O port.

[0034] The peripheral devices include network devices and Ethernet ports; the second I / O port is directly connected to the network device via a bus, and the second I / O port is connected to the Ethernet port via a physical layer interface chip.

[0035] Secondly, embodiments of this application provide a system-on-a-chip, which includes the computer system described above.

[0036] Thirdly, embodiments of this application provide an electronic device, which includes the system-on-a-chip described above.

[0037] The computer system provided in this application includes: a processor and multiple types of peripheral devices connected to the processor; the processor includes multiple types of peripheral ports, with each type of peripheral port connecting to a type of peripheral device; the multiple types of peripheral ports include a first part of peripheral ports and a second part of peripheral ports, wherein the first part of peripheral ports is at least one type of peripheral port among the multiple types of peripheral ports, and the second part of peripheral ports is other types of peripheral ports among the multiple types of peripheral ports besides the first part of peripheral ports; the first part of peripheral ports is directly connected to the connected peripheral devices via a bus; the second part of peripheral ports is connected to the connected peripheral devices via an intermediate connection device.

[0038] As can be seen, the computer system provided in this application embodiment has multiple peripheral ports in the processor adapted to various types of peripheral devices, and provides two ways for the processor to connect to the peripheral devices. Specifically, the first part of the processor's peripheral ports is directly connected to the peripheral devices via a bus, while the second part of the processor's peripheral ports (excluding the first part) can be connected to the peripheral devices via an intermediate connection device. Therefore, by providing multiple peripheral ports adapted to various types of peripheral devices in the processor, and with the aforementioned two connection methods, the processor can support the connection of different types of peripheral devices, ensuring the normal operation of the processor. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0040] Figure 1 This is a structural example diagram of the computer system provided in the embodiments of this application;

[0041] Figure 2 This is another structural example diagram of the computer system provided in the embodiments of this application;

[0042] Figure 3 This is an example diagram of the connection structure between the power port and the power supply device provided in the embodiments of this application;

[0043] Figure 4 This is an example diagram of the connection structure between the memory port and the memory device provided in the embodiments of this application;

[0044] Figure 5 This is an example diagram of the connection structure between the first IO port and the first IO device provided in the embodiments of this application;

[0045] Figure 6 This is an example diagram of another connection structure between the first IO port and the first IO device provided in the embodiments of this application;

[0046] Figure 7 This is an example diagram of the connection structure between the USB port and the USB device provided in the embodiments of this application;

[0047] Figure 8 This is an example diagram of the connection structure between the storage port and the storage device provided in the embodiments of this application;

[0048] Figure 9 This is an example diagram of the connection structure between the network port and the network device provided in the embodiments of this application;

[0049] Figure 10 This is an example diagram of the connection structure between the management port and the management device provided in the embodiments of this application. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0051] The processor is one of the most important components of a computer system and the core of the computer's various data processing and computational tasks. The processor is responsible for receiving and executing instructions from computer programs and controlling various operations of the computer system, ensuring that all tasks are performed in an orderly manner and providing better support for various computing applications.

[0052] In a computer system, the processor needs to connect and exchange data with peripheral devices so that these devices can assist the processor in completing various tasks and functions, meeting the processor's operational needs. As an optional implementation, Figure 1 An exemplary structural diagram of the computer system provided in the embodiments of this application is shown, with reference to... Figure 1A computer system can consist of a processor 1 and peripheral devices connected to the processor. The processor 1 has a port 2, and peripheral devices 3 can be located outside the processor 1. Port 2 can connect to the peripheral devices 3 outside the processor via a bus, allowing the processor 1 to interact and communicate with the peripheral devices 3. The bus is a physical or logical structure in a computer system used for data transmission, and it can be used to connect various devices within the computer, including the processor and peripheral devices.

[0053] However, the peripheral devices that the processor can connect to may be of various types (for example, the processor needs power supplies, storage devices, USB devices, etc.). Therefore, it is necessary to design a computer system that allows the processor in the computer system to support the connection of different types of peripheral devices in order to ensure the normal operation of the processor.

[0054] In the optional implementation, Figure 2 Another structural example diagram of the computer system provided in an embodiment of this application is illustrated. (Refer to...) Figure 2 The processor 1 is equipped with multiple types of peripheral ports, each with unique functions and protocols. These peripheral ports may include: a power port 210, a memory port 220, a first I / O port 230, a USB (Universal Serial Bus) port 240, a storage port 250, a network port 260, and a management port 270. Therefore, the processor 1 can communicate with peripheral devices and coordinate various operations and tasks through these peripheral ports. Each type of peripheral port connects to a specific type of peripheral device. Based on these peripheral ports, the corresponding peripheral devices 3 outside the processor may include: a power supply device 310 connected to the power port 210, a memory device 320 connected to the memory port 220, a first I / O device 330 connected to the first I / O port 230, a USB device 340 connected to the USB port 240, a storage device 350 connected to the storage port 250, a network device 360 ​​connected to the network port 260, and a management device 370 connected to the management port 270. The aforementioned peripheral devices interact with the processor through various peripheral ports of processor 1, supporting the processor's functions and performance.

[0055] In an optional implementation, the peripheral ports can be divided into a first part of peripheral ports and a second part of peripheral ports. The first part of peripheral ports consists of at least one type of peripheral port from a variety of peripheral port types, while the second part of peripheral ports consists of other types of peripheral ports besides the first part. The first part of peripheral ports can be directly connected to the connected peripheral device via a bus; the second part of peripheral ports can be connected to the connected peripheral device via an intermediate connection device.

[0056] Direct connection between the processor and peripheral devices via a bus reduces data transmission latency, simplifies system architecture, and improves the reliability and stability of the computer system. Connecting the processor to peripheral devices through intermediate connection devices enables compatibility between different devices, meeting the needs of various peripheral ports to connect to other peripheral devices to achieve their functions. Therefore, the computer system provided in this application provides different connection schemes for various types of peripheral ports and peripheral devices, satisfying the connection requirements of various peripheral ports and peripheral devices, enabling the processor to support the connection of different types of peripheral devices, and ensuring the normal operation of the processor.

[0057] Optionally, the intermediate connection device may include a connector, and the second peripheral port may be located on the connector. The connector provides a physical interface, enabling the processor and peripheral devices to connect, communicate, and interact. In specific implementations, a suitable connector can be selected based on the requirements of the peripheral devices and the protocols and standards of the peripheral ports to ensure that the processor and peripheral devices can operate and collaborate normally.

[0058] Optionally, when a connector is used in the intermediate connection device, or when a connector is not used, the intermediate connection device may include: a bus switching chip for distributing the bus, and a remote management control chip connected to the bus switching chip.

[0059] Among them, the Baseboard Management Controller (BMC) is a chip or circuit board used to manage and monitor remote computer systems. Bus switching chips can be used to connect multiple devices (such as processors, peripherals, and the Baseboard Management Controller) in a computer system. When different devices need to be switched, the bus switching chip can achieve this by switching paths and allocating buses.

[0060] In an optional implementation, the remote management control chip can be connected between the second part of the peripheral port and the peripheral device to realize the management operation of the peripheral device; the bus switching chip is connected between the second part of the peripheral port and the remote management control chip, as well as between the remote management control chip and the peripheral device. Thus, when the processor needs to use the remote management control chip, the bus switching chip can be used to allocate the bus between the processor's peripheral port and the remote management control chip.

[0061] Optionally, the intermediate connection device may also include a level conversion chip. A level conversion chip is an electronic device used to convert one level or signal to another level or signal, enabling interconnection and compatibility between different levels.

[0062] In an optional implementation, the level conversion chip can be connected between the remote management control chip and the bus switching chip to realize level conversion between the bus connected to the processor peripheral port and the bus connected to the remote management control chip, ensuring level consistency and connection interaction between different devices.

[0063] As an optional implementation, the various peripheral ports may include at least two of the following: a power port, a memory port, a first I / O port, a USB port, a storage port, a network port, and a management port. Wherein, the peripheral device connected to the power port is a power device, the peripheral device connected to the memory port is a memory device, the peripheral device connected to the first I / O port is a first I / O device, the peripheral device connected to the USB port is a USB device, the peripheral device connected to the storage port is a storage device, the peripheral device connected to the network port is a network device, and the peripheral device connected to the management port is a management device. The following examples illustrate each type of peripheral port connected to its corresponding peripheral device.

[0064] In one optional embodiment, taking the connection of a power supply device to a power port as an example, Figure 3 An exemplary diagram illustrating the connection structure between the power port and the power supply device provided in an embodiment of this application is shown. (Refer to...) Figure 3 The connection structure includes a peripheral port and peripheral devices connected to the peripheral port. The peripheral port includes a power port 210, and the peripheral device connected to the power port 210 can be a VR (Virtual Reality) chip 211.

[0065] VR chips are chips specifically designed for virtual reality (VR) technology. Because VR applications place high demands on computer system performance and energy consumption, efficient power management is essential to provide a better user experience and extend lifespan. VR chips are characterized by tight integration and collaboration with the processor, for example, through a power supply plane (see...). Figure 3 The VR chip (212) connects to the processor's power port and works in conjunction with it. The VR chip can monitor and control the processor's power consumption and performance status, dynamically adjusting the power supply to meet actual needs. Thus, the VR chip can provide fine-grained power management for the processor. The power plane plays a crucial role in the processor. By providing a low-impedance power connection, the power plane ensures the processor receives a stable DC power supply while providing low noise and low interference to maintain the stability and reliability of the processor circuitry and reduce interference to the processor.

[0066] In an optional implementation, the power port is the first part of the peripheral port, and the power port and the VR chip can be directly connected via a bus.

[0067] Optionally, the power port may include multiple interfaces, and the VR chip can connect to the power port through the interfaces connected to the power port.

[0068] In an optional embodiment, refer to Figure 3 The power port 210 can be internally configured with an SVI (Serial Voltage Identification) interface. The VR chip can connect to the power port 210 by connecting to the SVI interface. The SVI interface is a bus interface used for power-related interactions, which can be used to manage and monitor the power supply and power consumption of a computer system.

[0069] In an optional implementation, the SVI interface may include a first SVI interface 213 and / or a second SVI interface 214; the power port 210 contains a core power supply, which may include a first core power supply 215, a second core power supply 216, and a third core power supply 217. (See reference...) Figure 3 The VR chip can be connected to the first SVI interface 213 in the power port 210 via the SVI bus 218 to achieve connection to the power port 210. The SVI bus refers to a bus that supports the SVI protocol and is used to connect the SVI interface to the VR chip to transmit data or signals.

[0070] Optionally, depending on the protocols supported by the SVI interface, the SVI interface is divided into a first SVI interface and a second SVI interface. The first SVI interface supports both SVI2 (second generation serial voltage identification bus) and SVI3 (third generation serial voltage identification bus) protocols, while the second SVI interface only supports the SVI2 protocol. The specific protocol that the first SVI interface runs can be set through an external setting pin on the processor.

[0071] Optionally, an SVI interface supporting the SVI2 protocol can manage one VR chip; an SVI interface supporting the SVI3 protocol can manage multiple VR chips.

[0072] Furthermore, depending on the protocol of the SVI interface connected to the SVI bus, the SVI bus can be an SVI2 bus and / or an SVI3 bus, and thus the SVI interface in the power port can be connected to the VR chip through an SVI bus that supports the same protocol.

[0073] In an optional implementation, the peripheral device includes an adapter interface that is compatible with the interface of the connected peripheral port.

[0074] Optionally, the VR chip has an SVI interface, which can be used to connect the SVI bus to the SVI interface in the power port. The SVI interface in the VR chip can support the SVI2 or SVI3 protocol. In specific implementations, the SVI interface in the power port connects to and manages VR chips that support the same protocol through an SVI bus that supports the same protocol.

[0075] In a further alternative implementation, the VR chip can be powered by connecting to a power port via a power rail on the power plane. A power rail is a wire or circuit path on the power plane used to connect power to a specific electronic device or component (such as the processor's power port).

[0076] Optionally, the VR chip can generate one or more power rails, which can then be connected to a power port.

[0077] In practice, depending on the protocols supported by the VR chip and the number of power rails generated by the VR chip, the SVI interface connects to an SVI bus that supports the same protocol, the SVI bus connects to a VR chip that supports the same protocol, and the VR chip provides power to the processor through a power supply plane.

[0078] In the optional implementation, there are multiple first SVI interfaces, multiple second SVI interfaces, and multiple core power supplies.

[0079] It should be noted that when numbering the core power supplies in this application embodiment (for example, numbering the three core power supplies as the first to the third core power supply), the core power supply with a certain number does not specifically refer to a fixed core power supply. The numbering of the core power supply is only for the convenience of explaining the configuration scheme of multiple core power supplies, and the number has no special meaning.

[0080] In an optional embodiment, refer to Figure 3 The system has two SVI interfaces, two SVI interfaces, and three core power supplies. Taking the VR chip 211, which supports the SVI3 protocol, as an example... Figure 3The VR chip 211 located on the side of the first core power supply 215 and the second core power supply 216 generates two power rails, while the VR chip 211 located on the side of the third core power supply 217 generates one power rail. Since the first SVI interface 213 supports both SVI2 and SVI3 protocols, the two first SVI interfaces 213 are connected to and manage the two VR chips 211 via two sets of SVI buses 218. The VR chip 211 can provide power to the processor through the power supply plane 212. If the VR chip 211 supports the SVI2 protocol, any two of the two first SVI interfaces and two second SVI interfaces in the processor can manage the VR chip through an SVI bus supporting the same protocol. The principle is described above and will not be elaborated further here.

[0081] In another alternative embodiment, taking the connection of a memory device via a memory port as an example, Figure 4 An exemplary diagram illustrating the connection structure between a memory port and a memory device provided in an embodiment of this application is shown. (Refer to...) Figure 4 The connection structure may include: a memory port 220, a memory connector 221, and peripheral devices connected to the memory port: a memory module 222 and memory chips 223. The memory port is used for data exchange and communication between the processor and the memory device. The memory connector is used to connect the memory module (e.g., a memory module) to the processor. Memory chips are the basic units for storing data, while a memory module is a memory module composed of multiple memory chips.

[0082] In an optional implementation, the memory port can be used as either a first-part peripheral port or a second-part peripheral port.

[0083] Optionally, if the memory port is used as a first-part peripheral port, and the memory device connected to the memory port is a memory chip, the memory port and the memory chip can be directly connected via a memory bus. The memory bus is the physical channel responsible for data transfer between the processor and the memory device.

[0084] Optionally, if the memory port is used as a second peripheral port, and the memory device connected to the memory port is a memory module, the memory port can be connected to the memory module via a connector. The memory module is mounted on the connector.

[0085] In an optional embodiment, refer to Figure 4If memory port 220 is used as the first part of the peripheral port, the memory device connected to memory port 220 is memory chip 223, and memory port 220 and memory chip 223 can be directly connected through memory bus 224. If memory port 220 is used as the second part of the peripheral port, the memory device connected to memory port 220 is memory module 222, and memory port 220 can be connected to memory module 222 through memory connector 221. The memory channel of the memory port and the memory connector can be connected through memory bus 224.

[0086] It should be noted that the memory connector 221 can exist in the form of a slot, and the memory module 222 can be inserted into the memory connector 221 to communicate with the processor.

[0087] Furthermore, a memory port may include a memory channel. The memory device connected to the memory port can be connected to the memory port by connecting to the memory channel within the memory port. A memory channel refers to the internal pathway of the memory port used to connect the memory port and the memory device, and can be used to transmit data, addresses, and signals between the processor and the memory device.

[0088] In the optional implementation, refer to Figure 4 The memory port 220 has a memory channel 225 inside. The memory chip 223 can be connected to the memory port 220 by connecting to the memory channel 225; the memory module 222, which is mounted on the memory connector 221, can be connected to the memory port 220 by connecting to the memory channel 225.

[0089] Optionally, there can be multiple memory channels within a memory port, and there can also be multiple memory buses, but the number of memory buses cannot exceed the number of memory channels. If the number of memory buses exceeds the number of memory channels, memory bus redundancy may occur, making efficient data transfer impossible.

[0090] In an optional implementation, the number of memory modules mounted on a memory connector does not exceed the number of memory connectors connected to a single memory bus.

[0091] Optional, refer to Figure 4 If the memory bus 224 is connected to one memory connector 221, a memory module 222 can be installed on the memory connector 221; if the memory bus 224 is connected to two memory connectors 221, one or two memory modules 222 can be installed on the memory connector 221.

[0092] In another optional embodiment, taking the connection of the first IO port to the first IO device as an example, Figure 5An exemplary diagram illustrating the connection structure between the first IO port and the first IO device provided in an embodiment of this application is shown. (Refer to...) Figure 5 The connection structure may include: a first I / O port 230, and a peripheral device connected to the first I / O port 230: a first I / O device 231. The first I / O port contains a first I / O interface 232, and the I / O port is a channel used by the processor to transmit data with the peripheral device.

[0093] In an optional implementation, the first I / O port can be used as either a first part of the peripheral port or a second part of the peripheral port.

[0094] Optionally, if the first I / O port is used as a first part of the peripheral port, the peripheral device connected to the first I / O port is the first I / O device, and the first I / O port and the first I / O device can be directly connected via the I / O bus. The I / O bus is the physical channel responsible for data transmission between the processor and the first I / O device. The first I / O device can connect to the first I / O port by connecting to the first I / O interface within the first I / O port.

[0095] In an optional embodiment, refer to Figure 5 If the first I / O port 230 is used as a first peripheral port, the first I / O port 230 and the first I / O device 231 are directly connected via the I / O bus 233. The first I / O device 231 connects to the first I / O port 230 by connecting to the first I / O interface 232 within the first I / O port 230.

[0096] Optionally, if the first IO port is used as a second peripheral port, the peripheral device connected to the first IO port is the first IO device, and the first IO port can be connected to the first IO through an intermediate connection device.

[0097] In an optional implementation, the intermediate connection device through which the first IO port connects to the first IO device may include a connector, a remote management control chip, or a bus switching chip.

[0098] Optionally, the remote management control chip can be connected between the first IO port and the first IO device; the bus switching chip can be connected between the first IO port and the remote management control chip, as well as between the remote management control chip and the first IO device.

[0099] In an optional embodiment, Figure 6 An exemplary diagram illustrating another connection structure between the first IO port and the first IO device provided in an embodiment of this application is shown. (Refer to...) Figure 6The remote management control chip 234 is connected between the first I / O port 230 and the first I / O device 231 to manage the first I / O device 231. The bus switching chip 235 is connected between the first I / O port 230 and the remote management control chip 234, and between the remote management control chip 234 and the first I / O device 231. The first I / O device 231 can be mounted on the connector 236.

[0100] It should be noted that intermediate connection devices (such as bus switching chips) that connect to the first IO port all achieve connection to the first IO port by connecting to the first IO interface within the first IO port.

[0101] In a further optional implementation, the intermediate connection device through which the first I / O port connects to the first I / O device may further include a level conversion chip. (See reference...) Figure 6 The level conversion chip 237 can be connected between the remote management control chip 234 and the bus switching chip 235.

[0102] It should be noted that if the first level of the IO bus connected to the first IO port is different from the second level of the IO bus connected to the remote management control chip, a level conversion chip is needed to make the first and second levels the same; if the first and second levels are the same, a level conversion chip is not needed.

[0103] Optionally, the first I / O interface configured within the first I / O port may include I / O interfaces supporting various protocols, such as SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver Transmitter), LPC (Low Pin Count), eSPI (Enhanced Serial Peripheral Interface), I2C (Inter-Integrated Circuit), SMBUS (System Management Bus), SGPIO (Serial General-Purpose Input / Output), and MDIO (Management Data Input / Output).

[0104] In an optional embodiment, the first I / O port can be a second peripheral port, the first I / O interface within the first I / O port can be an SPI interface, and the first I / O device connected to the first I / O port via the SPI interface can be a BIOS Flash (Basic Input / Output System Flash) chip.

[0105] The SPI interface is a communication protocol and interface standard for serial data transmission, used to connect the processor and peripheral devices. It can connect to devices that support the SPI protocol (such as BIOS Flash chips). A BIOS Flash chip is a flash memory chip used to store the computer's basic input / output system (BIOS). The BIOS program is the first program to run when the computer system starts, responsible for self-testing and initializing computer system resources. Flash chips are non-volatile storage devices characterized by high speed, reliability, and low power consumption. Therefore, the BIOS Flash chip is crucial for the normal startup and operation of the computer system. In a computer system, the BIOS Flash chip can connect to the first I / O port via the SPI interface to access the processor, facilitating the rapid loading of the BIOS program during system startup. Simultaneously, a remote management control chip can manage the BIOS Flash chip. Based on this, the processor's SPI interface, the remote management control chip, and the BIOS Flash chip are connected via a bus switching chip to achieve data transmission access and device management functions.

[0106] In another alternative embodiment, taking the connection of a USB device via a USB port as an example, Figure 7 An exemplary diagram illustrating the connection structure between a USB port and a USB device provided in an embodiment of this application is shown. (Refer to...) Figure 7 The connection structure may include: a USB port 240, and a peripheral device connected to the USB port 240: a USB device 241.

[0107] USB is a universal interface standard for connecting peripheral devices. A USB port is a physical interface that has the above universal interface standard. It can be used to connect USB devices and provide data transmission and power supply functions.

[0108] In an optional implementation, the USB port can be used as a second peripheral port, and the USB port and USB device can be connected via a connector.

[0109] In an optional embodiment, refer to Figure 7USB port 240 is connected to USB device 241 via connector 242, wherein USB device 241 is mounted on connector 242 and then connected to USB port 240 via USB bus 243.

[0110] Optionally, the USB port includes a built-in USB interface. USB devices mounted on the connector connect to the USB port via this interface. (See reference...) Figure 7 The USB port 240 has a USB interface 244 inside, and the USB device 241 is mounted on the connector 242. The USB port can be connected by connecting to the USB interface 244.

[0111] In an optional implementation, the USB interface may include a first USB interface and a second USB interface. The first USB interface supports the USB 3.1 protocol, and the second USB interface supports the USB 2.0 protocol. Therefore, the interface speed of the first USB interface can support USB 3.1 Gen1 (5Gbps) and USB 3.1 Gen2 (10Gbps); the interface speed of the second USB interface can support 1.5Mb / s (Low-speed), 12Mb / s (Full-speed), and 480Mb / s (High-speed).

[0112] Correspondingly, the USB bus may include a first USB bus and a second USB bus; the USB device may include a first USB device and a second USB device. Both the first USB bus and the first USB device support the USB 3.1 protocol, while both the second USB bus and the second USB device support the USB 2.0 protocol.

[0113] In an optional implementation, the first USB interface can be adapted to a first USB device that supports the same protocol via a connector; the second USB interface can be adapted to a second USB device that supports the same protocol via a connector.

[0114] It should be noted that there are multiple first USB ports and multiple second USB ports in the USB port, which can meet the connection needs of different devices and provide higher data transfer speeds and better compatibility.

[0115] In yet another optional embodiment, taking the connection of a storage port to a storage device as an example, Figure 8 An exemplary diagram illustrating the connection structure between the storage port and the storage device provided in an embodiment of this application is shown. (Refer to...) Figure 8 The connection structure may include: a storage port 250, and a peripheral device 252 connected to the storage port 250 via a second I / O port 251. The data transfer rate of the second I / O port is higher than that of the first I / O port described above.

[0116] In an optional implementation, the storage port can be used as a second peripheral port. The second I / O port is connected to the storage port, and the storage port can be connected to a storage device through the second I / O port.

[0117] Optionally, the second I / O port can be directly connected to the storage device via a bus or via a connector.

[0118] In an optional embodiment, refer to Figure 8 The second I / O port 251 is connected to the storage port 250, and the storage port 250 can be connected to the storage device 252 through the second I / O port 251. Specifically, the second I / O port 251 is directly connected to the storage device 252 via the bus 253, or connected to the storage device 252 via the connector 254. The storage device 252 is mounted on the connector 254.

[0119] Optionally, the second I / O port can be a high-speed SerDes (Serializer / Deserializer) port. A high-speed SerDes port is an interface technology for high-speed data transmission, used to transfer large amounts of data between the processor and peripheral devices. SerDes technology converts parallel data into serial signals for transmission over relatively small and inexpensive physical links, and can provide higher data transfer rates. Therefore, using a high-speed SerDes port can achieve signal or data transmission between the processor and peripheral devices, while meeting high bandwidth requirements, improving data transfer rates, and reducing latency. However, when using a high-speed SerDes port for data transmission, a specific link needs to be established for communication. Therefore, both parties—the high-speed SerDes port and the peripheral device—need to use the same protocol to establish an effective data link.

[0120] Optionally, there can be multiple high-speed SerDes ports, and each high-speed SerDes port can establish multiple links. The number of peripheral devices connected to the processor via the bus shall not exceed the number of links established by all high-speed SerDes ports.

[0121] In an optional embodiment, the storage port can be configured as SATA (Serial Advanced Technology Attachment, ATA) via a high-speed SerDes port. That is, the link of the high-speed SerDes port can be configured to support the SATA protocol. The SATA protocol is an interface protocol for data transmission in computer storage devices. It transmits data serially, thereby reducing signal interference and increasing transmission distance and capacity. Correspondingly, the bus used to connect the storage port and the storage device located on the connector can be a SATA bus supporting the same protocol, and the storage device can be a SATA device supporting the same protocol.

[0122] Optionally, when connecting the storage port to the storage device, the storage port can connect to the SATA device via a high-speed SerDes port. The high-speed SerDes port and the SATA device can be directly connected via a bus; or connected via a connector (e.g., a standard 7-pin SATA connector, MCIO connector, Slimline connector, or M.2 connector), with the SATA device mounted on the connector.

[0123] In one optional embodiment, taking a network port connection to a network device as an example, Figure 9 An exemplary diagram illustrating the connection structure between a network port and a network device provided in an embodiment of this application is shown. (Refer to...) Figure 9 The connection structure may include: a network port 260, and peripheral devices connected to the network port 260 through a second I / O port: a network device 261 and a gigabit Ethernet port 262.

[0124] In an optional implementation, the network port can be used as a second peripheral port. The second I / O port is connected to the network port, and the network port can connect to peripheral devices through the second I / O port.

[0125] Optionally, if the peripheral device connected to the network port is a network device, the second I / O port can be directly connected to the network device via a bus.

[0126] In an optional embodiment, refer to Figure 9 The second I / O port 263 is connected to the network port 260, and the network port 260 can be connected to the network device 261 through the second I / O port 263. Specifically, the second I / O port 263 and the network device 261 can be directly connected through the bus 264.

[0127] Optionally, if the peripheral device connected to the network port is an Ethernet port, the second I / O port can be connected to the network device through a physical layer interface chip.

[0128] In an optional embodiment, refer to Figure 9 The second I / O port 265 connects to network port 260, and network port 260 can connect to Gigabit Ethernet port 262 through the second I / O port 265. A Gigabit Ethernet port is a network interface that supports Gigabit Ethernet speeds, providing fast data transmission speeds to meet the needs of most network applications.

[0129] Furthermore, the second I / O port 265 and the Gigabit Ethernet port 262 can be connected via the physical layer interface chip 266. The PHY chip (physical layer interface chip) is responsible for processing physical layer signals and data conversion and can be used in conjunction with the Gigabit Ethernet port.

[0130] The PHY chip can be connected to the Gigabit Ethernet port via a cable (e.g., a H2O cable) to transmit data and signals. A cable is a way of directly connecting different devices (such as processors and peripherals) in a network or computer system using cables or other physical lines. Through these cables or physical lines, data and information can be transmitted between the processor and peripherals.

[0131] The PHY chip is connected to the Gigabit Ethernet port via a cable. On the one hand, the Gigabit Ethernet port can convert data from the processor into analog signals and send them to the network through the PHY chip, enabling high-speed data transmission. On the other hand, by connecting the Gigabit Ethernet port and the network port, the processor can establish network connections with other network devices (such as switches and routers), enabling data transmission and reception and communication, and improving the network performance and communication capabilities of the processor and other peripheral devices such as network devices.

[0132] In an optional implementation, the second I / O port can be a high-speed SerDes port. The network port can be configured as XGBE (10 Gigabit Ethernet (10GBE)) using a high-speed SerDes port; that is, a high-speed SerDes port can be configured as an XGBE port supporting the XGBE protocol. Here, GBE refers to Gigabit Ethernet, and XGBE refers to 10GBE. XGBE is a high-speed Ethernet protocol characterized by high speed, high efficiency, high reliability, and high flexibility, used for high-speed data transmission.

[0133] Optionally, the network port can connect to network devices via an XGBE port, and the XGBE port and network devices can be directly connected via a bus. The network device can be any one of the following protocols: 10GBASE-KR, SFI (SerDes Framer Interface), or SGMII (Serial Gigabit Media Independent Interface). These three protocols are different types of high-speed Ethernet protocols and can be used with XGBE-enabled network devices.

[0134] Optionally, the network port can be connected to the Gigabit Ethernet port via the XGBE port, and the XGBE port and the Gigabit Ethernet port can be connected via a PHY chip.

[0135] In one optional embodiment, taking the management port connection to the management device as an example, Figure 10 An exemplary diagram illustrating the connection structure between the management port and the management device provided in this application embodiment is shown. (Refer to...) Figure 10 The connection structure may include: a management port 270, and peripheral devices connected to the management port 270 through an intermediate connection device.

[0136] In an optional implementation, the management port can be used as a second peripheral port, and the management port can be connected to peripheral devices through an intermediate connection device.

[0137] Optionally, the intermediate connection device may include a BMC chip (remote management control chip) and a bus switching chip. The BMC chip has remote management capabilities, enabling it to manage and monitor the computer system's hardware, operating system, and applications. Therefore, a BMC chip can be used in a computer system to manage the processor and peripheral devices. Specifically, the BMC chip connects between the management port and the peripheral devices, while the bus switching chip connects between the management port and the BMC chip, as well as between the BMC chip and the peripheral devices.

[0138] In a further optional implementation, the management port may include multiple interfaces that implement different functions, and the BMC chip may include: an adapter interface, a management module, and a bus interface. Specifically, the adapter interface is adapted to at least some of the interfaces in the management port, the management module is adapted to at least some of the peripheral devices connected to the management port, and the bus interface is adapted to the bus switching chip.

[0139] Optional, refer to Figure 10The interfaces configured inside the management port may include: a first UART interface 2721, a first PCIe interface 2731, a first eSPI interface 2741, a first USB interface 2751, and a first SPI interface 2761.

[0140] Correspondingly, the adapter interfaces provided within the BMC chip may include: a second PCIe interface 2733 connected to the first PCIe interface 2731 via a PCIe bus 2732; a second eSPI interface 2743 connected to the first eSPI interface 2741 via an eSPI bus 2742; and a second USB interface 2753 connected to the first USB interface 2751 via a USB bus 2752. The bus interfaces provided within the BMC chip that are compatible with the bus switching chip may include: a second UART interface 2722 and a second SPI interface 2762.

[0141] In an optional implementation, the BMC chip connects to the interface in the management port via an adapter interface within the BMC chip to achieve connection to the management port. The bus switching chip connects to the BMC chip via a compatible bus interface within the BMC chip. The following examples, using multiple different interfaces in the management port, illustrate the connection methods between the management port and the BMC chip, the bus switching chip, and peripheral devices.

[0142] Optional, refer to Figure 10 The first UART interface 2721 of the management port and the second UART interface 2722 of the BMC chip are connected to the first bus switching chip 2723, which is also connected to the UART device 2724. The first UART interface 2721 and the first bus switching chip 2723 are connected via UART bus 2725, and the second UART interface 2722 of the BMC chip is also connected to the first bus switching chip 2723 via UART bus 2725. The UART device is a peripheral device that supports the UART protocol.

[0143] UART is a serial communication protocol, and the UART interface is a standard interface for serial communication used to transmit data between devices. For example, the management port can connect to a UART device through the first UART interface to send and receive data. The BMC chip communicates with the processor through the second UART interface, reading information such as the computer system status and data sent by the processor, and can also send commands or instructions to the processor for control and management operations. In other words, through the UART interface, the BMC chip can communicate bidirectionally with the processor, managing the processor's serial port functions. Simultaneously, the BMC chip connects to peripheral devices through a bus switching chip, enabling serial communication and control of these devices.

[0144] Optional, refer to Figure 10 The first SPI interface 2761 of the management port and the second SPI interface 2762 of the BMC chip are connected to the second bus switching chip 2763, which is also connected to the BIOS Flash chip 2764. The first SPI interface 2761 and the second bus switching chip 2763 are connected via an SPI bus 2765, and the second SPI interface 2762 of the BMC chip is also connected to the second bus switching chip 2763 via an SPI bus 2765.

[0145] The management port connects to the BIOS Flash chip via the first SPI interface, allowing it to read BIOS firmware data or write updated firmware. The BMC chip connects to the second bus switching chip via the second SPI interface, and then to the BIOS Flash chip, enabling it to read and write firmware data, thus allowing the BMC chip to update and manage the system firmware.

[0146] Optional, refer to Figure 10 The first PCIe interface 2731 of the management port and the second PCIe interface 2733 of the BMC chip can be directly connected via the PCIe bus 2732.

[0147] PCIe (Peripheral Component Interconnect Express) is a high-speed serial bus protocol based on point-to-point connections, used to connect processors and peripheral devices for data communication, offering higher data transfer rates and stability. In a specific implementation, the second PCIe interface of the BMC chip and the first PCIe interface in the management port, which support the same protocol, can be directly interconnected via the PCIe bus to achieve data communication between the processor and the BMC chip.

[0148] Optional, refer to Figure 10 The first eSPI interface 2741 of the management port and the second eSPI interface 2743 of the BMC chip can be directly connected via the eSPI bus 2742.

[0149] eSPI (enhanced Serial Peripheral Interface) is an interface protocol for computer system management and control, providing functions such as remote monitoring, remote control, and surveillance. In a practical implementation, the second eSPI interface of the BMC chip and the first eSPI interface in the management port, which support the same protocol, can be directly interconnected via the eSPI bus. This eSPI interface then enables the management of data communication between the processor and the BMC chip.

[0150] Optional, refer to Figure 10 The first USB interface 2751 of the management port and the second USB interface 2753 of the BMC chip can be directly connected via the USB bus 2752.

[0151] The USB interface is a high-speed data transfer interface that supports high-speed data transmission, multiple device connections, and data format conversion. In its implementation, the second USB interface of the BMC chip and the first USB interface in the management port, which support the same protocol, can be directly interconnected via the USB bus. This allows for the input of external data during data management.

[0152] In the optional implementation, refer to Figure 10 The BMC chip 271 also includes a management module adapted to at least some peripheral devices connected to the management port. This management module may include a VGA (Video Graphics Array) display module 2771 and a network module 2781. The peripheral device connected to the VGA display module 2771 via the VGA display bus 2772 is a display device 2773, and the peripheral device connected to the network module 2781 via the network 2782 is a remote host computer 2783.

[0153] VGA is a display interface standard used in devices such as computer monitors and projectors. A VGA display module is a hardware module that converts digital image signals into VGA interface output. Through the VGA display module, the BMC chip can remotely access the server's management interface and display it on a display device, enabling server control and monitoring without a physical connection. In other words, the VGA display module integrated into the BMC chip provides a more convenient and flexible way to remotely manage servers.

[0154] In an optional implementation, the VGA display module in the BMC chip can be connected to the display device via the VGA display bus to output system information to the display device.

[0155] A network module is a hardware module used to implement network connectivity, enabling remote management and monitoring of servers or computer systems. Through a network module, the BMC chip can connect to a local area network (LAN) or the internet, providing a remote access interface to the server's management interface without requiring a physical connection, saving time and costs.

[0156] A remote host computer refers to a computer that controls and monitors equipment via a network or other remote means. The remote host computer can send commands and requests to the BMC chip and achieve remote operation and monitoring through the BMC chip's settings.

[0157] In an optional implementation, the network module in the BMC chip can connect to a remote host computer via a network to achieve remote management and monitoring functions.

[0158] As can be seen, the computer system provided in this application embodiment has multiple peripheral ports in the processor adapted to various types of peripheral devices, and provides two ways for the processor to connect to the peripheral devices. Specifically, the first part of the processor's peripheral ports is directly connected to the peripheral devices via a bus, while the second part of the processor's peripheral ports (excluding the first part) can be connected to the peripheral devices via an intermediate connection device. Therefore, by providing multiple peripheral ports adapted to various types of peripheral devices in the processor, and with the aforementioned two connection methods, the processor can support the connection of different types of peripheral devices, ensuring the normal operation of the processor.

[0159] This application also provides a system-on-a-chip, which includes the computer system described in the foregoing embodiments.

[0160] This application provides an electronic device, which includes the system-on-a-chip described in the foregoing embodiments.

[0161] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0162] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A computer system, It is characterized in that include: A processor and a plurality of peripheral devices connected to the processor; The processor includes multiple types of peripheral ports, one type of peripheral port is connected to one type of peripheral device; The multiple types of peripheral ports include a first part of peripheral ports and a second part of peripheral ports, the first part of peripheral ports is at least one type of peripheral ports among the multiple types of peripheral ports, and the second part of peripheral ports is other types of peripheral ports among the multiple types of peripheral ports except the first part of peripheral ports; The first part of the peripheral ports is directly connected to the connected peripheral devices via a bus; the second part of the peripheral ports is connected to the connected peripheral devices via an intermediate connection device.

2. The computer system according to claim 1, It is characterized in that The intermediate connection device includes: a connector; The peripheral devices connected to the second part of peripheral ports are arranged on the connector.

3. The computer system according to claim 1, It is characterized in that The intermediate connection device includes: a bus switch chip for allocating a bus, and a remote management control chip connected to the bus switch chip; The remote management control chip is connected between the second peripheral port and the peripheral device; the bus switch chip is connected between the second peripheral port and the remote management control chip, and between the remote management control chip and the peripheral device.

4. The computer system according to claim 3, It is characterized in that The intermediate connection device also includes: a level conversion chip; The level conversion chip is connected between the remote management control chip and the bus switching chip.

5. The computer system according to claim 4, It is characterized in that The remote management control chip includes: an adapter interface, a management module and a bus interface; wherein the adapter interface is adapted to at least part of the interfaces in the second part of the peripheral ports, the management module is adapted to at least part of the peripheral devices connected to the second part of the peripheral ports, and the bus interface is adapted to the bus switching chip.

6. The computer system according to claim 5, It is characterized in that The second part of the peripheral ports is a management port, and the interfaces in the management port include: a first UART interface, a first PCIe interface, a first eSPI interface, a first USB interface and a first SPI interface; the bus switching chip includes a first bus switching chip and a second bus switching chip; The management module of the remote management control chip includes: a VGA display module connected to the display device, and a network module connected to the remote host computer; The adapter interface of the remote management control chip includes: a second PCIe interface connected to the first PCIe interface via a PCIe bus, a second eSPI interface connected to the first eSPI interface via an eSPI bus, and a second USB interface connected to the first USB interface via a USB bus; The bus interface of the remote management control chip includes: a second UART interface and a second SPI interface; wherein, the first UART interface and the second UART interface are connected to the first bus switching chip, and the first bus switching chip is also connected to the UART device; the first SPI interface and the second SPI interface are connected to the second bus switching chip, and the second bus switching chip is also connected to the BIOS Flash chip.

7. The computer system according to claim 1, It is characterized in that The first part of the peripheral ports includes a power port; the power port includes an SVI interface and a core power supply; the peripheral device includes a VR chip; The SVI interface is directly connected to the VR chip via an SVI bus.

8. The computer system according to claim 1, It is characterized in that The first part of the peripheral ports includes a memory port; the memory port includes a memory channel; the peripheral device includes a memory chip; The memory channel is directly connected to the memory chip via a memory bus.

9. The computer system according to claim 2, It is characterized in that The second part of peripheral ports includes a memory port; the memory port includes a memory channel; the peripheral device includes a memory stick; The memory channel is connected to the memory bar through the connector.

10. The computer system according to claim 1, It is characterized in that The first part of peripheral ports includes a first IO port; the first IO port includes a first IO interface; the peripheral device includes a first IO device; The first IO interface is directly connected to the first IO device via an IO bus.

11. The computer system according to claim 4, It is characterized in that The second part of peripheral ports includes a first IO port; the first IO port includes a first IO interface; the peripheral device includes a first IO device; The remote management control chip is connected between the first IO interface and the first IO device; the bus switch chip is connected between the first IO interface and the remote management control chip, and between the remote management control chip and the first IO device.

12. The computer system according to claim 2, It is characterized in that The second part of the peripheral ports includes a USB port; the USB port includes a USB interface; the peripheral device is a USB device compatible with the USB interface; The USB interface is connected to the USB device through the connector.

13. The computer system according to claim 1 or 2, It is characterized in that The second portion of peripheral ports includes storage ports; the peripheral devices include storage devices; The storage port is connected to the storage device via a second IO port; the second IO port is directly connected to the storage device via a bus, or is connected to the storage device via a connector.

14. The computer system according to claim 1, It is characterized in that The second part of peripheral ports includes a network port; the network port is connected to the peripheral device through the second IO port; The peripheral device includes a network device and an Ethernet port; the second IO port is directly connected to the network device via a bus, and the second IO port is connected to the Ethernet port via a physical layer interface chip.

15. A system on a chip, It is characterized in that The system on chip comprises the computer system according to any one of claims 1-14.

16. An electronic device, It is characterized in that The electronic device comprises the system on chip as claimed in claim 15.

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