Network-on-chip structure, processor and electronic equipment
By dividing the router into packets and adopting series connection method, the cross-switch scale and complexity of the on-chip network are reduced, the problems of complex circuits and high energy consumption in the prior art are solved, and the processor performance is improved.
Patent Information
- Application Number
- CN202420267408.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-02
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2034-02-02
AI Technical Summary
The cross-switch scale of existing on-chip networks is large, resulting in complex circuits, large area and energy consumption, and high delay, affecting processor performance.
Divide multiple routers into two packets with the same number. The routers in each packet are connected in series in sequence, and communicate through access lines, left lines, right lines and longitudinal lines to reduce the cross-switch scale of each router and Complexity.
It effectively reduces the circuit area and energy consumption of the on-chip network, improves performance, and reduces delay.
Smart Images
Figure CN222169830U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of computers, and in particular to an on-chip network structure, a processor and an electronic device. Background Art
[0002] The on-chip network is a key technology of the multi-processor architecture. It is the interconnection path and communication network inside the processor, responsible for message transmission, and is the basis for the collaborative work of processors.
[0003] At present, the on-chip network includes routers with a specification of N×N, that is, the main structure of the on-chip network is composed of multiple routers with N rows and N columns. Each router is connected to the corresponding processor core and cache. This means that for each router, there are five transmission directions: up, down, left, right, and external (the direction of accessing the processor core and cache). Therefore, the scale of the cross switch of each router in the on-chip network is 5×5.
[0004] In the related art, the crossbar switch of the on-chip network is large in scale, which leads to complex circuits of the on-chip network, large circuit area and energy consumption. Utility Model Content
[0005] In view of the above problems, embodiments of the present utility model are proposed to provide a network-on-chip structure, a processor, and an electronic device that overcome the above problems or at least partially solve the above problems.
[0006] In a first aspect, an embodiment of the utility model discloses a network-on-chip structure, the network-on-chip structure comprising:
[0007] A plurality of routers, and an access device correspondingly connected to each of the plurality of routers;
[0008] The plurality of routers are divided into two groups of the same number; the routers between the two groups correspond to each other one by one; the routers in each group are connected in series in sequence; the two routers corresponding to each other are connected to each other;
[0009] Each of the routers includes an access line, a left line, a right line and a longitudinal line;
[0010] The access line is used to connect to the access device; the left line and the right line are used to connect to adjacent routers in the same group; and the vertical line is used to connect to a corresponding router in another group.
[0011] In a second aspect, an embodiment of the utility model discloses a processor, wherein the processor includes an on-chip network structure.
[0012] In a third aspect, an embodiment of the utility model further discloses an electronic device, comprising a processor.
[0013] In the embodiment of the utility model, multiple routers can be divided into two groups of the same number, so that each group contains the same number of routers, and the routers in each group are connected in series in sequence, the routers in the two groups correspond one to one, and the two corresponding routers are connected to each other, and each router can contain 4 transmission directions: the transmission direction corresponding to the access line, the transmission direction corresponding to the left line, the transmission direction corresponding to the right line, and the transmission direction corresponding to the longitudinal line, and the design of the 4 transmission directions has met the mutual communication between the two groups of routers and the mutual communication between the router and the access device, that is, it meets the internal communication requirements of the on-chip network. Compared with the related art, the utility model, on the basis of meeting the on-chip network communication, because the number of lines of the router is reduced, the scale of the cross switch of each router is greatly reduced, so the complexity of the cross switch is greatly reduced, so that the circuit area occupied by the on-chip network is reduced, and the energy consumption is reduced. At the same time, the delay of the on-chip network is also reduced, and the performance is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 It is a schematic diagram of a network-on-chip structure provided by an embodiment of the utility model;
[0015] Figure 2 This is a schematic diagram of a router connection structure provided by an embodiment of the utility model;
[0016] Figure 3 A schematic diagram comparing the transmission directions of the network on chip in the related technology and the embodiment of the utility model;
[0017] Figure 4 This is a schematic diagram of another on-chip network structure provided by an embodiment of the utility model
[0018] Figure 5 is a schematic diagram of another network-on-chip structure provided by an embodiment of the utility model;
[0019] Figure 6 A schematic diagram of a processor provided by an embodiment of the utility model
[0020] Figure 7 It is a schematic diagram of an electronic device provided by an embodiment of the utility model. DETAILED DESCRIPTION
[0021] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.
[0022] refer to Figure 1 , which shows a schematic diagram of an on-chip network structure provided by an embodiment of the utility model, including: multiple routers, and access devices corresponding to each of the multiple routers; the multiple routers are divided into two groups of the same number: group 1 and group 2; the routers between the two groups correspond one to one; the routers in each group are connected in series in sequence; the two routers corresponding to each other are connected to each other; refer to Figure 2 Each router includes an access line, a left line, a right line and a longitudinal line; the access line of the router is used to connect to the access device; the left line and the right line of the router are used to connect to the adjacent routers in the same group; the longitudinal line of the router is used to connect to the corresponding router in another group.
[0023] In practical applications, although the multiple processor cores in a multi-core processor chip each execute their own code, data needs to be shared and synchronized between the processor cores. Therefore, the hardware structure of the multi-core processor must support efficient inter-core communication, and the performance of the on-chip communication structure will directly affect the performance of the processor.
[0024] Therefore, the Network on Chip (NoC) aims to solve the communication problem within the multi-core processor. The NoC is an integrated circuit on a network-based communication subsystem. The NoC is a packet switching network based on routers between systems on chip. The NoC technology draws on the interconnected network structure of parallel computers, integrating a large number of computing resources and an on-chip communication network connecting these resources on a single chip. Each processor core has an independent router and its private cache, and is connected together through an on-chip communication network. The processor cores use a message communication mechanism, and use routers and packet switching technology to replace the on-chip bus of related technologies to complete the communication task, thereby solving various bottleneck problems caused by bus interconnection in related technologies.
[0025] The bus structure of the related technology adopts a time-division multiplexing working mode, so only one mutual communication process can be carried out on the same bus at the same time. The crossbar switch interconnection structure of the on-chip network can effectively improve the bandwidth of data exchange. The crossbar switch can connect the input line and the output line in any order. The crossbar switch can be regarded as a set of switches organized in the form of a matrix. The crossbar switch has multiple input lines and output lines, which are cross-connected together. The crosspoint can be regarded as a single switch. When the switch at the connection point between an input line and an output line is turned on, a connection is established between the input line and the output line. There can be multiple conductive connections, so that multi-channel communications can run in parallel.
[0026] Furthermore, the scale and complexity of the crossbar switch of the on-chip network directly affect the circuit area and energy consumption of the on-chip network. The higher the scale and complexity of the crossbar switch, the greater the circuit area and energy consumption. The scale and complexity of the crossbar switch are directly proportional to the number of lines each router in the on-chip network. Therefore, reducing the scale and complexity of the crossbar switch is an important issue to improve the performance of the on-chip network.
[0027] Specifically, Figure 1 The figure shows a network-on-chip structure containing 16 routers, that is, the total number of routers in the network-on-chip structure is an even number. In this case, the 16 routers can be divided into two groups with the same number: group 1 and group 2, so that each group contains 8 routers and the routers in each group are connected in series in sequence. The routers in the two groups correspond to each other one by one and the two corresponding routers are connected to each other to form a Figure 1 Based on the on-chip network structure, each router only includes an access line, a left line, a right line and a longitudinal line to realize the communication of the on-chip network. Among them, the access line of the router is used to connect to the access device corresponding to the router, the left line and the right line of the router are used to connect to the adjacent routers in the same group; the longitudinal line of the router is used to connect to the router corresponding to the router in another group. It should be noted that the embodiment of the utility model can also include a scheme in which the total number of routers is other even numbers, such as the total number of routers is 10, 20, 24, 28, etc., and the embodiment of the utility model does not specifically limit this.
[0028] In an embodiment of the utility model, based on the above design, all routers of the on-chip network adopt a 2×N layout, and each router can include 4 transmission directions: a transmission direction corresponding to the access line, a transmission direction corresponding to the left line, a transmission direction corresponding to the right line, and a transmission direction corresponding to the longitudinal line. The design of the 4 transmission directions can meet the mutual communication between the two groups of routers and the mutual communication between the router and the access device, that is, it meets the internal communication needs of the on-chip network.
[0029] Furthermore, the embodiment of the utility model can also be configured that: in the same group, a data packet received by the left line of a router will not be returned from the left line. That is, a data packet sent by the right line of a router will not be returned from the right line.
[0030] For example, refer to Figure 3 , which shows a schematic diagram comparing the transmission directions of the on-chip network of a related technology and an embodiment of the utility model. Based on the on-chip network design (B) of the embodiment of the utility model, the scale of the cross switch is 4×3, compared with the scale of the cross switch of the on-chip network design (A) of the related technology being 5×5. On the basis of meeting the on-chip network communication, the embodiment of the utility model greatly reduces the scale of the cross switch, so the complexity of the cross switch is also greatly reduced, so that the circuit area occupied by the on-chip network is reduced, and the energy consumption is reduced. At the same time, the delay of the on-chip network is also reduced, the performance is greatly improved, the demand for wiring resources of the on-chip network is also reduced, and the production cost is reduced.
[0031] In summary, the scheme of the utility model can divide multiple routers into two groups of the same number, so that each group contains the same number of routers, and the routers in each group are connected in series in sequence, the routers in the two groups correspond one to one, and the two corresponding routers are connected to each other, and each router can contain 4 transmission directions: the transmission direction corresponding to the access line, the transmission direction corresponding to the left line, the transmission direction corresponding to the right line, and the transmission direction corresponding to the longitudinal line, and the design of the 4 transmission directions has met the mutual communication between the two groups of routers and the mutual communication between the router and the access device, that is, it meets the internal communication requirements of the on-chip network. Compared with the related art, the utility model, on the basis of meeting the on-chip network communication, has a reduced number of lines in the router, which greatly reduces the scale of the cross switch, so the complexity of the cross switch is greatly reduced, so that the circuit area occupied by the on-chip network is reduced, and the energy consumption is reduced. At the same time, the delay of the on-chip network is also reduced, and the performance is greatly improved.
[0032] Optional, see Figure 1 , in each group, the left line of the router at the head end and the right line of the router at the tail end are vacant.
[0033] In an embodiment of the utility model, since the left side of the router at the head end in each group is not connected to other routers, and the right side of the router at the tail end is not connected to other routers, the left line of the router at the head end in each group and the right line of the router at the tail end can be left vacant.
[0034] Optional, see Figure 4, which shows a schematic diagram of another on-chip network structure provided by an embodiment of the utility model, the on-chip network structure also includes: 1 additional router, and an additional access device connected to the additional router; the additional router is respectively connected to the two routers at the head end or the tail end of the two groups.
[0035] In the embodiment of the utility model, when the total number of routers in the on-chip network structure is an odd number, one router can be selected as an additional router, and the remaining routers can be divided into two groups with the same number, that is, all routers of the on-chip network are arranged in a 2×N+1 manner ( Figure 4 The additional router is connected to the corresponding additional access device, and the additional router is connected to the two routers at the head end or the tail end of the two groups respectively ( Figure 4 The scheme of connecting to two routers at the tail ends of two groups is shown. In the router topology of the entire network structure, the mutual communication between routers (including additional routers) and the mutual communication between routers (including additional routers) and access devices (including additional access devices) are satisfied.
[0036] Therefore, the embodiment of the utility model is further compatible with the on-chip network structure design when the number of routers is an odd number. Compared with the N×N layout method of the related art, the number of routers can only be expanded to 4, 9, 16, 25, 36, 49, 64..., which is extremely insufficient in expansion flexibility. The embodiment of the utility model accepts the layout scheme of the number of routers being an even number or an odd number, and has higher expansion flexibility.
[0037] Optional, see Figure 5 , which shows a schematic diagram of another on-chip network structure provided by an embodiment of the utility model, the on-chip network structure also includes: 2 additional routers, and an additional access device connected to each additional router; one additional router is connected to the two routers at the head end of the two groups, and the other additional router is connected to the two routers at the tail end of the two groups.
[0038] In the embodiment of the utility model, for another case where the total number of routers in the on-chip network structure is an even number, two routers can be selected as additional routers, and the remaining routers can be divided into two groups with the same number, that is, all routers of the on-chip network are arranged in a 2×N+2 manner ( Figure 5The additional routers are connected to the corresponding additional access devices, and one additional router is connected to the two routers at the head end of the two groups, and the other additional router is connected to the two routers at the tail end of the two groups. In the router topology of the entire network structure, the mutual communication between routers (including additional routers) and the mutual communication between routers (including additional routers) and access devices (including additional access devices) are satisfied.
[0039] Optional, see Figure 4 and Figure 5 The additional router includes: a longitudinal line, a transverse line and an access line; the access line of the additional router is connected to the additional access device; the transverse line and the longitudinal line of the additional router are respectively connected to the two routers at the head end of the two groups, or the transverse line and the longitudinal line of the additional router are respectively connected to the two routers at the tail end of the two groups.
[0040] In the embodiment of the utility model, the additional router only includes: vertical lines, horizontal lines and access lines, which can realize the communication connection between the additional router and the router in the group, and the connection between the additional router and the additional access device, thereby further reducing the complexity and scale of the cross switch in the on-chip network, so that the circuit area occupied by the on-chip network is further reduced, and the energy consumption is further reduced.
[0041] Optional, see Figure 4 and Figure 5 , the additional access devices include a processor core and a cache; or the additional access devices include any one of a memory, a graphics card, and a network card.
[0042] In the embodiment of the present utility model, Figure 4 and Figure 5 In one case shown, the additional access device may include a processor core and a cache, thereby enabling communication of a multi-core processor architecture, and the cache may be a cache cache, which is used to temporarily store memory data accessed by the processor core to improve the access speed of the data. In another case, the additional access device includes any one of a memory, a graphics card, and a network card, that is, through a rich selection of additional access devices, the functional implementation of the multi-core processor architecture is improved.
[0043] Optional, see Figure 1 , the access device includes a processor core and a cache.
[0044] In an embodiment of the utility model, an access device connected to a router may include a processor core and a cache, thereby enabling communication of a multi-core processor architecture. The cache is used to temporarily store communication interaction data to improve data access speed.
[0045] Reference Figure 6 , which shows a schematic diagram of a processor provided by an embodiment of the utility model, and the processor includes the on-chip network structure provided by the above embodiment.
[0046] Reference Figure 7 , which shows a schematic diagram of an electronic device provided by an embodiment of the utility model, the electronic device may include Figure 6 processor.
[0047] Those skilled in the art will readily come up with other embodiments of the present invention after considering the specification and practicing the utility model disclosed herein. The present invention is intended to cover any variation, use or adaptation of the present invention, which follows the general principles of the present invention and includes common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the present invention are indicated by the following claims.
[0048] It should be understood that the present invention is not limited to the precise structure described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.
Claims
1. A network-on-chip structure, characterized in that: The network-on-chip structure comprises: A plurality of routers, and an access device correspondingly connected to each of the plurality of routers; The plurality of routers are divided into two groups of the same number; the routers between the two groups correspond to each other one by one; the routers in each group are connected in series in sequence; the two routers corresponding to each other are connected to each other; Each of the routers includes an access line, a left line, a right line and a longitudinal line; The access line is used to connect to the access device; the left line and the right line are used to connect to adjacent routers in the same group; and the vertical line is used to connect to a corresponding router in another group.
2. The network-on-chip structure according to claim 1, characterized in that: In each of the groups, the left line of the router at the head end and the right line of the router at the tail end are vacant.
3. The network-on-chip structure according to claim 1, characterized in that: The network-on-chip structure further includes: 1 additional router, and an additional access device connected to the additional router; The additional router is respectively connected to two routers at the head end or the tail end of the two groups.
4. The network-on-chip structure according to claim 1, characterized in that: The network-on-chip structure further includes: 2 additional routers, and additional access devices connected to each of said additional routers; One of the additional routers is respectively connected to the two routers at the head ends of the two groups, and the other additional router is respectively connected to the two routers at the tail ends of the two groups.
5. The network-on-chip structure according to claim 3 or 4, characterized in that: The additional router includes: a longitudinal line, a transverse line and an access line; An access line of the additional router is connected to the additional access device; The transverse line and the longitudinal line of the additional router are respectively connected to the two routers at the head end of the two groups, or the transverse line and the longitudinal line of the additional router are respectively connected to the two routers at the tail end of the two groups.
6. The network-on-chip structure according to claim 3 or 4, characterized in that: The additional access device includes a processor core and a cache; Or the additional access device includes any one of a memory, a graphics card, and a network card.
7. The network-on-chip structure according to claim 1 or 2, characterized in that: The access device includes a processor core and a cache.
8. A processor, characterized in that: The processor comprises: a network-on-chip structure as described in any one of claims 1-7.
9. An electronic device, characterized in that: The method comprises a processor as claimed in claim 8.