Detection baseband circuit

Abstract

The utility model discloses a detection baseband circuit, which comprises a detection baseband internal circuit, an external power supply end and an external radio frequency circuit, and the detection baseband internal circuit comprises a filtering module which is directly connected with an external radio frequency signal receiving end and is used for carrying out preliminary filtering processing on a received detection signal emitted by the radio frequency circuit. The filtering module is directly connected with the sampling module and is used for carrying out analog-to-digital conversion on the processed detection signal to convert the detection signal into a digital signal; and the sampling module is directly connected with the digital processing module and is used for processing the digital signal. According to the detection baseband circuit, the influence of noise and clutter is reduced through the accumulation relation of chips with different functions, and the processing efficiency of detection signals is improved.

Description

Technical Field

[0001] The utility model relates to the field of detection signal processing, in particular to a detection baseband circuit. Background Art

[0002] In recent years, with the development of science and technology and the progress of society, the application of detection signals in the field of collision avoidance has become more extensive and the demand has increased.

[0003] The existing technology usually adopts the working mode of transmitting detection signals by radio frequency circuits. When the detection signals encounter obstacles, echo signals are generated. The radio frequency circuits filter out clutter and reduce noise on the received detection signals to reduce the shielding effect of noise and clutter on the target. This detection method can only obtain approximate target distance and speed information, and the signal-to-noise ratio and adjacent targets are greatly affected. Utility Model Content

[0004] The main technical problem solved by the utility model is to provide a detection baseband circuit to solve the problems in the prior art of small signal-to-noise ratio in processing detection signals and strong shielding effect of clutter on targets.

[0005] To solve the above problems, a technical solution adopted by the utility model is to provide a detection baseband circuit, including a filtering module directly connected to the external RF signal receiving end, used to perform low-pass filtering on the received detection signal; the filtering module is directly connected to the sampling module, used to perform analog-to-digital conversion on the detection signal after the low-pass filtering, and convert it into a digital baseband signal; the sampling module is directly connected to the digital processing module, used to demodulate the digital baseband signal.

[0006] Specifically, the filtering module includes two identical low-pass filter chips, and the low-pass filter chip includes a differential signal input interface, a differential signal output interface and a parameter control interface; the differential signal input interface includes a first differential signal input interface and a second differential signal input interface, which are respectively used to input the orthogonal I and Q signals of the detection signal; the differential signal output interface includes a first differential signal output interface and a second differential signal output interface, which are respectively used to output the filtered I signal and Q signal; the parameter control interface is used to connect an external controller to set the parameters of the low-pass filter chip, including a chip selection input interface pin, a serial data input interface pin, a serial data output interface pin, and a serial clock input interface pin.

[0007] Specifically, the sampling module has two identical analog-to-digital conversion chips, and the analog-to-digital conversion chip includes an analog differential input interface, a clock input interface, a data output interface, and an output enable interface; the analog differential input interface includes a first analog differential input interface and a second analog differential input interface, which are respectively connected to the first differential signal output interface and the second differential signal output interface of the low-pass filter chip, and are used to input the I-path signal and the Q-path signal after filtering; the clock input interface includes a first clock input interface pin and a second clock input interface pin, which are used to input the sampling clock signal of the analog-to-digital conversion chip during use; the data output interface includes a first data output interface and a second data output interface, which are used to output the digital signal after analog-to-digital conversion; the output enable interface includes a first output enable interface and a second output enable interface, which are respectively used to enable the selection of data output of the first data output interface and data output of the second data output interface.

[0008] Specifically, the digital processing module is electrically connected to a first memory, a second memory and a third memory; wherein the first memory includes a FLASH memory for storing result data processed by the digital processing module; the second memory includes an EMMC memory for storing the program of the digital processing module itself; and the third memory includes a DDR memory for temporarily storing intermediate data of the digital processing module during the processing process.

[0009] Specifically, the third memory includes a synchronous dynamic random access memory chip, and the synchronous dynamic random access memory chip includes a DDR address interface, a DDR parameter setting interface, a DDR data output interface, a DDR data input interface and a DDR data selection interface, which are electrically connected to the digital processing module respectively.

[0010] Specifically, the second memory includes an EMMC embedded flash memory chip, and the EMMC industrial-grade embedded flash memory chip includes an EMMC data transmission interface and an EMMC parameter setting interface, which are electrically connected to the digital processing module respectively.

[0011] Specifically, the digital processing module is electrically connected to the Ethernet communication module, the Ethernet communication module includes a network transceiver chip, and the network transceiver chip includes a network data sending interface, a network data receiving interface, a serial data bus interface and a network parameter setting interface, which are electrically connected to the digital processing module respectively.

[0012] Specifically, the network data transmission interface includes a data transmission interface pin, a data transmission clock interface pin, and a data transmission control interface pin, which are used for the network transceiver chip to send data to the digital processing module; the network data reception interface includes a data reception interface pin, a data reception clock interface pin, and a data reception control interface pin, which are used for the network transceiver chip to receive data from the digital processing module; the serial data bus interface includes a data transmission interface pin and a clock signal transmission interface pin, which are used for serial port data transmission between the network transceiver chip and the digital processing module. The network parameter setting interface includes a clock frequency setting interface and a reset interface, which are used to set the parameters of the network receiver chip.

[0013] Specifically, the digital processing module is electrically connected to a mobile storage module, the mobile storage module includes an SD card socket and an SDO expander chip, the SD card socket includes an SD data interface and an SD control interface, the SDO expander chip includes a data transfer interface and an SDO control interface; the data transfer interface is used for transferring data transmission between the digital processing module and the SD card socket.

[0014] Specifically, the digital processing module is electrically connected to the digital transmission module, the digital transmission module is connected to the 4G module, and the 4G module is connected to the 4G antenna for wirelessly transmitting detection data.

[0015] The beneficial effects of the utility model are as follows: the utility model discloses a detection baseband circuit, including a detection baseband circuit, an external power supply terminal and an external detection radio frequency signal receiving terminal, wherein the detection baseband circuit internally includes a filter module, a sampling module and a digital processing module for processing the received detection signal; wherein one end of the filter module is directly connected to the radio frequency circuit for receiving the detection signal, and the other end is directly connected to the sampling module, which is connected to the digital processing module through the sampling module; the filter module is used to perform low-pass filtering on the received detection signal; the sampling module is used to perform analog-to-digital conversion on the filtered detection signal, and the digital processing module is used to process the digital signal. The detection baseband circuit reduces the influence of noise and clutter through the cumulative relationship of different functional chips, thereby improving the efficiency of detection signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of an overall circuit of a detection baseband circuit according to the utility model;

[0017] Figure 2 It is a schematic diagram of a low-pass filter chip for detecting a baseband circuit filter module according to the utility model;

[0018] Figure 3 It is a schematic diagram of the structure of an analog-to-digital conversion chip for detecting a sampling module of a baseband circuit according to the utility model;

[0019] Figure 4 It is a schematic diagram of the structure of a synchronous dynamic random access memory chip for detecting a baseband circuit memory module according to the utility model;

[0020] Figure 5 It is a schematic diagram of the structure of an EMMC industrial-grade embedded flash memory device chip for detecting a baseband circuit embedded flash memory module according to the utility model;

[0021] Figure 6 It is a schematic diagram of the structure of a network transceiver chip for detecting a baseband circuit Ethernet communication module according to the utility model;

[0022] Figure 7 It is a schematic diagram of the SD card structure of a baseband connection module for detecting a baseband circuit according to the utility model;

[0023] Figure 8 It is a schematic diagram of the structure of an SDO port expander chip of a baseband connection module for detecting a baseband circuit according to the utility model;

[0024] Fig. 9 It is a schematic diagram of a sampling interface of a detection baseband circuit digital processing module according to the utility model;

[0025] Fig.10 It is a schematic diagram of a storage interface of a detection baseband circuit digital processing module according to the utility model;

[0026] Fig.11 It is a schematic diagram of a flash memory interface of a detection baseband circuit digital processing module according to the utility model;

[0027] Fig.12 It is a schematic diagram of a physical layer interface of a detection baseband circuit digital processing module according to the utility model;

[0028] Fig.13 The utility model is a schematic diagram of a baseband interface of a detection baseband circuit digital processing module. DETAILED DESCRIPTION

[0029] In order to facilitate the understanding of the present invention, the present invention is described in more detail below in conjunction with the accompanying drawings and specific embodiments. The accompanying drawings provide preferred embodiments of the present invention. However, the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0030] It should be noted that, unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more related listed items.

[0031] like Figure 1 As shown, the detection baseband circuit 1 is connected to the external power supply terminal 2 and the external radio frequency circuit 3. The detection baseband circuit is used to filter the received signal, convert it into a digital signal, and then perform demodulation.

[0032] After the detection baseband circuit 1 receives the detection signal sent by the radio frequency circuit 3, the detection signal first enters the filtering module 6 for filtering processing.

[0033] like Figure 2 As shown, the filter module 6 includes two low-pass filter chips, wherein the first low-pass filter chip U19 has a model number of LTC6602, and the first low-pass filter chip U19 includes a differential signal input interface, a differential signal output interface and a parameter control interface.

[0034] The differential signal input interface includes a first differential signal input interface and a second differential signal input interface, both of which are connected to the detection signal output interface of the radio frequency circuit 3 for receiving the detection signal to be filtered.

[0035] Furthermore, the detection signal includes two orthogonal I and Q signals, the I signal is input from the first differential signal input interface, and the Q signal is input from the second differential signal input interface.

[0036] Further, the first differential signal input interface includes a first forward signal input pin +I NA and a first reverse signal input pin −I NA, and correspondingly, the second differential signal input interface includes a second forward signal input pin +I NB and a second reverse signal input pin −I NB.

[0037] The differential signal output interface includes a first differential signal output interface and a second differential signal output interface, and the two interfaces are connected to the first analog differential input interface and the second analog differential input interface of the sampling module 5 respectively (such as Figure 3 As shown), it is used to input the filtered detection signal into the sampling module 5 for analog-to-digital conversion processing.

[0038] Correspondingly, after filtering, the first differential signal output interface is used to output the I-channel signal input by the first differential signal input interface, and the second differential signal output interface is used to output the Q-channel signal input by the second differential signal input interface.

[0039] Furthermore, the first differential signal output interface includes a first forward signal output pin +OUT and a first reverse signal output pin -OUT, and the above two output pins output signals to the outside through filter resistors R1 and R2 respectively; the corresponding second differential signal output interface includes a second forward signal output pin +OUTB and a second reverse signal output pin -OUTB.

[0040] By filtering the differential signal, it is helpful to eliminate the common mode interference superimposed on the detection signal, and the detection signal is divided into two orthogonal I and Q signals for filtering respectively, in order to adapt the two orthogonal signals to be processed as complex signals. The parameter setting interface is directly connected to the external controller to set the parameters of the low-pass filter chip.

[0041] Furthermore, the above parameter control interface includes a chip selection input interface pin LPF1 / CS, a serial data input interface pin HPF1 / SD I, a serial data output interface pin HPFO / SDO, and a serial clock input interface pin LPFO / SCLK, which are used for parameter setting of the low-pass filter chip U19.

[0042] Preferably, the filter module 6 includes a first low-pass filter chip U19 and a second low-pass filter chip. The function and structure of the second low-pass filter chip are exactly the same as those of the first low-pass filter chip U19, which will not be described here. The purpose of using two low-pass filter chips is to simultaneously receive two detection signals from the radio frequency circuit, and the two detection signals can be used to measure the distance and angle. The detection signal after filtering arrives at the sampling module 5 for sampling and analog-to-digital conversion.

[0043] like Figure 3 As shown, the sampling module 5 includes two analog-to-digital conversion chips, wherein the first analog-to-digital conversion chip U18, model number is AD9238BST-20, and the analog-to-digital conversion chip U18 includes an analog differential input interface, a clock input interface, a data output interface, and an output enable interface. The analog differential input interface includes a first analog differential input interface and a second analog differential input interface, which are respectively connected to the first differential signal output interface and the second differential signal output interface of the first low-pass filter chip U19, and are used to input the filtered I-path signal and Q-path signal.

[0044] Correspondingly, the first analog differential input interface is used to receive the I-channel signal of the first differential signal output interface, and the second analog differential input interface is used to receive the Q-channel signal of the second differential signal output interface.

[0045] Further, the first analog differential input interface includes a first analog forward signal input pin VIN+_A and a first analog reverse signal input pin VIN-_A, and the second analog differential input interface includes a second analog forward signal input pin VIN+_B and a second analog reverse signal input pin VIN-_B.

[0046] The clock input interface includes a first clock input interface pin CLK_A and a second clock input interface pin CLK_B, which are used to input a sampling clock signal of the analog-to-digital conversion chip U18 during use.

[0047] The data output interface includes a first data output interface D0_A to D11_A and a second data output interface D0_B to D11_B, which are respectively connected to a first data receiving interface and a second data receiving interface of the digital processing module 4, and are used to output the digital signal after analog-to-digital conversion.

[0048] The output enable interface includes a first output enable interface OEB_A and a second output enable interface OEB_B, which are used to enable and select data output of the first data output interface and data output of the second data output interface.

[0049] Correspondingly, the first output enable interface OEB_A correspondingly enables and controls the first data output interfaces D0_A to D11_A, and the second output enable interface OEB_B correspondingly enables and controls the second data output interfaces D0_B to D11_B.

[0050] Further, according to the setting of the analog-to-digital conversion chip U18, when the first output enable interface OEB_A is set at a low level, the first output enable interface OEB_A controls the first data output interface to output data, and when the second output enable interface OEB_B is set at a low level, the second output enable interface OEB_B controls the second data output interface to output data.

[0051] Combination Figure 1 The digital signal after analog-to-digital conversion enters the digital processing module 4 for processing, and the processed signal can be temporarily stored and saved for use at any time. The storage module includes a first memory 7, a second memory 8 and a third memory 9.

[0052] Among them, the first memory 7 includes a FLASH memory for storing the result data processed by the digital processing module 4; the second memory 8 includes an EMMC memory for storing the program of the digital processing module 4 itself; the third memory 9 includes a DDR memory for temporarily storing the intermediate data of the digital processing module 4 during the processing process.

[0053] It also includes an Ethernet communication module 11 for physically transmitting processed digital signals, and the Ethernet communication module 11 can perform network data transmission through a network port 111; in addition, it also includes a reset chip module 12 respectively connected to the Ethernet communication module 11 and the digital processing module, for resetting the two modules at the same time to ensure the stability of the circuit system.

[0054] like Figure 4 As shown, the third memory 9 includes a synchronous dynamic random access memory chip U14, model MT41K256M16HA-125I T. The synchronous dynamic random access memory chip U14 includes a DDR address interface, a DDR parameter setting interface, a DDR data output interface, a DDR data input interface, and a DDR data selection interface, which are electrically connected to the digital processing module respectively.

[0055] The DDR address input interface includes a row and column address interface and a BANK address interface. The above address interfaces are electrically connected to the digital processing module 4 and are used to select the storage address of the memory chip.

[0056] The DDR parameter setting interface includes a chip selection input interface, a command input interface, a differential clock input interface, and a clock enable input interface, which are connected to the controller and used to set specific parameters of the synchronous dynamic random access memory chip.

[0057] Among them, the chip selection input interface refers to the first chip selection input interface pin CS, the command input interface includes the first command input interface RAS, the second command input interface CAS, and the third command input interface WE, and the differential clock input interface includes the first differential clock input interface CLK_P and the second differential clock input interface CLK_N, all of which are connected to the differential clock setting interface of the digital processing module 4.

[0058] The clock enable input interface refers to the clock enable input interface CKE, which is connected to the clock enable setting interface of the digital processing module 4 and is used to activate at a high level and disable the internal clock signal at a low level.

[0059] The DDR data output interface refers to the data output interface pins DQ0 to DQ15, which are directly connected to the data input interface of the digital processing module 4 and are used to output data to the digital processing module.

[0060] The DDR data input interface includes a first data input interface pin LDM and a second data input interface pin UDM, which are used to receive data transmitted by the digital processing module 4.

[0061] Furthermore, when writing data, LDM and UDM correspond to the lower 8-bit data and the upper 8-bit data on the data bus respectively.

[0062] The DDR data strobe interface includes a first data strobe interface pin LDQS and a second data strobe interface UDQS, which are used to write data and read data, that is, to achieve synchronous access of data. Furthermore, the first data strobe interface pin LDQS is used for the lower 8 bits of the instruction, and the second data strobe interface UDQS is used for the upper 8 bits of the instruction.

[0063] Preferably, the third memory 9 includes two synchronous dynamic random access memory chips, including a first synchronous dynamic random access memory chip U14 and a second synchronous dynamic random access memory chip. The second synchronous dynamic random access memory chip has the same structure and function as the first synchronous dynamic random access memory chip U14, which will not be described in detail here.

[0064] like Figure 5 As shown, the second memory 8 includes an EMMC industrial-grade embedded flash memory chip U15A, whose model is SDINBDG4-8G-ZA. The EMMC industrial-grade embedded flash memory chip U15A includes an EMMC data transmission interface and an EMMC parameter setting interface, and the above interfaces are electrically connected to the digital processing module.

[0065] Among them, the EMMC data transmission interface refers to the data transmission interface pins DAT0~DAT3, which are connected to the data transmission interface of the digital processing module and are used for data transmission.

[0066] The EMMC parameter setting interface includes a clock input interface pin CLK, a command input interface pin CMD and a reset interface pin RST, which are used to set specific parameters of the EMMC industrial-grade embedded flash memory chip U15A.

[0067] like Figure 6 As shown, the Ethernet communication module 11 includes a network transceiver chip U17, model 88E1512-XX-NNP2I000, and the network transceiver chip U17 includes a network data sending interface, a network data receiving interface, a serial data bus interface, and a network parameter setting interface, which are electrically connected to the digital processing module respectively.

[0068] The network data transmission interface includes data transmission interface pins TXD[0]~TXD[3], data transmission clock interface pin TX_CLK, and data transmission control interface pin TX_CTRL, which are used to control the network transceiver chip U17 to send data to the digital processing module 4.

[0069] The network data receiving interface includes data receiving interface pins RXD[0]~RXD[3], data receiving clock interface pin RX_CLK, and data receiving control interface pin RX_CTRL, which are used to control the network transceiver chip U17 to receive data from the digital processing module 4.

[0070] The serial data bus interface includes a data transmission interface pin MD IO and a clock signal transmission interface pin MDC, which are used for serial data transmission between the network transceiver chip and the digital processing module. The above interfaces are connected to the physical layer interface U9D2 of the digital processing module 4 (see Fig.12 ).

[0071] The network parameter setting interface includes a clock frequency setting interface and a reset interface, which are used to set the parameters of the network receiver chip U17.

[0072] The clock frequency setting interface includes a clock frequency input interface pin XTAL_IN and a clock frequency output interface pin XTAL_OUT.

[0073] Furthermore, the above two interfaces are both connected to the physical layer interface U9D2 of the digital processing module 4, wherein the clock frequency input interface pin XTAL_I N is used to set the clock frequency, for example, to set the clock frequency to 25 MHz.

[0074] The reset interface refers to the reset interface pin RESETn, which is used to reset the current settings of the chip, corresponding to the aforementioned reset chip module 12 connected to the reset interface for reset and reset

[0075] Furthermore, the reset interface includes three interface terminals, wherein the first interface terminal is connected to the reset power interface DVDD_ETH_PHY_B through the protection resistor R11, the second interface terminal is connected to the first reset interface RESET_PS through the first voltage zener diode D1, and the third interface terminal is connected to the second reset interface PS_PHY_RESET_AND through the second voltage zener diode D2.

[0076] The above-mentioned second reset interface PS_PHY_RESET_AND is connected to the physical layer interface U9D2 of the digital processing module 4.

[0077] like Figure 7 As shown, the mobile storage module 101 includes an SD card socket J2 and an SDO expander chip U16, and the SD card socket J2 includes an SD data interface and an SD control interface. The data transfer interface is used for transferring data transmission between the digital processing module and the SD card socket.

[0078] Among them, the SD data interface refers to the data interface pins DAT0~DAT3, which are directly connected to Figure 8 The second data transmission interface of the SDO expander chip in the embodiment.

[0079] The SD control interface includes a clock input interface pin CLK and a command input interface pin CMD. The above interfaces are directly connected to Figure 8The second clock setting interface pin CLKB0 and the second command setting interface pin CMDB0 of the SDO expander chip.

[0080] Furthermore, the SD card socket J2 also includes a card insertion detection pin CD for detecting the insertion of the SD card.

[0081] like Figure 8 As shown, the model of the SDO expander chip U16 is TXS02612RTWR, which includes a data transfer interface and an SDO control interface.

[0082] The data transfer interface includes a first data transfer interface DAT0A to DAT3A and a second data transfer interface DAT0B to DAT3B. The first data transfer interface DAT0A to DAT3A is directly connected to the baseband interface U9D3 (such as Fig.13 As shown), the second data transfer interfaces DAT0B to DAT3B are respectively connected to the SD data interfaces of the SD card socket J2, and are used for transferring data transmission between the digital processing module 4 and the SD card socket J2.

[0083] Specifically, the second data transfer interfaces DAT0B to DAT3B are connected to the SD data interface of the SD card socket J2 through pull-up resistors R12, R13, R14, and R15, respectively, and are connected to the power supply end interface VCCB0 of the SDO expander chip U16.

[0084] The SDO control interface includes a first clock setting interface pin CLKA, a second clock setting interface pin CLKB0, a first command control interface pin CMDA, and a second command setting interface pin CMDB0.

[0085] The first clock setting interface CLKA and the first command setting interface CMDA are directly connected to the baseband interface U9D3 (such as Fig.13 As shown), the second clock setting interface CLKB0 and the second command setting interface CMDB0 are both directly connected to the SD card module J2.

[0086] Specifically, the second clock setting interface CLKB0 and the second command setting interface CMDB0 are connected to the clock setting interface pin CLK and the command setting interface pin CMD of the second parameter setting interface of the SD card module J2 through pull-up resistors R16 and R17 respectively.

[0087] The digital processing module 4 includes a processing chip U9, model XC7Z020-2CLG400I. The processing chip U9 includes multiple functional interfaces, which are respectively connected to different modules.

[0088] like Fig. 9As shown, the sampling interface U9G of the processing chip includes a data receiving interface and a parameter setting interface.

[0089] The data receiving interface includes a first data receiving interface and a second data receiving interface, which are used to receive the digital signal transmitted from the sampling module 5 .

[0090] The first data receiving interface refers to the data receiving interface pin IO_L7N_T1_34, pin IO_L10N_T1_34, pin IO_L8P_T1_34, pin IO_L8N_T1_34, pin IO_L4N_T0_34, pin IO_L3P_T0_DQS_PUDC_B_34, pin IO_L4P_T0_34, pin IO_L3N_T0_DQS_34, pin IO_L11P_T1_SRCC_34, pin IO_L10P_T1_34, pin IO_L11 N_T1_SRCC_34, pin

[0091] IO_L18P_T2_34 are respectively connected to the first data output interface pins D0_A to D11_A of the first analog-to-digital conversion chip U18 of the sampling module 5 for transmitting digital signals.

[0092] The second data receiving interface refers to the data receiving interface pin IO_L14N_T2_SRCC_34, pin IO_L13N_T2_MRCC_34, pin IO_0_34, pin IO_L15P_T2_DQS_34, pin IO_25_34, pin IO_L15N_T2_DQS_34, pin IO_L12N_T1_DMRCC_34, pin IO_L16P_T2_34, pin IO_L16N_T2_34, pin IO_L22N_T3_34, pin IO_L17N_T2_34, pin IO_L22P_T3_34, respectively sampling module 5 first data output interface pins D0_A ~ D11_A of the first analog-to-digital conversion chip U18, for transmitting digital signals.

[0093] The parameter setting interface includes a first clock setting interface IO_L2N_T0_34 and IO_L7N_T1_34, a second clock setting interface IO_L18N_T2_34 and

[0094] IO_L14P_T2_SRCC_34, the above four interfaces are respectively connected to the first clock input interface CLK_A and the second clock input interface CLK_B of the two analog-to-digital conversion chips of the sampling module 5.

[0095] like Fig.10As shown, the storage interface U9E of the processing chip U9 includes a data input interface, a parameter setting interface, an address output interface, a data selection interface and a data output interface.

[0096] The data input interface includes pins PS_DDR_DQ0_502 to PS_DDR_DQ31_502, which are respectively connected to data output interface pins DQ0 to DQ31 of two synchronous dynamic random access memory chips of the memory module 9.

[0097] The parameter setting interface includes a chip selection setting interface, a command setting interface, a differential clock setting interface, and a clock enable setting interface, and is used to connect to the controller through the digital processing module 4 to set the parameters of the two synchronous dynamic random access memory chips.

[0098] The chip selection setting interface includes a first chip selection setting interface PS_DDR_CS_B_502 connected to a chip selection input interface pin CS of the first synchronous dynamic random access memory chip U13 of the memory module 9 .

[0099] The command setting interface includes a first command setting interface PS_DDR_RAS_B_502, a second command setting interface PS_DDR_CAS_B_502, and a third command setting interface PS_DDR_WE_B_502, which are respectively connected to the first command input interface RAS, the second command input interface CAS, and the third command input interface WE of the first synchronous dynamic random access memory chip U13 of the storage module 9.

[0100] The differential clock setting interface includes a first differential clock setting interface PS_DDR_CKP_502 and a second differential clock setting interface PS_DDR_CKN_502, which are respectively connected to a first differential clock input interface CLK_P and a second differential clock input interface CLK_N of the first synchronous dynamic random access memory chip U13 of the memory module 9.

[0101] The clock enable setting interface includes a first clock enable setting interface PS_DDR_CKE_502 connected to the clock enable input interface CKE of the first synchronous dynamic random access memory chip U13 of the memory module 9 .

[0102] The address output interface includes a row and column address output interface and a BANK address output.

[0103] The row and column address output interfaces refer to row and column address output interfaces PS_DDR_A0-A14_502, which are respectively connected to the row and column address input interfaces A0-A14 of the first synchronous dynamic random access memory chip U13 of the memory module 9.

[0104] BANK address output interface includes BANK address output interface

[0105] PS_DDR_BA0-BA2_502 is connected to the BANK address input interfaces BA0-BA2 of the first synchronous dynamic random access memory chip U13 of the memory module 9.

[0106] The data strobe interface includes a first data strobe interface PS_DDR_DQS_P0-P3_502 connected to a first data strobe interface pin LDQS and a second data strobe interface pin UDQS of two synchronous dynamic random access memory chips of the memory module 9.

[0107] The second data strobe interface PS_DDR_DQS_N0-N3_502 is connected to the first data strobe interface pins LDQS and the second data strobe interface UDQS of two synchronous dynamic random access memory chips of the memory module 9.

[0108] The data output interface includes a first data output interface PS_DDR_DM0_502, a second data output interface PS_DDR_DM1_502, a third data output interface PS_DDR_DM2_502, and a fourth data output interface PS_DDR_DM3_502, which are respectively connected to a first data input interface LDM and a second data input interface UDM of two synchronous dynamic random access memory chips of the memory module 9.

[0109] like Fig.11 As shown, the processing chip U9 includes a flash memory interface U9D1 connected to the embedded flash memory module 8, a physical layer interface U9D2 connected to the Ethernet communication module 11, and a baseband interface U9D3 connected to the baseband connection module 101.

[0110] Among them, the flash memory interface U9D1 includes a data transmission interface and a parameter setting interface, which are used for data transmission with the embedded flash memory module 8.

[0111] The data transmission interface includes a first data transmission interface PS_M IO46_501, a second data transmission interface PS_M IO49_501, a third data transmission interface PS_M IO50_501, and a fourth data transmission interface PS_M IO51_501, which are respectively connected to the data transmission interfaces DAT0-DAT3 of the embedded flash memory module 8.

[0112] The parameter setting interface includes a first clock setting interface PS_M IO39_501, a first command setting interface PS_M IO47_501 and a first reset setting interface PS_M IO48_501, which are respectively connected to the clock input interface pin CLK, the command input interface pin CMD and the reset interface pin RST of the embedded flash memory module 8.

[0113] The physical layer interface U9D2 includes a signal input interface, a signal output interface, a data transmission interface and a parameter setting interface.

[0114] The signal input interface includes a first signal receiving interface PS_M IO20_501, a second signal receiving interface PS_M IO19_501, a third signal receiving interface PS_M IO18_501, and a fourth signal receiving interface PS_M IO17_501, which are respectively connected to data sending interfaces PS_PHY_TXD0~3 of the network transceiver chip U17 of the Ethernet communication module 11.

[0115] It includes a clock signal receiving interface PS_M IO16_501 connected to a data sending clock interface PS_PHY_TX_CLK of a network transceiver chip U17 of the Ethernet communication module 11 .

[0116] It also includes a signal receiving control interface PS_MIO21_501, which is connected to a data sending control interface PS_PHY_TX_CTRL of a network transceiver chip U17 of the Ethernet communication module 11.

[0117] The signal output interface includes a first signal output interface PS_MIO26_501, a second signal output interface PS_MIO25_501, a third signal output interface PS_MIO24_501, and a fourth signal output interface PS_MIO23_501, which are respectively connected to data receiving interface pins PS_PHY_RXD0-3 of the network transceiver chip U17 of the Ethernet communication module 11.

[0118] It includes a clock signal output interface PS_MIO22_501 connected to a data receiving clock interface PS_PHY_RX_CLK of a network transceiver chip U17 of the Ethernet communication module 11 .

[0119] It also includes a signal output control interface PS_MIO27_501, which is connected to a data receiving control interface PS_PHY_RX_CTRL of a network transceiver chip U17 of the Ethernet communication module 11.

[0120] The data transmission interface includes a data line interface PS_MIO53_501 connected to the data line interface MDIO of the Ethernet communication module 11, and a clock signal transmission interface, which includes a clock signal interface PS_M IO52_501 connected to the clock signal interface MDC of the network transceiver chip U17 of the Ethernet communication module 11.

[0121] The parameter setting interface includes a reset setting interface PS_MIO38_501, which is connected to a first reset interface PS_PHY_RESET of the network transceiver chip U17 of the Ethernet communication module 11.

[0122] The baseband interface U9D3 includes a data transmission interface and a parameter setting interface.

[0123] The data transmission interface includes a first data transmission interface

[0124] PS_MIO42_501~PS_MIO45_501, the above interfaces are respectively connected to the first data transmission interfaces DATOA~DAT3A of the SDO expander chip U16 of the baseband connection module 101 for data exchange.

[0125] The parameter setting interface includes a first clock setting interface pin PS_M IO40_501 and a first command control interface pin PS_MIO41_501, which are respectively connected to the first clock setting interface CLKA and the first command control interface CMDA of the SDO expander chip U16 of the baseband connection module 101.

[0126] In addition, the digital processing module 4 is also connected to a digital transmission module 13 for wirelessly transmitting digital signals. The digital transmission module 13 is directly connected to the 4G module 131 and transmits wirelessly through the 4G antenna 133. The digital signal can also be extracted through the identification card module 132 with storage function.

[0127] The above are only embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A detection baseband circuit, characterized in that: It includes a filtering module directly connected to an external RF signal receiving end, which is used to perform low-pass filtering on the received detection signal; the filtering module is directly connected to a sampling module, which is used to perform analog-to-digital conversion on the detection signal after the low-pass filtering, and convert it into a digital baseband signal; the sampling module is directly connected to a digital processing module, which is used to demodulate the digital baseband signal.

2. The detection baseband circuit according to claim 1, characterized in that: The filtering module includes two identical low-pass filtering chips, and the low-pass filtering chip includes a differential signal input interface, a differential signal output interface and a parameter control interface; The differential signal input interface includes a first differential signal input interface and a second differential signal input interface, which are respectively used to input the orthogonal I and Q signals of the detection signal; the differential signal output interface includes a first differential signal output interface and a second differential signal output interface, which are respectively used to output the filtered I signal and Q signal; The parameter control interface is used to connect to an external controller to set the parameters of the low-pass filter chip, including a chip selection input interface pin, a serial data input interface pin, a serial data output interface pin, and a serial clock input interface pin.

3. The detection baseband circuit according to claim 2, characterized in that: The sampling module has two identical analog-to-digital conversion chips, and the analog-to-digital conversion chip includes an analog differential input interface, a clock input interface, a data output interface, and an output enable interface; The analog differential input interface includes a first analog differential input interface and a second analog differential input interface, which are respectively connected to the first differential signal output interface and the second differential signal output interface of the low-pass filter chip, and are used to input the filtered I-path signal and Q-path signal; The clock input interface includes a first clock input interface pin and a second clock input interface pin, which are used to input a sampling clock signal of the analog-to-digital conversion chip during use; The data output interface includes a first data output interface and a second data output interface, which are used to output the digital signal after analog-to-digital conversion; The output enable interface includes a first output enable interface and a second output enable interface, which are respectively used to enable and select data output of the first data output interface and data output of the second data output interface.

4. The detection baseband circuit according to claim 1, characterized in that: The digital processing module is electrically connected to the first memory, the second memory and the third memory; Among them, the first memory includes a FLASH memory for storing the result data processed by the digital processing module; the second memory includes an EMMC memory for storing the program of the digital processing module itself; the third memory includes a DDR memory for temporarily storing the intermediate data of the digital processing module during the processing process.

5. The detection baseband circuit according to claim 4, characterized in that: The third memory includes a synchronous dynamic random access memory chip, which includes a DDR address interface, a DDR parameter setting interface, a DDR data output interface, a DDR data input interface and a DDR data selection interface, which are electrically connected to the digital processing module respectively.

6. The detection baseband circuit according to claim 4, characterized in that: The second memory includes an EMMC industrial-grade embedded flash memory chip, and the EMMC industrial-grade embedded flash memory chip includes an EMMC data transmission interface and an EMMC parameter setting interface, which are electrically connected to the digital processing module respectively.

7. The detection baseband circuit according to claim 1, characterized in that: The digital processing module is electrically connected to the Ethernet communication module, and the Ethernet communication module includes a network transceiver chip. The network transceiver chip includes a network data sending interface, a network data receiving interface, a serial data bus interface and a network parameter setting interface, which are electrically connected to the digital processing module respectively.

8. The detection baseband circuit according to claim 7, characterized in that: The network data transmission interface includes a data transmission interface pin, a data transmission clock interface pin, and a data transmission control interface pin, which are used for the network transceiver chip to send data to the digital processing module; The network data receiving interface includes a data receiving interface pin, a data receiving clock interface pin, and a data receiving control interface pin, which are used for the network transceiver chip to receive data from the digital processing module; The serial data bus interface includes a data transmission interface pin and a clock signal transmission interface pin, which are used for serial port data transmission between the network transceiver chip and the digital processing module; The network parameter setting interface includes a clock frequency setting interface and a reset interface, which are used to set the parameters of the network transceiver chip.

9. The detection baseband circuit according to claim 1, characterized in that: The digital processing module is electrically connected to a mobile storage module, the mobile storage module includes an SD card socket and an SDO expander chip, the SD card socket includes an SD data interface and an SD control interface, the SDO expander chip includes a data transfer interface and an SDO control interface; the data transfer interface is used for transferring data transmission between the digital processing module and the SD card socket.

10. The detection baseband circuit according to claim 1, characterized in that: The digital processing module is electrically connected to the digital transmission module, the digital transmission module is connected to the 4G module, and the 4G module is connected to the 4G antenna for wirelessly transmitting detection data.

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