Testing device and testing box for memory chip
The memory chip testing device addresses inefficiencies in single-chip testing by employing a control chip with increased bit width to test multiple chips simultaneously, enhancing efficiency and reducing costs.
Patent Information
- Application Number
- CN202420302604.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-19
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2034-02-19
AI Technical Summary
Existing memory chip test devices have low test efficiency and high cost due to the inability to test multiple chips simultaneously, as they are designed for single-chip testing and require multiple devices for increased capacity, leading to inefficiency and elevated costs.
A memory chip testing device with a control chip having a bit width greater than or equal to the combined bit width of multiple memory chips, allowing simultaneous testing of multiple chips through a test socket with appropriately matched interfaces, and optionally including a power module and configuration module for enhanced functionality.
The solution enables efficient testing of multiple memory chips, improving test efficiency and reducing costs by eliminating the need for additional devices, thus optimizing resource utilization.
Smart Images
Figure CN222190285U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip testing technology, and in particular to a memory chip testing device and a testing box. Background Art
[0002] During the packaging and testing process of memory chips, system level testing (STL) is required to test whether the functions between various modules of the memory chip are normal by executing system software programs on the memory chip.
[0003] At present, when a memory chip is tested at the system level, it needs to be placed on a test device, and the test device tests one memory chip corresponding to a system-level chip (SOC). This test device can only test a single memory chip at a time, and has the disadvantage of low test efficiency. Utility Model Content
[0004] The present application provides a memory chip testing device and a testing box.
[0005] A technical solution adopted in the present application is to provide a memory chip testing device, the testing device comprising:
[0006] A test socket configured to support placement of multiple memory chips to be tested;
[0007] The control chip is connected to the test socket and is configured to test at least one memory chip to be tested placed on the test socket, wherein the control chip is used to test that the bit width of the memory chip to be tested is greater than or equal to the bit width of at least one memory chip to be tested.
[0008] Optionally, the test socket includes multiple test interfaces, the first end of each test interface is coupled to the control chip, the second end of each test interface is configured to couple to a memory chip to be tested, and the total bit width of the multiple test interfaces is less than or equal to the bit width of the control chip.
[0009] Optionally, each test interface has a different bit width.
[0010] Optionally, each test interface has the same bit width.
[0011] Optionally, some of the multiple test interfaces have the same bit width.
[0012] Optionally, a minimum bit width among the multiple test interfaces is 16 bits.
[0013] Optionally, the testing device further comprises a power module, which is electrically connected to the test socket and the control chip respectively, and is used to supply power to the test socket and the control chip.
[0014] Optionally, the test device further includes a configuration module, which is connected to the control chip and is used to provide a test running environment for the control chip.
[0015] Optionally, the bit width of the control chip is any one of 32 bits, 64 bits or 128 bits.
[0016] Another technical solution adopted by the present application is to provide a test box for a memory chip, the test box comprising:
[0017] at least one testing device, wherein the testing device is a testing device as described above;
[0018] The housing is used to accommodate the testing device.
[0019] The beneficial effect of the present application is that, compared with conventional technical solutions, by increasing the bit width of the control chip so that the bit width of the control chip is greater than or equal to the bit width of at least one memory chip to be tested, the control chip can test multiple memory chips to be tested placed on a test socket, thereby improving test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0021] Figure 1 It is a schematic diagram of the structure of a common memory chip testing device;
[0022] Figure 2 It is a structural schematic diagram of an embodiment of a memory chip testing device provided by the present application;
[0023] Figure 3 is a structural schematic diagram of another embodiment of the memory chip testing device provided by the present application;
[0024] Figure 4 It is a structural schematic diagram of an embodiment of a memory chip testing device provided by the present application;
[0025] Figure 5 It is a structural schematic diagram of an embodiment of a memory chip test box provided by the present application. DETAILED DESCRIPTION
[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0027] At present, the test device of memory chip in SLT (system level test) system mainly adopts dual-channel DDR physical layer (DDR PHY) system-level chip (SOC) for testing. Common memory chip test devices include Figure 1 As shown, the memory chip to be tested is placed on the test socket, the test socket is connected to the control chip, the power system is electrically connected to the test socket and the control chip respectively, and is used to supply power to the test socket and the control chip; the peripheral configuration system is connected to the control chip, and is used to provide the necessary operating environment for the control chip. Since the bit width of the control chip is equal to the bit width of a single memory chip to be tested, the memory chip test device achieves full-function testing of the memory chip to be tested by one control chip (i.e., SOC) corresponding to one memory chip to be tested.
[0028] The inventor of the present application has found that, since a single memory chip test device only supports testing a single memory chip, common memory chip test devices have the disadvantage of low test efficiency. The inventor of the present application has considered that common memory chip test devices are expensive, and using several memory chip test devices to test the same number of memory chips at the same time increases the test cost to a certain extent.
[0029] See also Figure 2 , Figure 2 It is a structural schematic diagram of an embodiment of a memory chip testing device provided by the present application.
[0030] like Figure 2 As shown, the memory chip testing device 10 provided in the present application includes a test socket 11 and a control chip 12 .
[0031] The test socket 11 is configured to support placement of a plurality of memory chips 2 to be tested.
[0032] The control chip 12 is connected to the test socket 11. The control chip 12 is configured to test at least one memory chip 2 to be tested placed on the test socket 11. The control chip is used to test whether the bit width of the memory chip to be tested is greater than or equal to the bit width of at least one memory chip to be tested.
[0033] In some possible embodiments, the bit width of the control chip used to test the memory chip to be tested is greater than or equal to the bit width of one memory chip to be tested.
[0034] In some possible embodiments, the bit width of the control chip used to test the memory chip to be tested is greater than or equal to the bit width of at least two memory chips to be tested.
[0035] In some possible embodiments, the bit width of the control chip 12 is 64 bits, and two to four 16-bit memory chips 2 to be tested placed in the test socket 11 can be tested, and two 32-bit memory chips 2 to be tested can also be tested.
[0036] In some possible embodiments, the bit width of the control chip 12 is 128 bits, and 2 to 8 16-bit memory chips 2 to be tested placed in the test socket 11 can be tested, and 2 to 4 32-bit memory chips 2 to be tested can also be tested.
[0037] In some embodiments, the control chip 12 may be a system-on-chip (SOC). In some possible application scenarios, the control chip 12 may be a DDR PHY SOC.
[0038] In some possible embodiments, the sum of the bit widths of the multiple memory chips 2 to be tested is less than or equal to the total bit width provided by the test socket.
[0039] In some embodiments, the memory chip 2 to be tested is a memory chip with a BGA (ball grid array) packaging structure.
[0040] Optionally, the memory chip 2 to be tested is an LPDDR memory chip. Exemplarily, the memory chip 2 to be tested is any one of LPDDR4, LPDDR4X, LPDDR5, and LPDDR5X, which is not limited here.
[0041] In some possible embodiments, the memory chip 2 to be tested is a LPDDR5 chip, and the package type of the memory chip 2 to be tested can be 315, 297, or 496, etc., which is not limited here.
[0042] Optionally, the memory chip 2 to be tested may be a single-channel memory chip, a dual-channel memory chip, or a quad-channel memory chip, which is not limited here.
[0043] In some possible embodiments, the bit width of the memory chip to be tested is smaller than or equal to the bit width of the control chip.
[0044] Optionally, the test socket 11 also includes multiple test interfaces (not shown), the first end of each test interface is coupled to the control chip 12, and the second end of each test interface is configured to couple a memory chip 2 to be tested, and the total bit width of the multiple test interfaces is less than or equal to the bit width of the control chip 12.
[0045] In some possible embodiments, the sum of the bit widths of the multiple memory chips 2 to be tested is less than or equal to the total bit width of the multiple test interfaces.
[0046] In some possible embodiments, each test interface has a different bit width. Exemplarily, the bit width of the test interface is any combination of 32 bits, 64 bits, 96 bits, 128 bits, 192 bits, 256 bits, and 384 bits.
[0047] In some possible embodiments, each test interface has the same bandwidth. Exemplarily, the bit width of the test interface is any one of 16 bits, 32 bits, 64 bits, 96 bits, 128 bits, 192 bits, 256 bits or 384 bits, which is not limited here.
[0048] In some possible embodiments, some of the multiple test interfaces have the same bit width. For example, a test socket 11 has 3 test interfaces, 2 of which have a bit width of 32 bits, and the remaining 1 has a bit width of 64 bits.
[0049] In some embodiments, the minimum bit width of the multiple test interfaces in the test socket 11 is 16 bits.
[0050] It can be understood that the bit width of the test interface is greater than or equal to the bit width of the memory chip 2 to be tested, so that the memory chip 2 to be tested can perform a memory test.
[0051] Optionally, the test device 10 further includes a power module 13, which is electrically connected to the test socket 11 and the control chip 12, respectively, and is used to supply power to the test socket 11 and the control chip 12. It can be understood that the power module 13 also supplies power to the memory chip 2 to be tested placed on the test socket 11.
[0052] Optionally, the test device 10 further includes a configuration module 14 , which is connected to the control chip 12 , and is used to provide a test running environment for the control chip 12 .
[0053] In some embodiments, the bit width of the control chip 12 is any one of 32 bits, 64 bits or 128 bits. In some possible application scenarios, the bit width of the control chip 12 can also be greater than 128 bits. Exemplarily, the bit width of the control chip is 192 bits or 256 bits, etc., which is not limited here.
[0054] The above scheme increases the bit width of the control chip so that the bit width of the control chip is greater than or equal to the bit width of at least one memory chip to be tested, so that the control chip can test multiple memory chips to be tested placed on the test socket, thereby improving the test efficiency.
[0055] See also Figure 3 , Figure 3 It is a structural schematic diagram of another embodiment of the memory chip testing device provided by the present application.
[0056] like Figure 3 As shown, the test device 20 of the embodiment of the present application includes a test socket 21, a control chip 22, a power system 23 and a peripheral configuration system 24.
[0057] In some embodiments, the test seat 21 is also called a socket.
[0058] The control chip 22 is a DDR PHY system chip (DDR PHY SOC) with a bit width of 64 bits.
[0059] Among them, the test socket 21 is connected to the control chip 22, and the test socket 21 can simultaneously place two dual-channel LPDDR5 memory chips to be tested, and the bit width of each memory chip to be tested is 32 bits.
[0060] That is to say, the control chip 22 can test two 32-bit dual-channel LPDDR5 memory chips to be tested at the same time.
[0061] Specifically, the test device 20 further includes a power supply system 23, which is electrically connected to the test socket 21 and the control chip 22, and is used to supply power to the test socket 21 and the control chip 22. It can be understood that the power supply system 23 also supplies power to the memory chip to be tested placed on the test socket 21.
[0062] Furthermore, the testing device 20 also includes a peripheral configuration system 24 , which is connected to the control chip 22 , and is used to provide a test running environment for the control chip 22 .
[0063] Exemplarily, two 32-bit dual-channel LPDDR5 memory chips A and B to be tested are placed on the test socket 21. The test device 20 is powered on to start the test, so that the memory chips A and B to be tested are tested at the same time. When one or more of them are tested, they can be taken out, and the other memory chips to be tested are placed on the test socket 21 to test the memory chips to be tested.
[0064] The above scheme increases the bit width of the control chip so that the bit width of the control chip is greater than or equal to the bit width of at least one memory chip to be tested, so that the control chip can test multiple memory chips to be tested placed on the test socket, thereby improving the test efficiency.
[0065] Furthermore, the memory chip testing device provided in the present application can test multiple memory chips to be tested, thereby improving the testing efficiency of the memory chip without adding expensive memory chip testing devices, thereby reducing the testing cost to a certain extent.
[0066] See also Figure 4 , Figure 4It is a structural schematic diagram of another embodiment of the memory chip testing device provided by the present application.
[0067] like Figure 4 As shown, the test device 30 of the embodiment of the present application includes a test socket 31 , a control chip 32 , a power system 33 and a peripheral configuration system 34 .
[0068] The control chip 32 is a DDR PHY system chip with a bit width of 64 bits.
[0069] Among them, the test socket 31 is connected to the control chip 32, and the test socket 31 can simultaneously place 4 dual-channel LPDDR5 memory chips to be tested, and the bit width of each memory chip to be tested is 32 bits.
[0070] In some possible application scenarios, the bit width of each memory chip to be tested is 16 bits. In some possible application scenarios, the bit width of each memory chip to be tested is greater than 32 bits, which is not limited here.
[0071] That is to say, the control chip 32 can test four 32-bit dual-channel LPDDR5 memory chips to be tested at the same time.
[0072] Specifically, the test device 30 further includes a power supply system 33, which is electrically connected to the test socket 31 and the control chip 32, and is used to supply power to the test socket 31 and the control chip 32. It can be understood that the power supply system 33 also supplies power to the memory chip to be tested placed on the test socket 31.
[0073] Furthermore, the testing device 30 also includes a peripheral configuration system 34 , which is connected to the control chip 32 , and is used to provide a test running environment for the control chip 32 .
[0074] Exemplarily, four 32-bit dual-channel LPDDR5 memory chips C, D, E, and F to be tested are placed on the test socket 31. The test device 30 is powered on to start the test, so that the memory chips C, D, E, and F to be tested are tested at the same time. When one or more of them are tested, they can be taken out, and other memory chips to be tested are placed on the test socket 31 to test the memory chips to be tested.
[0075] The above scheme increases the bit width of the control chip so that the bit width of the control chip is greater than or equal to the bit width of at least one memory chip to be tested, so that the control chip can test multiple memory chips to be tested placed on the test socket, thereby improving the test efficiency.
[0076] Furthermore, the memory chip testing device provided in the present application can test multiple memory chips to be tested, thereby improving the testing efficiency of the memory chip without adding expensive memory chip testing devices, thereby reducing the testing cost to a certain extent.
[0077] See also Figure 5 , Figure 5 It is a structural schematic diagram of an embodiment of a memory chip test box provided in the present application.
[0078] like Figure 5 As shown, the test box 40 provided in the present application includes at least one test device 41, wherein the test device 41 is the test device described above.
[0079] The test box 40 further includes a housing 42 for accommodating the test device 41 .
[0080] The above scheme increases the bit width of the control chip so that the bit width of the control chip is greater than or equal to the bit width of at least one memory chip to be tested, so that the control chip can test multiple memory chips to be tested placed on the test socket, thereby improving the test efficiency.
[0081] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Equivalent structures or equivalent process changes made by utilizing the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A memory chip testing device, characterized in that: The testing device comprises: A test socket configured to support placement of multiple memory chips to be tested; A control chip is connected to the test socket and is configured to test at least one of the memory chips to be tested placed on the test socket, wherein the control chip is used to test that the bit width of the memory chip to be tested is greater than or equal to the bit width of at least one memory chip to be tested.
2. The testing device according to claim 1, characterized in that: The test socket includes multiple test interfaces, a first end of each test interface is coupled to the control chip, a second end of each test interface is configured to couple a memory chip to be tested, and a total bit width of the multiple test interfaces is less than or equal to the bit width of the control chip.
3. The testing device according to claim 2, characterized in that: Each of the test interfaces has a different bit width.
4. The testing device according to claim 2, characterized in that: Each of the test interfaces has the same bit width.
5. The testing device according to claim 2, characterized in that: Some of the multiple test interfaces have the same bit width.
6. The testing device according to any one of claims 3 to 5, characterized in that: The minimum bit width of the multiple test interfaces is 16 bits.
7. The testing device according to claim 1, characterized in that: The testing device further comprises a power supply module, which is electrically connected to the testing socket and the control chip respectively, and is used to supply power to the testing socket and the control chip.
8. The testing device according to claim 1, characterized in that: The test device further comprises a configuration module, which is connected to the control chip and is used to provide a test running environment for the control chip.
9. The testing device according to claim 2, characterized in that: The bit width of the control chip is any one of 32 bits, 64 bits or 128 bits.
10. A memory chip test box, characterized in that: The test kit comprises: At least one testing device, wherein the testing device is a testing device as claimed in any one of claims 1 to 9; The housing is used to accommodate the testing device.
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