Stacked crystal supporting structure
The stacked wafer support structure addresses the issue of chip tilting and flatness by using copper pillars and a substrate design with insulating and metal layers to improve chip integration reliability and bonding efficiency.
Patent Information
- Application Number
- CN202421091766.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-20
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2034-05-20
AI Technical Summary
Stacking chips of the same size causes the upper chip to be partially suspended, leading to tilting and deteriorated flatness, making bonding difficult in chip integration.
A stacked wafer support structure with staggered chips connected via copper pillars to a substrate, supported by copper pillars for improved flatness and facilitated wire bonding, featuring a substrate with insulating and metal layers, green oil layers for protection, and vias for inter-layer connections.
Enhances chip flatness and reliability, allowing multiple window exposures for easier inter-layer connections, thus simplifying and securing the bonding process.
Smart Images

Figure CN222281977U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a semiconductor device, in particular to a stacked crystal support structure. Background Art
[0002] As modern chips have more and more functions, the size of a single chip is also increasing. As a result, the process technology is becoming more and more complex, resulting in high manufacturing costs and design costs. In order to deal with this problem, a modular design method is used to separate functional blocks into small modules, making them into high-yield, low-cost core particles, and then flexibly assemble them according to needs.
[0003] Currently, stacking chips on chips is one of the assembly methods. By stacking chips and then bonding circuits on different layers of chips and substrates, multiple chips can be integrated without occupying plane space. However, stacking chips of the same size to reserve window positions will cause the upper chip to be partially suspended, which will cause the chip to tilt and the flatness to deteriorate, making bonding difficult. Summary of the invention
[0004] In view of the above problems, the utility model provides a stacked wafer support structure which has a simple structure, is convenient for processing and has improved reliability.
[0005] The technical solution of the utility model is: a stacked crystal support structure, including a substrate, a chipset is arranged on the top of the substrate; the chipset includes a plurality of stacked chips, and the plurality of chips are staggered and connected in sequence, wherein, starting from the bottom to the top, the suspended parts of the second chip to the last chip are connected to the substrate respectively through copper columns.
[0006] The substrate comprises an insulating plate, a top metal layer is disposed on the top of the insulating plate, and a bottom metal layer is disposed on the bottom of the insulating plate.
[0007] The invention also comprises a top green oil layer and a bottom green oil layer, wherein the top green oil layer is used to cover the top metal layer, and the bottom green oil layer is used to cover the bottom metal layer.
[0008] The top metal layer is connected to the first chip through a metal wire.
[0009] The top metal layer, the insulating plate and the bottom metal layer are provided with corresponding vias,
[0010] A solder ball is provided at the bottom of the substrate, and the solder ball is connected to the bottom metal layer.
[0011] A chip surface metal layer is provided on the chip surface.
[0012] A plastic package is provided on the top of the substrate, and the plastic package is used to wrap the chipset.
[0013] In the operation of the utility model, by pre-installing copper pillars on the substrate, the suspended part of the upper chip can be supported by the copper pillars, which improves the flatness of the chip and facilitates wire bonding. At the same time, the support allows the chip to have a larger suspended area, so that multiple rows of windows can be exposed, which is more convenient and reliable for inter-layer connection. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 It is a schematic diagram of the overall structure of the utility model;
[0015] Figure 2 It is a schematic diagram of the back side of the utility model as a whole;
[0016] Figure 3 This is a schematic diagram of the internal structure of the utility model;
[0017] Figure 4 It is a schematic diagram of the internal details of the utility model;
[0018] Figure 5 This is a schematic diagram of the substrate structure of the utility model;
[0019] Figure 6 This is a schematic diagram of the top green oil layer of the utility model;
[0020] Figure 7 This is a schematic diagram of the top metal layer of the utility model;
[0021] Figure 8 This is a schematic diagram of the top insulation board of the utility model;
[0022] Fig. 9 This is a schematic diagram of the bottom metal layer of the utility model;
[0023] Fig.10 This is a schematic diagram of the bottom green oil layer of the utility model;
[0024] In the figure: 1, substrate; 101, insulating board; 102, top metal layer; 103, top green oil layer; 104, bottom metal layer; 105, bottom green oil layer; 106, via;
[0025] 2. Plastic package; 3. Solder ball;
[0026] 4. Chip; 401. Metal layer on the chip surface;
[0027] 5. Metal wire; 6. Copper pillar. DETAILED DESCRIPTION
[0028] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0029] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0030] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0031] The present invention Figure 1-10 As shown, the stacked crystal support structure includes a substrate, and a chipset is provided on the top of the substrate 1; the chipset includes a plurality of stacked chips, and the plurality of chips (along the same direction) are staggered and connected in sequence, wherein, starting from the bottom to the top, the suspended parts of the second chip to the last chip are connected to the substrate through copper pillars 6 respectively.
[0032] A chip 4 is mounted on the substrate 1, and chips are stacked on the chip 4 in an offset manner. The suspended part of the chip relies on copper pillars 6 to support metal wires 5 to connect different layers of chips and the substrate. The structure above the substrate is wrapped and protected by a plastic package 2.
[0033] The substrate 1 includes an insulating plate 101, a top metal layer 102, a top green oil layer 103, a bottom metal layer 104, and a bottom green oil layer 105. The insulating plate 101 provides support to ensure the overall strength of the substrate 1, and isolates the top metal layer 102 and the bottom metal layer 104. The top metal layer and the bottom metal layer are used for arranging circuits and connecting to the outside. The top green oil layer 103 and the bottom green oil layer 105 are used to cover the top metal layer and the bottom metal layer respectively for protection, and at the same time insulate and isolate from the outside. A window is opened in the green oil layer where an external connection is required to expose the metal layer for external connection. In order to prevent oxidation, a nickel-palladium-gold protective layer is chemically plated on the surface of the exposed part of the metal layer. The top metal layer and the bottom metal layer can be set to corresponding shapes according to the requirements of use.
[0034] The top metal layer is connected to the first chip through a metal wire.
[0035] The top metal layer, the insulating plate and the bottom metal layer are provided with corresponding vias,
[0036] The bottom of the substrate is provided with solder balls, which are connected to the bottom metal layer. In application, the bottom has solder balls 3 for connecting with external circuits.
[0037] The via hole 106 is formed by hole metallization electroplating and is used for interconnecting the top metal layer and the bottom metal layer at the designated position. The surface is also completely covered with green oil.
[0038] The surface of the chip 4 has a chip surface metal layer 401 for providing a window for connecting to the outside by using a metal wire 5 .
[0039] Regarding the contents disclosed in this case, there are a few points that need to be explained:
[0040] (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design;
[0041] (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments;
[0042] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.
Claims
1. A stacked crystal support structure, comprising a substrate, characterized in that: A chipset is arranged on the top of the substrate; the chipset comprises a plurality of stacked chips, which are staggered and connected in sequence, wherein, starting from the bottom to the top, the suspended parts of the second chip to the last chip are connected to the substrate via copper pillars respectively.
2. The stacked crystal support structure according to claim 1, characterized in that: The substrate comprises an insulating plate, a top metal layer is disposed on the top of the insulating plate, and a bottom metal layer is disposed on the bottom of the insulating plate. The invention also comprises a top green oil layer and a bottom green oil layer, wherein the top green oil layer is used to cover the top metal layer, and the bottom green oil layer is used to cover the bottom metal layer.
3. The stacked crystal support structure according to claim 2, characterized in that: The top metal layer is connected to the first chip through a metal wire.
4. The stacked crystal support structure according to claim 3, characterized in that: The top metal layer, the insulating plate and the bottom metal layer are provided with corresponding vias, A solder ball is provided at the bottom of the substrate, and the solder ball is connected to the bottom metal layer.
5. The stacked crystal support structure according to any one of claims 1 to 4, characterized in that: The chip surface is provided with a chip surface metal layer.
6. The stacked crystal support structure according to claim 1, characterized in that: A plastic package is provided on the top of the substrate, and the plastic package is used to wrap the chipset.