Array substrate and display panel

Abstract

The utility model discloses an array substrate and a display panel, the array substrate comprises a substrate and a thin film transistor, the thin film transistor is arranged on one surface of the substrate, the thin film transistor comprises a semiconductor layer, a crystallized inorganic layer and a gate insulation layer, the semiconductor layer is arranged on one surface of the substrate, and the crystallized inorganic layer is arranged on the other surface of the substrate. The crystallized inorganic layer is disposed on a surface of the semiconductor layer away from the substrate. The gate insulating layer is disposed on a surface of the crystallized inorganic layer away from the substrate. The stability of the TFT device can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] Mini LED (Mini Light Emitting Diode, sub-millimeter light-emitting diode) display panels and Micro LED (Micro Light Emitting Diode, micro light-emitting diode) display panels have entered an accelerated development stage in recent years and can be used in small and medium-sized, high value-added display applications. Compared with OLED (Organic Light Emitting Diode, organic light-emitting diode) display panels, Mini LED display panels and Micro LED display panels have superior performance in terms of cost, contrast, high brightness and thin and light appearance.

[0003] However, in actual products, the gate insulating layer covering the semiconductor layer has poor film density and many defects on the film surface of the gate insulating layer, resulting in reduced device stability of the thin film transistor.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Utility Model Content

[0005] The purpose of the present application is to provide an array substrate and a display panel to improve the stability of a thin film transistor device.

[0006] To solve the above problems, the technical solution of this application is as follows:

[0007] The present application proposes an array substrate, comprising:

[0008] substrate; and

[0009] A thin film transistor is disposed on a surface of the substrate, wherein the thin film transistor comprises a semiconductor layer, a crystallized inorganic layer and a gate insulating layer;

[0010] The semiconductor layer is disposed on a surface of the substrate, the crystallized inorganic layer is disposed on a surface of the semiconductor layer away from the substrate, and the gate insulating layer is disposed on a surface of the crystallized inorganic layer away from the substrate.

[0011] In one embodiment of the present application, the semiconductor layer includes:

[0012] A channel portion is provided on a surface of the substrate;

[0013] A transition portion is provided on a surface of the substrate and is located at the periphery of the channel portion, wherein the carrier concentration of the transition portion is greater than the carrier concentration of the channel portion;

[0014] A lap portion, disposed on a surface of the substrate and located on a side of the transition portion away from the channel portion, wherein the carrier concentration of the lap portion is greater than the carrier concentration of the transition portion;

[0015] The transition portion connects the channel portion and the overlapping portion, and the crystallized inorganic layer covers a surface of the channel portion away from the substrate and a surface of the transition portion away from the substrate.

[0016] In one embodiment of the present application, the transition portion includes:

[0017] A first sub-portion, located at the periphery of the channel portion;

[0018] A second sub-portion is located at a side of the first sub-portion away from the channel portion, the carrier concentration of the second sub-portion is greater than the carrier concentration of the first sub-portion, and the carrier concentration of the second sub-portion is less than the carrier concentration of the overlapping portion;

[0019] Wherein, the first sub-portion connects the channel portion and the second sub-portion, and the second sub-portion connects the first sub-portion and the overlapping portion;

[0020] The orthographic projection of the gate insulating layer on the substrate overlaps with the first sub-portion;

[0021] An orthographic projection of an edge of the second sub-portion on the substrate is located on an outer peripheral side of an orthographic projection of an edge of the gate insulating layer on the substrate.

[0022] In one embodiment of the present application, a distance from a side of the transition portion away from the channel portion to a side of the transition portion close to the channel portion is in a range of 1 micrometer to 1.5 micrometers;

[0023] A distance from a side of the first sub-portion away from the channel portion to a side of the first sub-portion close to the channel portion is in a range of 0.5 micrometers to 1 micrometer.

[0024] In an embodiment of the present application, a distance from a side of the second sub-portion away from the channel portion to a side of the second sub-portion close to the channel portion is in a range of 0.5 micrometers to 1 micrometer.

[0025] In one embodiment of the present application, the distance from the side of the second sub-portion away from the channel portion to the side of the second sub-portion close to the channel portion is greater than the distance from the side of the first sub-portion away from the channel portion to the side of the first sub-portion close to the channel portion.

[0026] In one embodiment of the present application, the thickness of the crystallized inorganic layer is less than the thickness of the semiconductor layer;

[0027] The thickness of the crystallized inorganic layer is smaller than the thickness of the gate insulating layer.

[0028] In one embodiment of the present application, the thickness of the crystallized inorganic layer is in a range of 5 nanometers to 10 nanometers.

[0029] In one embodiment of the present application, the thin film transistor further includes:

[0030] A gate is disposed on a surface of the gate insulating layer away from the substrate;

[0031] an interlayer dielectric layer, disposed on a surface of the substrate and covering the semiconductor layer, the crystallized inorganic layer, the gate insulating layer and the gate;

[0032] A source electrode is disposed on a surface of the interlayer dielectric layer away from the substrate and is electrically connected to the semiconductor layer; and

[0033] A drain electrode is disposed on a surface of the interlayer dielectric layer away from the substrate and is electrically connected to the semiconductor layer;

[0034] The array substrate further comprises a passivation layer and a pixel electrode, wherein the passivation layer is disposed on a surface of the interlayer dielectric layer away from the substrate and covers the source electrode and the drain electrode; and

[0035] A pixel electrode, disposed on a surface of the passivation layer away from the substrate and electrically connected to the drain electrode;

[0036] The substrate comprises:

[0037] substrate;

[0038] a light shielding layer disposed on a surface of the substrate; and

[0039] A buffer layer, disposed on a surface of the substrate and covering the light shielding layer;

[0040] The thin film transistor is arranged on a surface of the buffer layer away from the substrate, and the light shielding layer is electrically connected to the source electrode.

[0041] The present application proposes a display panel, including an array substrate, wherein the array substrate includes a substrate and a thin film transistor, the thin film transistor is arranged on a surface of the substrate, and the thin film transistor includes a semiconductor layer, a crystallized inorganic layer and a gate insulating layer; the semiconductor layer is arranged on a surface of the substrate, the crystallized inorganic layer is arranged on a surface of the semiconductor layer away from the substrate, and the gate insulating layer is arranged on a surface of the crystallized inorganic layer away from the substrate.

[0042] In the present application, a crystallized inorganic layer is disposed on a surface of the semiconductor layer away from the substrate. Compared with the conventional gate insulating layer, the surface density of the crystallized inorganic layer is better and the surface defects of the film layer are less. The provision of the crystallized inorganic layer can better protect the front channel of the thin film transistor, thereby improving the gate control performance and stability of the thin film transistor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a schematic diagram of a conventional array substrate;

[0044] Figure 2 is a schematic diagram of an array substrate provided in an embodiment of the present application;

[0045] Figure 3 It is a top view of the array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The meanings of the terms used in this specification and claims correspond to the meanings commonly understood by those of ordinary skill in the art to which this application belongs. The terms used in this specification and claims are only for the purpose of facilitating the description and understanding of this application, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.

[0047] See also Figure 1 The conventional display panel 100a includes a substrate 10a and a thin film transistor 20a, wherein the thin film transistor 20a of the conventional display panel 100a includes a semiconductor layer 21a, a gate insulating layer 23a, and a gate 24a. On the one hand, since the side of the semiconductor layer 21a away from the substrate 10a is not provided with a crystallized inorganic layer, the gate insulating layer 23a is in direct contact with the side of the semiconductor layer 21a away from the substrate 10a. However, the density of the film surface of the gate insulating layer 23a is poor, and there are many defects on the film surface of the gate insulating layer 23a. The gate insulating layer 23a has a poor protection effect on the front channel of the thin film transistor 20a, which will lead to a decrease in the gate control performance and stability of the thin film transistor 20a device.

[0048] On the other hand, in the conventional display panel 100a, the side of the semiconductor layer 21a away from the substrate 10a is not provided with a crystallized inorganic layer, so that the gate insulating layer 23a is in direct contact with the semiconductor layer 21a. In the process of high-temperature oxidation or high-temperature nitridation, the semiconductor layer 21a is affected by the diffusion of hydrogen in the gate insulating layer 23a and the bombardment of particles during the conductorization process of the semiconductor layer 21a, resulting in a greater influence of the relative content of hydrogen and oxygen in the gate insulating layer 23a on the thin film transistor 20a device. Simply relying on the regulation of hydrogen and oxygen in the gate insulating layer 23a is likely to result in a smaller process window.

[0049] The semiconductor layer 21a of the conventional thin film transistor 20a includes a channel portion 211a, a transition portion 212a and a lap portion 213a connected in sequence, wherein the upper surfaces of the channel portion 211a and the transition portion 212a are covered with a gate insulating layer 23a, and the upper surface of the lap portion 213a is not covered with the gate insulating layer 23a. In the thermal process of the display panel, since the particle concentration in the lap portion 213a is the highest after the conductor treatment, at high temperature, the high concentration of metal oxide with oxygen vacancies in the lap portion 213a diffuses to the transition portion 212a. Since the length of the transition portion 212a is constant, when the thermal process time is too long or the diffusion speed of the high concentration of metal oxide with oxygen vacancies is fast, the high concentration of metal oxide with oxygen vacancies will further diffuse to the edge of the channel portion 211a, resulting in a shortened effective channel length of the semiconductor layer 21a, affecting the gate control performance of the thin film transistor 20 device. It should be noted that the carrier concentration of the transition portion 212 a is greater than the carrier concentration of the channel portion 211 a .

[0050] The present application proposes a display panel, which may be an organic light emitting diode display panel (OLED), a micro light emitting diode display panel (Micro LED), a sub-millimeter light emitting diode display panel (Mini LED), or a liquid crystal panel. The display panel of the present application is described by taking a micro light emitting diode display panel as an example, but is not limited thereto. The display panel includes an array substrate 100.

[0051] See also Figure 2, the present application proposes an array substrate 100. The array substrate 100 includes a substrate 10 and a thin film transistor 20. The thin film transistor 20 is disposed on a surface of the substrate 10. The thin film transistor 20 includes a semiconductor layer 21, a crystallized inorganic layer 22, and a gate insulating layer 23. Among them, the semiconductor layer 21 is disposed on a surface of the substrate 10, the crystallized inorganic layer 22 is disposed on a surface of the semiconductor layer 21 away from the substrate 10, and the gate insulating layer 23 is disposed on a surface of the crystallized inorganic layer 22 away from the substrate 10.

[0052] See also Figure 2 In the present application, a crystallized inorganic layer 22 is disposed on a surface of the semiconductor layer away from the substrate. Compared with the gate insulating layer in the conventional display panel, the crystallized inorganic layer 22 of the present application has a better film surface density and fewer defects on the film surface. The provision of the crystallized inorganic layer 22 can better protect the front channel of the thin film transistor 20, thereby improving the gate control performance and stability of the thin film transistor 20 device.

[0053] On the other hand, in the present application, a crystallized inorganic layer 22 is provided on a surface of the semiconductor layer 21 away from the substrate 10. The material of the semiconductor layer 21 includes a crystallized metal oxide. In the process of high-temperature oxidation or high-temperature nitridation, the crystallized inorganic layer 22 will compete for oxygen in the semiconductor layer 21, and further form a dense film with fewer defects, and at the same time promote the crystallization of the crystallized metal oxide in the semiconductor layer 21. The stability of the thermal process of the semiconductor layer 21 is increased, and the diffusion length of the metal oxide with oxygen vacancies in the conductor part at the edge of the semiconductor layer 21 to the channel part in the semiconductor layer 21 is reduced, so as to ensure that the effective channel length of the semiconductor layer 21 is not shortened, and the stability of the TFT device is improved to realize the design of a narrow channel. At the same time, since the crystallized inorganic layer 22 separates the gate insulating layer 23 and the semiconductor layer 21, the influence of the relative content of hydrogen and oxygen in the gate insulating layer 23 on the semiconductor layer 21 is reduced.

[0054] Optionally, the material of the semiconductor layer 21 includes one of crystalline metal oxides such as indium gallium tin oxide (IGTO) and indium tin oxide (IGO).

[0055] Optionally, the raw material of the crystallized inorganic layer 22 includes silicon or other metal (such as aluminum, titanium, tantalum, etc.) materials.

[0056] Optionally, the material of the crystallized inorganic layer 22 includes inorganic oxide.

[0057] Optionally, the material of the crystallized inorganic layer 22 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide and molybdenum oxide.

[0058] In one embodiment of the present application, the raw material of the crystallized inorganic layer 22 is aluminum metal, and the material of the crystallized inorganic layer 22 is aluminum oxide. In the thermal process of the display panel, under the condition of high temperature oxidation, the crystallized inorganic layer 22 whose raw material is aluminum metal will compete for oxygen in the semiconductor layer 21, thereby forming dense aluminum oxide with fewer defects, so as to promote the crystallization of the amorphous metal oxide in the semiconductor layer 21.

[0059] In another embodiment of the present application, the raw material of the crystallized inorganic layer 22 is silicon, and the material of the crystallized inorganic layer 22 is silicon oxide. In the thermal process of the display panel, under the condition of high temperature oxidation, the crystallized inorganic layer 22 whose raw material is silicon will compete for oxygen in the semiconductor layer 21, thereby forming dense silicon oxide with fewer defects, so as to promote the crystallization of the amorphous metal oxide in the semiconductor layer 21.

[0060] See also Figure 2 Optionally, the thin film transistor 20 further includes a gate electrode 24, an interlayer dielectric layer 25, a source electrode 26 and a drain electrode 27. The gate electrode 24 is disposed on a surface of the gate insulating layer 23 away from the substrate 10. The interlayer dielectric layer 25 is disposed on a surface of the substrate 10 and covers the semiconductor layer 21, the crystallized inorganic layer 22, the gate insulating layer 23 and the gate electrode 24. The source electrode 26 is disposed on a surface of the interlayer dielectric layer 25 away from the substrate 10 and is electrically connected to the semiconductor layer 21. The drain electrode 27 is disposed on a surface of the interlayer dielectric layer 25 away from the substrate 10 and is electrically connected to the semiconductor layer 21.

[0061] Optionally, the array substrate 100 further includes a passivation layer 30 and a pixel electrode 40. The passivation layer 30 is disposed on a surface of the interlayer dielectric layer 25 away from the substrate 10 and covers the source electrode 26 and the drain electrode 27. The pixel electrode 40 is disposed on a surface of the passivation layer 30 away from the substrate 10 and is electrically connected to the drain electrode 27.

[0062] See also Figure 2 , leakage current will occur due to the semiconductor layer 21 of part of the thin film transistor 20 being exposed to light. Optionally, the base 10 further includes a substrate 11, a light shielding layer 12 and a buffer layer 13. The light shielding layer 12 is disposed on a surface of the substrate 11. The buffer layer 13 is disposed on a surface of the substrate 11 and covers the light shielding layer 12. The thin film transistor 20 is disposed on a surface of the buffer layer 13 away from the substrate 11. The light shielding layer 12 is electrically connected to the source 26.

[0063] The provision of the light shielding layer 12 can reduce the exposure of the semiconductor layer 21 to light on the side facing the substrate 11, thereby reducing the leakage current of the TFT device.

[0064] Optionally, the material of the light shielding layer 12 includes at least one of molybdenum, aluminum, copper, titanium, zinc oxide, and indium tin oxide.

[0065] Optionally, the material of the buffer layer 13 includes at least one of silicon oxide and silicon nitride.

[0066] See also Figure 2 Optionally, the semiconductor layer 21 includes a channel portion 211, a transition portion 212 and a lap portion 213. The channel portion 211 is provided on a surface of the substrate 10. The transition portion 212 is provided on a surface of the substrate 10 and is located at the periphery of the channel portion 211. The carrier concentration of the transition portion 212 is greater than the carrier concentration of the channel portion 211. The lap portion 213 is provided on a surface of the substrate 10 and is located on a side of the transition portion 212 away from the channel portion 211. The carrier concentration of the lap portion 213 is greater than the carrier concentration of the transition portion 212. The transition portion 212 connects the channel portion 211 and the lap portion 213. The crystallized inorganic layer 22 covers a surface of the channel portion 211 away from the substrate 10 and a surface of the transition portion 212 away from the substrate 10. The orthographic projection of the edge of the crystallized inorganic layer 22 on the substrate 10 is located on the outer peripheral side of the orthographic projection of the edge of the gate insulating layer 23 on the substrate 10.

[0067] Optionally, the orthographic projection of the edge of the transition portion 212 on the substrate 10 is located on the outer peripheral side of the orthographic projection of the edge of the gate insulating layer 23 on the substrate 10 .

[0068] Optionally, the orthographic projection of the edge of the gate insulating layer 23 on the substrate 10 is located on the outer peripheral side of the orthographic projection of the edge of the channel portion 211 on the substrate 10 .

[0069] In order to improve the device performance of the thin film transistor 20, the overlapping portion 213 of the semiconductor layer 21 needs to be subjected to a conductor treatment. The carrier concentration of the overlapping portion 213 after the conductor treatment is greater than the carrier concentration of the transition portion 212 and the carrier concentration of the channel portion 211. In the subsequent thermal process, since the carrier concentration of the overlapping portion 213 of the semiconductor layer 21 is greater than the carrier concentration of the transition portion 212, under high temperature conditions, the high concentration of metal oxides with oxygen vacancies in the overlapping portion 213 will diffuse to the transition portion 212, so that the carrier concentration of the transition portion 212 is greater than the carrier concentration of the channel portion 211.

[0070] See also Figure 1In the conventional thin film transistor 20a, the portion of the semiconductor layer 21a covered by the gate insulating layer 23a is the channel portion 211a and the transition portion 212a, and the portion of the semiconductor layer 21a not covered by the gate insulating layer 23a is the overlap portion 213a. Since the diffusion rate of the high-concentration metal oxide with oxygen vacancies in the overlap portion 213a is uncontrollable during the thermal process of the array substrate 100a, the high-concentration metal oxide with oxygen vacancies in part of the semiconductor layer 21a diffuses faster and diffuses to the transition portion 212a and the edge portion of the channel portion 211a in turn, shortening the effective channel length of the channel portion 211a. When the effective channel length of the channel portion 211a shortens, the gate control performance of the thin film transistor 20 device decreases.

[0071] See also Figure 2 In the embodiment of the present application, a crystallized inorganic layer 22 is added, and the orthographic projection of the edge of the crystallized inorganic layer 22 on the substrate 10 is located on the outer peripheral side of the orthographic projection of the edge of the gate insulating layer 23 on the substrate 10. In the process of conducting the semiconductor layer 21, the crystallized inorganic layer 22 is used as a mask. At this time, the part of the semiconductor layer 21 not covered by the crystallized inorganic layer 22 is formed as an overlap portion 213. Since the length of the crystallized inorganic layer 22 is longer than the length of the gate insulating layer 23, the length of the transition portion 212 in the semiconductor layer 21 is longer than the length of the transition portion 212a of the conventional thin film transistor 20a. In the thermal process of the array substrate 100, due to the increase in the length of the transition portion 212, the high concentration of metal oxide with oxygen vacancies in the overlap portion 213 can be prevented from diffusing into the channel portion 211, so as to ensure that the effective channel length of the channel portion 211 is not shortened, thereby improving the gate control performance of the thin film transistor 20 device.

[0072] Optionally, the transition portion 212 includes a first sub-portion 2121 and a second sub-portion 2122. The first sub-portion 2121 is located at the periphery of the channel portion 211.

[0073] The second sub-portion 2122 is located on a side of the first sub-portion 2121 away from the channel portion 211. The carrier concentration of the second sub-portion 2122 is greater than the carrier concentration of the first sub-portion 2121. The carrier concentration of the second sub-portion 2122 is less than the carrier concentration of the overlapping portion 213. The first sub-portion 2121 connects the channel portion 211 and the second sub-portion 2122. The second sub-portion 2122 connects the first sub-portion 2121 and the overlapping portion 213. The orthographic projection of the gate insulating layer 23 on the substrate 10 overlaps with the first sub-portion 2121. The orthographic projection of the edge of the second sub-portion 2122 on the substrate 10 is located on the outer peripheral side of the orthographic projection of the edge of the gate insulating layer 23 on the substrate 10.

[0074] Optionally, the orthographic projection of the gate insulating layer 23 on the substrate 10 overlaps with the orthographic projection of the channel portion 211 on the substrate 10 and the orthographic projection of the first sub-portion 2121 on the substrate 10 .

[0075] Optionally, the orthographic projection of the crystallized inorganic layer 22 on the substrate 10 overlaps with the orthographic projection of the channel portion 211 on the substrate 10 , the orthographic projection of the first sub-portion 2121 on the substrate 10 , and the orthographic projection of the second sub-portion 2122 on the substrate 10 .

[0076] See also Figure 3 In the top view of the array substrate 100, the length of the crystallized inorganic layer 22 in the long side direction of the semiconductor layer 21 is greater than the length of the gate insulating layer 23 in the long side direction of the semiconductor layer 21. The portion of the semiconductor layer 21 covered by the crystallized inorganic layer 22 and not covered by the gate insulating layer 23 is the second sub-portion 2122. The portion of the semiconductor layer 21 covered by the gate insulating layer 23 and not covered by the gate 24 is the first sub-portion 2121.

[0077] See also Figure 1 In the conventional semiconductor layer 21a, the transition portion 212a includes only the first sub-portion, so the length of the transition portion 212a is the length of the first sub-portion. Figure 2 In the semiconductor layer 21 of the present application, the transition portion 212 includes a first sub-portion 2121 and a second sub-portion 2122, so the length of the transition portion 212 is the sum of the length of the first sub-portion 2121 and the length of the second sub-portion 2122. The formation of the second sub-portion 2122 increases the length of the transition portion 212, ensuring that the length of the transition portion 212 of the present solution is longer than the length of the transition portion 212a of the traditional solution, and can prevent the high concentration of metal oxides with oxygen vacancies from diffusing from the overlapping portion 213 to the edge of the channel portion 211, so as to ensure that the effective channel length of the channel portion 211 is not shortened, thereby improving the gate control performance of the thin film transistor 20 device.

[0078] Optionally, the distance from the side of the transition portion 212 away from the channel portion 211 to the side of the transition portion 212 close to the channel portion 211 is in a range of 1 micron to 1.5 microns. The distance from the side of the first sub-portion 2121 away from the channel portion 211 to the side of the first sub-portion 2121 close to the channel portion 211 is in a range of 0.5 micron to 1 micron.

[0079] The length of the transition portion 212 is in the range of 1 micron to 1.5 microns, which can ensure good gate control performance of the thin film transistor 20 device. When the length of the transition portion 212 is less than 1 micron, the length of the transition portion 212 is short, and the transition portion 212 cannot play a role in blocking the high concentration of metal oxides with oxygen vacancies in the overlapping portion 213 from diffusing into the channel portion 211, resulting in the edge of the channel portion 211 infiltrating the metal oxides with oxygen vacancies diffused in the overlapping portion 213, so that the effective channel length of the channel portion 211 is shortened, affecting the gate control performance of the device. When the length of the transition portion 212 is greater than 1.5 microns, the thin film transistor 20 occupies a large area in the array substrate 100, which is not conducive to improving the resolution of the display panel.

[0080] In the manufacturing process of the array substrate 100, after the crystallized inorganic layer 22, the gate insulating layer 23 and the gate 24 are sequentially formed on the semiconductor layer 21, the gate insulating layer 23 and the crystallized inorganic layer 22 are patterned by using the principle of different dry etching selectivity. Among them, the etching speed of the gate insulating layer 23 is faster, and the etching speed of the crystallized inorganic layer 22 is slower, so in the long side direction of the semiconductor layer 21, the length of the crystallized inorganic layer 22 is greater than the length of the gate insulating layer 23. Since the second sub-portion 2122 is covered by the crystallized inorganic layer 22 of the transition portion 212 and is not covered by the gate insulating layer 23. Therefore, the present solution needs to reasonably control the selectivity of dry etching so that the length of the first sub-portion 2121 in the length direction of the semiconductor layer 21 is between 0.5 micrometers and 1 micrometer to ensure the stable performance of the thin film transistor 20 device.

[0081] The distance from the side of the transition portion 212 away from the channel portion 211 to the side of the transition portion 212 close to the channel portion 211 is one of 1.00 microns, 1.05 microns, 1.10 microns, 1.15 microns, 1.20 microns, 1.25 microns, 1.30 microns, 1.35 microns, 1.40 microns, 1.45 microns, and 1.50 microns.

[0082] The distance from the side of the first sub-portion 2121 away from the channel portion 211 to the side of the first sub-portion 2121 close to the channel portion 211 is one of 0.50 microns, 0.55 microns, 0.60 microns, 0.65 microns, 0.70 microns, 0.75 microns, 0.80 microns, 0.85 microns, 0.90 microns, 0.95 microns, and 1.00 microns.

[0083] Optionally, the distance from the side of the second sub-portion 2122 away from the channel portion 211 to the side of the second sub-portion 2122 close to the channel portion 211 is in the range of 0.5 micrometers to 1 micrometer. Since the length of the second sub-portion 2122 in the long side direction of the semiconductor layer 21 is determined by the gate insulating layer 23. When the length of the second sub-portion 2122 is too short, the insulating effect of the gate insulating layer 23 will be reduced, and the thin film transistor 20 device will be short-circuited. When the length of the second sub-portion 2122 is too long, the footprint of the thin film transistor 20 in the array substrate 100 increases, which is not conducive to the preparation of a high-resolution display panel.

[0084] The distance from the side of the second sub-portion 2122 away from the channel portion 211 to the side of the second sub-portion 2122 close to the channel portion 211 is one of 0.50 microns, 0.55 microns, 0.60 microns, 0.65 microns, 0.70 microns, 0.75 microns, 0.80 microns, 0.85 microns, 0.90 microns, 0.95 microns, and 1.00 microns.

[0085] Optionally, the distance from the side of the second sub-portion 2122 away from the channel portion 211 to the side of the second sub-portion 2122 close to the channel portion 211 is greater than the distance from the side of the first sub-portion 2121 away from the channel portion 211 to the side of the first sub-portion 2121 close to the channel portion 211 .

[0086] Under the premise of not affecting the internal insulation effect of the thin film transistor 20, the length of the second sub-portion 2122 is made greater than the length of the first sub-portion 2121, so as to achieve the goal of reducing the footprint of the thin film transistor 20 and ensuring that the effective channel length of the channel portion 211 remains unchanged, thereby achieving the effect of improving the resolution of the display panel and improving the gate control performance of the thin film transistor 20 device.

[0087] Optionally, the thickness of the crystallized inorganic layer 22 is smaller than the thickness of the semiconductor layer 21 . The thickness of the crystallized inorganic layer 22 is smaller than the thickness of the gate insulating layer 23 .

[0088] Reducing the thickness of the crystallized inorganic layer 22 can reduce the distance between the gate 24 and the channel portion 211 , thereby improving the gate control performance of the thin film transistor 20 device.

[0089] Optionally, the thickness of the crystallized inorganic layer 22 is in the range of 5 nm to 10 nm. The thickness of the crystallized inorganic layer 22 is one of 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm, and 10 nm.

[0090] The thickness of the crystallized inorganic layer 22 is in the range of 5 nanometers to 10 nanometers. On the one hand, the crystallized inorganic layer 22 has a certain thickness, which can compete for oxygen in the semiconductor layer 21 during the thermal process, and improve the stability of the channel portion 211 of the semiconductor layer 21 during the thermal process. On the other hand, the moderate thickness of the crystallized inorganic layer 22 can avoid the gate 24 and the channel portion 211 from being too large, and ensure the gate control performance of the thin film transistor 20 device.

[0091] Optionally, the thickness of the semiconductor layer 21 is in the range of 20 nanometers to 50 nanometers. The thickness of the semiconductor layer 21 is a value selected from 20 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, and 50 nanometers.

[0092] Optionally, the thickness of the gate insulating layer 23 is in the range of 100 nanometers to 200 nanometers. The thickness of the gate insulating layer 23 is one of 100 nanometers, 110 nanometers, 120 nanometers, 130 nanometers, 140 nanometers, 150 nanometers, 160 nanometers, 170 nanometers, 180 nanometers, 190 nanometers, and 200 nanometers.

[0093] The above is a detailed description of the specific implementation of the present application. The above implementation disclosed in the present application is only the preferred implementation of the present application. For ordinary technicians in this field, many modifications and improvements can be made without departing from the concept of the present application. These modifications and improvements all fall within the scope of protection defined by the claims of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; and A thin film transistor is disposed on a surface of the substrate, wherein the thin film transistor comprises a semiconductor layer, a crystallized inorganic layer and a gate insulating layer; The semiconductor layer is disposed on a surface of the substrate, the crystallized inorganic layer is disposed on a surface of the semiconductor layer away from the substrate, and the gate insulating layer is disposed on a surface of the crystallized inorganic layer away from the substrate.

2. The array substrate according to claim 1, characterized in that: The semiconductor layer comprises: A channel portion is provided on a surface of the substrate; A transition portion is provided on a surface of the substrate and is located at the periphery of the channel portion, wherein the carrier concentration of the transition portion is greater than the carrier concentration of the channel portion; A lap portion, disposed on a surface of the substrate and located on a side of the transition portion away from the channel portion, wherein the carrier concentration of the lap portion is greater than the carrier concentration of the transition portion; Wherein, the transition portion connects the channel portion and the overlapping portion, and the crystallized inorganic layer covers a surface of the channel portion away from the substrate and a surface of the transition portion away from the substrate; An orthographic projection of an edge of the crystallized inorganic layer on the substrate is located on an outer peripheral side of an orthographic projection of an edge of the gate insulating layer on the substrate.

3. The array substrate according to claim 2, characterized in that: The transition section comprises: A first sub-portion, located at the periphery of the channel portion; A second sub-portion is located at a side of the first sub-portion away from the channel portion, the carrier concentration of the second sub-portion is greater than the carrier concentration of the first sub-portion, and the carrier concentration of the second sub-portion is less than the carrier concentration of the overlapping portion; Wherein, the first sub-portion connects the channel portion and the second sub-portion, and the second sub-portion connects the first sub-portion and the overlapping portion; The orthographic projection of the gate insulating layer on the substrate overlaps with the first sub-portion; An orthographic projection of an edge of the second sub-portion on the substrate is located on an outer peripheral side of an orthographic projection of an edge of the gate insulating layer on the substrate.

4. The array substrate according to claim 3, characterized in that: A distance between a side of the transition portion away from the channel portion and a side of the transition portion close to the channel portion is in a range of 1 micrometer to 1.5 micrometers; A distance from a side of the first sub-portion away from the channel portion to a side of the first sub-portion close to the channel portion is in a range of 0.5 micrometers to 1 micrometer.

5. The array substrate according to claim 4, characterized in that: A distance from a side of the second sub-portion away from the channel portion to a side of the second sub-portion close to the channel portion is in a range of 0.5 micrometers to 1 micrometer.

6. The array substrate according to claim 5, characterized in that: A distance from a side of the second sub-portion away from the channel portion to a side of the second sub-portion close to the channel portion is greater than a distance from a side of the first sub-portion away from the channel portion to a side of the first sub-portion close to the channel portion.

7. The array substrate according to any one of claims 1 to 6, characterized in that: The thickness of the crystallized inorganic layer is smaller than the thickness of the semiconductor layer; The thickness of the crystallized inorganic layer is smaller than the thickness of the gate insulating layer.

8. The array substrate according to claim 7, characterized in that: The thickness of the crystallized inorganic layer is in a range of 5 nanometers to 10 nanometers.

9. The array substrate according to any one of claims 1 to 6, characterized in that: The thin film transistor further comprises: A gate is disposed on a surface of the gate insulating layer away from the substrate; an interlayer dielectric layer, disposed on a surface of the substrate and covering the semiconductor layer, the crystallized inorganic layer, the gate insulating layer and the gate; A source electrode is disposed on a surface of the interlayer dielectric layer away from the substrate and is electrically connected to the semiconductor layer; and A drain electrode is disposed on a surface of the interlayer dielectric layer away from the substrate and is electrically connected to the semiconductor layer; The array substrate further comprises a passivation layer and a pixel electrode, wherein the passivation layer is disposed on a surface of the interlayer dielectric layer away from the substrate and covers the source electrode and the drain electrode; and A pixel electrode, disposed on a surface of the passivation layer away from the substrate and electrically connected to the drain electrode; The substrate comprises: substrate; a light shielding layer disposed on a surface of the substrate; and A buffer layer, disposed on a surface of the substrate and covering the light shielding layer; The thin film transistor is arranged on a surface of the buffer layer away from the substrate, and the light shielding layer is electrically connected to the source electrode.

10. A display panel, characterized in that: It comprises an array substrate as described in any one of claims 1 to 9.

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