Analog-to-digital converter based on static bootstrap circuit
By using static bootstrap circuit and charge pump technology in the analog-to-digital converter, the high level of the clock signal is raised, and the problem of sampling speed limit of the bottom plate is solved, high-speed and high-precision analog-to-digital conversion is realized, and the analog-to-digital conversion is improved. Performance and accuracy of the digital converter.
Patent Information
- Application Number
- CN202421078822.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-17
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2034-05-17
AI Technical Summary
In high-speed and high-precision analog-to-digital converters, the sampling speed of the bottom plate is limited, resulting in sampling errors and nonlinear errors, affecting the performance and accuracy of the analog-to-digital converter.
Using an analog-to-digital converter based on a static bootstrap circuit, the switching capacitor circuit consisting of gate voltage bootstrap switch, static bootstrap circuit, MOS switch, sampling capacitor, and feedback capacitor is used to convert the high-level amplitude of the clock signal using the charge pump circuit. Raise it to 2VDD, reduce switch on resistance, reduce parasitic capacitance and leakage, and achieve high-speed and high-precision bottom plate sampling.
It effectively improves the speed and accuracy of bottom plate sampling, reduces the switching on-resistance, improves the performance and accuracy of analog-to-digital converters, and meets the needs of modern communication systems and instruments.
Smart Images
Figure CN222283234U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a circuit structure for a high-speed and high-precision analog-to-digital converter, in particular to an analog-to-digital converter based on a static bootstrap circuit. Background Art
[0002] With the rapid development of wireless communication equipment and radar technology, RF direct sampling analog-to-digital converters have gradually become mainstream applications due to their smaller hardware overhead and higher energy efficiency. In current communication systems and high-performance instruments, analog-to-digital converters with a resolution of 10 to 14 bits and a sampling frequency higher than 1GS / s have become core components. Analog-to-digital converters operating under such high sampling rates usually adopt a pipeline architecture. In pipeline analog-to-digital converters, in order to meet the requirements of high sampling rates and high precision, the sample-and-hold circuit is crucial to complete the sampling and holding of the front-end signal.
[0003] In the sample-and-hold circuit, the inherent charge injection effect and clock feedthrough effect of the MOS switch tube may cause the error to change with the signal input amplitude, thereby causing nonlinear errors in the sample-and-hold circuit. In order to effectively eliminate the charge injection effect of the sampling switch, the bottom plate sampling technology becomes a solution.
[0004] This technology maintains the charge on the upper plate during the sampling process, and before the sampling switch is turned off, the path between the maintained charge and the charge on the upper plate is cut off. These errors can be effectively reduced and the performance and accuracy of the ADC can be improved through the bottom plate sampling technology. However, compared with the top plate sampling, the speed of bottom plate sampling is usually limited, which brings challenges to the design of high-speed and high-precision analog-to-digital converters. Therefore, in the design of high-speed and high-precision analog-to-digital converters, how to overcome the speed limitation of bottom plate sampling has become a technical problem that needs to be solved urgently. Summary of the invention
[0005] The technical problem to be solved by the utility model is to provide an analog-to-digital converter based on a static bootstrap circuit which can effectively improve the speed and accuracy of bottom plate sampling.
[0006] In order to solve the above technical problems, the utility model is a digital-to-analog converter based on a static bootstrap circuit, including a switched capacitor circuit and an operational amplifier A1 and an operational amplifier A2. The switched capacitor circuit is composed of a gate voltage bootstrap switch S1, a gate voltage bootstrap switch S2, a static bootstrap circuit B1, a static bootstrap circuit B2, a MOS switch S3, a MOS switch S4, a MOS switch S5, a MOS switch S6, a MOS switch S7, a MOS switch S8, a MOS switch S9, a MOS switch S 10 And the sampling capacitor C S and feedback capacitor C FThe operational amplifier A1 and the operational amplifier A2 are both single-ended input and single-ended output, and one end of the operational amplifier A1 is connected to the MOS switch S3, and one end of the operational amplifier A2 is connected to the MOS switch S4, and the other ends of the operational amplifier A1 and the operational amplifier A2 are connected to the output end, thereby forming a pseudo differential structure together; the sampling capacitor C S There are two sampling capacitors, one C S are connected between the gate voltage bootstrap switch S1 and the input of the operational amplifier A1, a sampling capacitor C S They are connected between the gate voltage bootstrap switch S2 and the input of the operational amplifier A2, and the feedback capacitor C F There are two feedback capacitors C F The gate voltage bootstrap switch S1 and the gate voltage bootstrap switch S2 are respectively connected across the input and output terminals of the operational amplifier A1 and the input and output terminals of the operational amplifier A2. The input terminals of the gate voltage bootstrap switch S1 and the gate voltage bootstrap switch S2 are both provided with sampling phase clocks. , sampling capacitor C S The lower plate and V cm Voltage connection, one end of the static bootstrap circuit B1 is connected to MOS switch S7 and MOS switch S8, and the other end is connected to the amplified phase clock , one end of the static bootstrap circuit B2 is connected to the MOS switch S3 and the MOS switch S4, and the other end is connected to the sampling phase early disconnect clock MOS switches S5 and S6, MOS switches S7, S8, S9 and S10 are provided between the output terminals of the operational amplifier A1 and the operational amplifier A2, and are capable of resetting the feedback capacitor. 10 It can form a negative feedback amplification structure together with operational amplifier A1 and operational amplifier A2 in the amplification stage.
[0007] The sampling capacitor C S The size of the feedback capacitor C F twice.
[0008] The static bootstrap circuit B1 and the static bootstrap circuit B2 both have a charge pump circuit capable of raising the amplitude of a clock signal for controlling a switch connected to a DC signal from VDD to 2VDD.
[0009] The charge pump circuit is composed of an inverter INV1, an inverter INV2, a transmission gate S1, a capacitor C1 and a capacitor C2.
[0010] The static bootstrap circuit B1 and the static bootstrap circuit B2 also respectively include a circuit loop enclosed by branch No. 1, branch No. 2, branch No. 3 and branch No. 4. The charge pump circuit is connected between branch No. 1 and branch No. 3 through switch tube M1 and switch tube M2. At the same time, switch tube M3 is connected between branch No. 1 and branch No. 3. An output port of switch tube M3 is connected to branch No. 2 through capacitor C3 and inverter INV3. INV4 and INV5 are provided on branch No. 2. Switch tube M4 and capacitor C4 are connected to branch No. 4. Switch tube M5 is connected to branch No. 4 and is located between switch tube M4 and capacitor C4. Switch tube M4 is also connected between INV4 and INV5.
[0011] An output node CLK_BTS is provided between the switch tube M5 and the switch tube M6.
[0012] The advantages of the utility model are:
[0013] An analog-to-digital converter based on a static bootstrap circuit is formed by setting up a gate voltage bootstrap switch, a static bootstrap circuit, a MOS switch, a switching capacitor circuit composed of a sampling capacitor and a feedback capacitor, and an operational amplifier. Through the bottom plate sampling structure with a static bootstrap circuit, the amplitude of the high level of the clock signal that controls the DC signal switch is raised to 2VDD, thereby achieving a smaller switch on-resistance, and reducing the size of the switch tube to reduce parasitic capacitance and leakage, thereby achieving high-speed and high-precision bottom plate sampling, thereby achieving the purpose of improving performance and improving accuracy. This can effectively cope with the challenges of bottom plate sampling technology in high-speed and high-precision analog-to-digital converters, thereby meeting the needs of modern communication systems and instruments. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 The utility model is a circuit diagram of an analog-to-digital converter based on a static bootstrap circuit;
[0015] Figure 2 It is a circuit diagram of a static bootstrap circuit in the utility model;
[0016] Figure 3 This is a model diagram of the output voltage of the static bootstrap circuit in the utility model. DETAILED DESCRIPTION
[0017] The following is a further detailed description of the analog-to-digital converter based on the static bootstrap circuit of the present utility model in conjunction with the accompanying drawings and specific implementation modes.
[0018] As shown in the figure, the analog-to-digital converter based on the static bootstrap circuit of the utility model includes a switched capacitor circuit and an operational amplifier A1 and an operational amplifier A2. The switched capacitor circuit is composed of a gate voltage bootstrap switch S1, a gate voltage bootstrap switch S2, a static bootstrap circuit B1, a static bootstrap circuit B2, a MOS switch S3, a MOS switch S4, a MOS switch S5, a MOS switch S6, a MOS switch S7, a MOS switch S8, a MOS switch S9, a MOS switch S 10 And the sampling capacitor C S and feedback capacitor C F The operational amplifier A1 and the operational amplifier A2 are both single-ended input and single-ended output, and one end of the operational amplifier A1 is connected to the MOS switch S3, and one end of the operational amplifier A2 is connected to the MOS switch S4, and the other ends of the operational amplifier A1 and the operational amplifier A2 are connected to the output end, thereby forming a pseudo differential structure together; the sampling capacitor C S There are two sampling capacitors, one C S are connected between the gate voltage bootstrap switch S1 and the input of the operational amplifier A1, a sampling capacitor C S They are connected between the gate voltage bootstrap switch S2 and the input of the operational amplifier A2, and the feedback capacitor C F There are two feedback capacitors C F The sampling capacitor C is connected across the input and output terminals of the operational amplifier A1 and the input and output terminals of the operational amplifier A2 respectively. S The size of the feedback capacitor C F 2 times, that is: capacitance C S =2C F The input terminals of the gate voltage bootstrap switch S1 and the gate voltage bootstrap switch S2 are both provided with sampling phase clocks. , sampling capacitor C S The lower plate and V Cm Voltage connection, one end of the static bootstrap circuit B1 is connected to MOS switch S7 and MOS switch S8, and the other end is connected to the amplified phase clock , one end of the static bootstrap circuit B2 is connected to the MOS switch S3 and the MOS switch S4, and the other end is connected to the sampling phase early disconnect clock MOS switches S5 and S6, MOS switches S7, S8, S9 and S10 are provided between the output terminals of the operational amplifiers A1 and A2, which can reset the plates of the feedback capacitors. 10 It can form a negative feedback amplification structure together with operational amplifier A1 and operational amplifier A2 in the amplification stage;
[0019] In the figure, V ip 、V in is the input signal, Vxp 、V xn is the voltage at the op amp input, V outp 、V outn is the voltage at the output of the op amp, C s is the sampling capacitor, C F is the feedback capacitor, A is the gain of the amplifier, and its working principle is: in the sampling stage, the gate voltage bootstrap switch S1, the gate voltage bootstrap switch S2, the MOS switch S3, and the MOS switch S4 are turned on, and the capacitor C S The input signal is sampled, where the lower plate of the MDAC input positive and negative sampling capacitor CS is connected to V cm The voltage connection is performed, where MOS switches S3 and S4 are controlled by the sampling clock that is disconnected in advance. At the same time, MOS switches S5 and S6 are turned on to reset the plate of the feedback capacitor to prevent the residual charge from affecting the charge information in the amplification stage. In the amplification stage, MOS switches S7, S8, S9, and S 10 It is turned on and together with the operational amplifier forms a negative feedback amplification structure.
[0020] It can be seen from the above working principle that MOS switch S3, MOS switch S4, MOS switch S5, MOS switch S6, MOS switch S7, and MOS switch S8 are all connected to DC signals when they are turned on. During the bottom plate sampling process, the on resistance is determined by the width-to-length ratio of the MOS tube and the overdrive voltage. When the signal is on, the overdrive voltage is very small, and the larger on-resistance will limit the speed of bottom plate sampling. In order to meet the speed requirement, a larger MOS tube is needed, but this will bring about a larger parasitic capacitance and leakage, thereby affecting the accuracy of bottom plate sampling. Therefore, a static bootstrap circuit is provided in the utility model, which increases the overdrive voltage of the switch tube by increasing the high level of the clock signal to 2VDD. This design can use a smaller MOS tube to achieve the required on-resistance, meet the speed requirement of bottom plate sampling, and reduce the dependence on large-sized MOS tubes, which helps to improve the accuracy and stability of bottom plate sampling.
[0021] Furthermore, if Figure 2As shown, both the static bootstrap circuit B1 and the static bootstrap circuit B2 have a charge pump circuit capable of raising the amplitude of the clock signal controlling the connection of the DC signal switch from VDD to 2VDD. The charge pump circuit is composed of an inverter INV1, an inverter INV2, a transmission gate S1, a capacitor C1 and a capacitor C2. The charge pump principle is used to raise the amplitude of the clock signal controlling the connection of the DC signal switch from VDD to 2VDD to increase the overdrive voltage of the MOS tube, thereby reducing the on-resistance of the switch. The static bootstrap circuit B1 and the static bootstrap circuit B2 also include circuit loops enclosed by a No. 1 branch 1, a No. 2 branch 2, a No. 3 branch 3 and a No. 4 branch 4, respectively. The charge pump circuit is connected between the No. 1 branch and the No. 3 branch through the switch tube M1 and the switch tube M2. At the same time, a switch tube M3 is connected between branch No. 1 and branch No. 3 (specifically, one port of the switch tube M3 is connected between the switch tube M1 and the capacitor C1), and an output port of the switch tube M3 is connected to branch No. 2 through capacitor C3 and inverter INV3. Capacitor C3 and a circuit in which switch tubes M5 and M6 are connected in series form a parallel circuit. An output node CLK_BTS is provided between switch tubes M5 and M6. Inverters INV4 and INV5 are provided on branch No. 2, and switch tube M4 and capacitor C4 are connected to branch No. 4. One end of switch tube M5 is connected to branch No. 4 and is located between switch tube M4 and capacitor C4, and one end of switch tube M4 is also connected between inverter INV4 and inverter INV5.
[0022] Its principle is as follows Figure 2As shown, inverters INV1, INV2, transmission gate S1 and capacitors C1, C2 form a charge pump circuit. When CLK=0, the voltage of node 1 becomes VDD, the voltage of nodes 2 and 3 becomes low level, the voltage of the upper plate of C1 is raised to 2VDD, M2 and M3 are turned on, and capacitors C2 and C3 are charged. At the same time, the voltage of node 6 becomes low level, node 7 becomes high level, switch tube M4 is turned on, and the voltage of both plates of capacitor C4 becomes VDD, and switch tube M5 is turned off. Since the voltage of node 3 is low level at this time, the output node CLK_BTS is discharged, and the output voltage drops to 0. When CLK=1, node 1 becomes low level, nodes 2, 3, and 6 become high level, the voltage of the upper plates of capacitors C2 and C3 is raised to 2VDD, M1 is turned on, and capacitor C1 is charged to VDD, and switch tubes M2, M3, and M4 are turned off. The voltage on the upper plate of capacitor C3 is raised to 2VDD, the voltage on node 7 is low, the voltage on the upper plate of capacitor C4 becomes low, the switch tube M5 is turned on, capacitor C3 and switch tube M5 form a path, and the output voltage of output node CLK_BTS is 2VDD. Through this process, the high level of the clock signal that controls the switch tube can be raised to 2VDD, thereby greatly reducing the on-resistance of the switch tube. This design makes the bottom plate sampling more stable and reliable, which helps to realize a high-speed and high-precision analog-to-digital converter.
[0023] like Figure 3 As shown, the parasitic capacitance of the switch tube It will reduce the amplitude of the raised clock signal. According to the law of conservation of charge, we can get:
[0024]
[0025]
[0026] In this static bootstrap circuit, when When the parasitic capacitance Cp has an influence on the output voltage Therefore, by selecting a larger capacitor C3, the influence of the parasitic capacitance Cp on the circuit can be effectively reduced, making the output voltage Close to 2VDD. This can increase the overdrive voltage of the switch, thereby reducing the on-resistance of the switch and achieving better performance and accuracy.
[0027] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the protection scope of the present invention.
Claims
1. An analog-to-digital converter based on a static bootstrap circuit, comprising a switched capacitor circuit and operational amplifiers A1 and A2, characterized in that: The switch capacitor circuit comprises a gate voltage bootstrap switch S1, a gate voltage bootstrap switch S2, a static bootstrap circuit B1, a static bootstrap circuit B2, a MOS switch S3, a MOS switch S4, a MOS switch S5, a MOS switch S6, a MOS switch S7, a MOS switch S8, a MOS switch S9, a MOS switch S 10 And the sampling capacitor C S and feedback capacitor C F The operational amplifier A1 and the operational amplifier A2 are both single-ended input and single-ended output, and one end of the operational amplifier A1 is connected to the MOS switch S3, and one end of the operational amplifier A2 is connected to the MOS switch S4, and the other ends of the operational amplifier A1 and the operational amplifier A2 are connected to the output end, thereby forming a pseudo differential structure together; the sampling capacitor C S There are two sampling capacitors, one C S are connected between the gate voltage bootstrap switch S1 and the input of the operational amplifier A1, a sampling capacitor C S They are connected between the gate voltage bootstrap switch S2 and the input of the operational amplifier A2, and the feedback capacitor C F There are two feedback capacitors C F The gate voltage bootstrap switch S1 and the gate voltage bootstrap switch S2 are respectively connected across the input and output terminals of the operational amplifier A1 and the input and output terminals of the operational amplifier A2. The input terminals of the gate voltage bootstrap switch S1 and the gate voltage bootstrap switch S2 are both provided with a sampling phase clock , the sampling capacitor C S The lower plate and V cm voltage connection, one end of the static bootstrap circuit B1 is connected to the MOS switch S7 and the MOS switch S8, and the other end is connected to the amplified phase clock One end of the static bootstrap circuit B2 is connected to the MOS switch S3 and the MOS switch S4, and the other end is connected to the sampling phase advance disconnect clock MOS switches S5 and S6 are provided between the output terminals of the operational amplifier A1 and the operational amplifier A2, and the MOS switches S7, S8, S9 and S 10 It can form a negative feedback amplification structure together with operational amplifier A1 and operational amplifier A2 in the amplification stage.
2. The analog-to-digital converter based on the static bootstrap circuit according to claim 1, characterized in that: The sampling capacitor C S The size of the feedback capacitor C F twice.
3. The analog-to-digital converter based on the static bootstrap circuit according to claim 1, characterized in that: The static bootstrap circuit B1 and the static bootstrap circuit B2 both have a charge pump circuit capable of raising the amplitude of a clock signal for controlling a switch connected to a DC signal from VDD to 2VDD.
4. The analog-to-digital converter based on the static bootstrap circuit according to claim 3, characterized in that: The charge pump circuit is composed of an inverter INV1, an inverter INV2, a transmission gate S1, a capacitor C1 and a capacitor C2.
5. The analog-to-digital converter based on the static bootstrap circuit according to claim 4, characterized in that: The static bootstrap circuit B1 and the static bootstrap circuit B2 further comprise a circuit loop enclosed by a No. 1 branch (1), a No. 2 branch (2), a No. 3 branch (3) and a No. 4 branch (4), respectively; the charge pump circuit is connected between the No. 1 branch and the No. 3 branch via a switch tube M1 and a switch tube M2; a switch tube M3 is connected between the No. 1 branch (1) and the No. 3 branch (3); an output port of the switch tube M3 is connected to the No. 2 branch via a capacitor C3 and an inverter INV3; the switch tube M2 is also connected to the No. 2 branch via a capacitor C3 and an inverter INV3; After the switch tube M3, a parallel circuit consisting of a capacitor C3 and a switch tube M5 and a switch tube M6 connected in series is connected in parallel, and the parallel circuit is connected to the second branch through INV3. The second branch is provided with an inverter INV4 and an inverter INV5. The fourth branch is connected with a switch tube M4 and a capacitor C4. The switch tube M5 is connected to the fourth branch and is located between the switch tube M4 and the capacitor C4. The switch tube M4 is also connected between the inverter INV4 and the inverter INV5.
6. The analog-to-digital converter based on the static bootstrap circuit according to claim 5, characterized in that: An output node CLK_BTS is provided between the switch tube M5 and the switch tube M6.