Frequency synchronization signal circuit for inverter wired parallel operation

Abstract

The utility model relates to a frequency synchronizing signal circuit for wired parallel operation of inverters, which is used for transmitting and receiving frequency synchronizing signals of two inverters in parallel operation and comprises a signal transmitting circuit and a signal receiving circuit, and the output end of the signal transmitting circuit and the input end of the signal receiving circuit are the same pair of connecting ends. A frequency synchronizing signal output by the host micro-control unit is transmitted to the slave synchronizing signal end through the signal transmitting circuit, and then is transmitted to the slave micro-control unit through the slave synchronizing signal end, so that the frequency synchronization of the slave and the host is realized. The signal transmitting circuit and the signal receiving circuit realize bidirectional transmission of frequency synchronization signals, and can transmit the frequency synchronization signals and receive the frequency synchronization signals. And meanwhile, the transmitting end and the receiving end of the signal are isolated through the photoelectric coupler, so that the circuit has good electric insulation capability and anti-interference capability. The circuit is built through discrete components, parallel operation of analog signals can be achieved, and the circuit cost is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of power supply, in particular to a frequency synchronization signal circuit of a wired parallel inverter. Background Art

[0002] An inverter is a converter that converts DC power into constant frequency and voltage or frequency and voltage-regulated AC power. Large inverters are usually used to integrate the power generated by photovoltaic power generation or wind power generation into the AC power grid, and small inverters are usually used to convert DC power in batteries into AC power for household appliances. When the output power of a single inverter is insufficient, multiple inverters can be connected in parallel to form a distributed power supply. Distributed power supply can improve the reliability of power supply and the scalability of capacity.

[0003] In recent years, as the power demand of users' electrical equipment has gradually increased, the single-machine working mode can no longer meet the power demand, and the parallel working mode is increasingly adopted. Multiple inverters are connected together in parallel to share the load current and share the load, thereby improving the overall stability and reliability.

[0004] The frequency of the inverter is an important parameter of AC power. The key to achieving parallel operation of the inverter is frequency synchronization control, which requires the output voltage, frequency and phase of the inverter to be the same. Through synchronization control, closed-loop control of current and voltage can be achieved between the inverter outputs, thereby ensuring the stability and reliability of parallel operation. Existing frequency synchronization circuits are often built using integrated circuits, which have high circuit costs. Utility Model Content

[0005] In view of this, it is necessary to provide a frequency synchronization signal circuit for wired parallel inverters which is constructed by discrete components and has a simple circuit structure.

[0006] A frequency synchronization signal circuit for wired parallel operation of inverters is used for sending and receiving frequency synchronization signals of two parallel-operated inverters, wherein the two parallel-operated inverters include a host and a slave, and include a signal sending circuit and a signal receiving circuit, wherein the output end of the signal sending circuit and the input end of the signal receiving circuit are the same pair of connection ends, wherein the pair of connection ends include a first connection end CS-SYN+ and a second connection end CS-SYN-, wherein the first connection end CS-SYN+ and the second connection end CS-SYN- are connected to a slave synchronization signal end; the input end TXD of the signal sending circuit is connected to the output end of a host micro-control unit, and the output end RXD of the signal receiving circuit is connected to the input end of a slave micro-control unit, so that the frequency synchronization signal output by the host micro-control unit is transmitted to the slave synchronization signal end via the signal sending circuit, and then transmitted to the slave micro-control unit by the slave synchronization signal end, thereby realizing frequency synchronization between the slave and the host.

[0007] Preferably, the signal sending circuit includes a second optocoupler OPT2 and a ninth resistor R9, the second optocoupler OPT2 includes a second primary light-emitting diode and a second secondary photosensitive transistor, the cathode of the second primary light-emitting diode is the input terminal TXD of the signal sending circuit, and the anode of the second primary light-emitting diode is connected to a 3.3V power supply through the ninth resistor R9; the collector of the second secondary photosensitive transistor is connected to the first connection terminal CS-SYN+, and the emitter of the second secondary photosensitive transistor is connected to the second connection terminal CS-SYN- through an eighth resistor R8, and is also connected to the ground 5V_GND.

[0008] Preferably, a second transistor Q2 and a second capacitor C2 are further provided between the first connection terminal CS-SYN+ and the second connection terminal CS-SYN-, the base of the second transistor Q2 is connected to the emitter of the second secondary photosensitive transistor and the midpoint of the eighth resistor R8, and the two ends of the second capacitor C2 are respectively connected to the collector and emitter of the second transistor Q2, and are respectively connected to the first connection terminal CS-SYN+ and the second connection terminal CS-SYN-.

[0009] Preferably, the signal receiving circuit includes a first optocoupler OPT1, a first resistor R1, a first capacitor C1 and a second resistor R2, the first optocoupler OPT1 includes a first primary light-emitting diode and a first secondary photosensitive transistor, the collector of the first secondary photosensitive transistor is connected to a 3.3V power supply through the first resistor R1, and is connected to the output end RXD of the signal receiving circuit through the second resistor R2, and the emitter of the first secondary photosensitive transistor is connected to the ground 3.3V_GND; the two ends of the first capacitor C1 are respectively connected to the collector and emitter of the first secondary photosensitive transistor.

[0010] Preferably, the anode of the first primary light-emitting diode is connected to a 5V power supply through a third resistor R3, the cathode of the first primary light-emitting diode is connected to the collector of the second secondary photosensitive transistor through a first transistor Q1 and a seventh resistor R7, the collector of the first transistor Q1 is connected to the cathode of the first primary light-emitting diode, and the emitter of the first transistor Q1 is connected to the first connection terminal CS-SYN+ through the seventh resistor R7.

[0011] Preferably, it also includes a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6 connected in series, wherein the two ends of the fourth resistor R4 are respectively connected to the anode and cathode of the first primary light-emitting diode, the two ends of the fifth resistor R5 are respectively connected to the collector and base of the first transistor Q1, and the two ends of the sixth resistor R6 are respectively connected to the base of the first transistor Q1 and the first connection terminal CS-SYN+.

[0012] The frequency synchronization signal circuit of the above-mentioned inverter wired parallel machine is used for mobile energy storage inverter output wired parallel machine or other inverter output wired parallel machine. The signal sending circuit and the signal receiving circuit realize the two-way transmission of the frequency synchronization signal, which can send the frequency synchronization signal and receive the frequency synchronization signal; at the same time, the sending end and the receiving end of the signal are isolated and processed by the photoelectric coupler, so that the circuit has good electrical insulation and anti-interference capabilities. This circuit is constructed by discrete components, which can realize the parallel machine of analog signals and reduce the circuit cost. The circuit structure of the utility model is simple, easy to implement, low cost, and easy to promote. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The utility model is a circuit structure diagram of a frequency synchronization signal circuit of a wired parallel inverter according to an embodiment of the utility model. DETAILED DESCRIPTION

[0014] The present invention will be described in detail below with reference to specific embodiments and accompanying drawings.

[0015] See also Figure 1 , shows a frequency synchronization signal circuit for wired parallel operation of inverters, which is used to send and receive frequency synchronization signals of two parallel-operated inverters, wherein the two parallel-operated inverters include a host and a slave, and include a signal sending circuit and a signal receiving circuit, wherein the output end of the signal sending circuit and the input end of the signal receiving circuit are the same pair of connection ends, wherein the pair of connection ends include a first connection end CS-SYN+ and a second connection end CS-SYN-, wherein the first connection end CS-SYN+ and the second connection end CS-SYN- are connected to the slave synchronization signal end; the input end TXD of the signal sending circuit is connected to the output end of the host micro-control unit, and the output end RXD of the signal receiving circuit is connected to the input end of the slave micro-control unit, so that the frequency synchronization signal output by the host micro-control unit is transmitted to the slave synchronization signal end through the signal sending circuit, and then transmitted to the slave micro-control unit by the slave synchronization signal end, thereby realizing frequency synchronization between the slave and the host.

[0016] Specifically, the first connection terminal CS-SYN+ and the second connection terminal CS-SYN- are both the output terminals of the signal sending circuit and the input terminals of the signal receiving circuit. The first connection terminal CS-SYN+ and the second connection terminal CS-SYN- are connected to the slave synchronization signal terminal, so that the slave can receive the frequency synchronization signal sent by the host, and at the same time, can also send the received frequency synchronization signal to the micro-control unit of the slave.

[0017] Specifically, the signal sending circuit and the signal receiving circuit respectively include a photoelectric coupler, and two photoelectric couplers are reversely arranged in the signal sending circuit and the signal receiving circuit to realize bidirectional transmission of the frequency synchronization signal in the same circuit.

[0018] Preferably, the signal sending circuit includes a second optocoupler OPT2 and a ninth resistor R9, the second optocoupler OPT2 includes a second primary light-emitting diode and a second secondary photosensitive transistor, the cathode of the second primary light-emitting diode is the input terminal TXD of the signal sending circuit, and the anode of the second primary light-emitting diode is connected to a 3.3V power supply through the ninth resistor R9; the collector of the second secondary photosensitive transistor is connected to the first connection terminal CS-SYN+, and the emitter of the second secondary photosensitive transistor is connected to the second connection terminal CS-SYN- through an eighth resistor R8, and is also connected to the ground 5V_GND.

[0019] Preferably, a second transistor Q2 and a second capacitor C2 are further provided between the first connection terminal CS-SYN+ and the second connection terminal CS-SYN-, the base of the second transistor Q2 is connected to the emitter of the second secondary photosensitive transistor and the midpoint of the eighth resistor R8, and the two ends of the second capacitor C2 are respectively connected to the collector and emitter of the second transistor Q2, and are respectively connected to the first connection terminal CS-SYN+ and the second connection terminal CS-SYN-.

[0020] Preferably, the signal receiving circuit includes a first optocoupler OPT1, a first resistor R1, a first capacitor C1 and a second resistor R2, the first optocoupler OPT1 includes a first primary light-emitting diode and a first secondary photosensitive transistor, the collector of the first secondary photosensitive transistor is connected to a 3.3V power supply through the first resistor R1, and is connected to the output end RXD of the signal receiving circuit through the second resistor R2, and the emitter of the first secondary photosensitive transistor is connected to the ground 3.3V_GND; the two ends of the first capacitor C1 are respectively connected to the collector and emitter of the first secondary photosensitive transistor.

[0021] Preferably, the anode of the first primary light-emitting diode is connected to a 5V power supply through a third resistor R3, the cathode of the first primary light-emitting diode is connected to the collector of the second secondary photosensitive transistor through a first transistor Q1 and a seventh resistor R7, the collector of the first transistor Q1 is connected to the cathode of the first primary light-emitting diode, and the emitter of the first transistor Q1 is connected to the first connection terminal CS-SYN+ through the seventh resistor R7.

[0022] Preferably, it also includes a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6 connected in series, wherein the two ends of the fourth resistor R4 are respectively connected to the anode and cathode of the first primary light-emitting diode, the two ends of the fifth resistor R5 are respectively connected to the collector and base of the first transistor Q1, and the two ends of the sixth resistor R6 are respectively connected to the base of the first transistor Q1 and the first connection terminal CS-SYN+.

[0023] In this embodiment, the AC output terminals of two inverters of the same model and specification are connected through external connection lines, and the synchronization signal ports of two inverters of the same model and specification are connected through external connection lines, and are respectively connected to the first connection terminal CS-SYN+ and the second connection terminal CS-SYN-. Among the two inverters, one is defined as the host and the other is defined as the slave. The host sends a frequency synchronization signal for parallel operation through the first connection terminal CS-SYN+ and the second connection terminal CS-SYN-, and the slave receives the frequency synchronization signal through the first connection terminal CS-SYN+ and the second connection terminal CS-SYN- and realizes frequency synchronization. This circuit has both sending and receiving functions. In this embodiment, the host and the slave are interchangeable.

[0024] The host micro-control unit sends a 3.3V square wave signal between the input terminal TXD and 3.3V_GND of the signal sending circuit, which is converted into a 5V square wave signal with the same frequency and amplitude through the signal sending circuit of this analog circuit, and then transmitted to the external port through the first connection terminal CS-SYN+ and the second connection terminal CS-SYN-; the slave receives the 5V square wave signal with the first connection terminal CS-SYN+ and the second connection terminal CS-SYN- through the external port, which is converted into a 3.3V square wave signal with the same frequency and amplitude through the signal receiving circuit of this analog circuit, and then transmitted to the slave micro-control unit through the output terminal RXD and 3.3V_GND of the signal receiving circuit. Therefore, this circuit has two working modes:

[0025] First, the sending mode

[0026] The first state: the input terminal TXD of the signal sending circuit outputs a 3.3V high-level signal, the second primary light-emitting diode in the second optocoupler OPT2 does not meet the conduction condition, and the emitter and collector of the second secondary photosensitive transistor are in a high-impedance state, causing the second transistor Q2 to be cut off. At this time, the first primary light-emitting diode of the first optocoupler OPT1 is in forward bias conduction, and the voltage between the two ends after conduction is the diode conduction voltage drop. The collector and emitter of the first secondary photosensitive transistor are in a low-impedance state, and the output terminal RXD of the signal receiving circuit is pulled to a low level by the second resistor R2 and the first optocoupler OPT1, and the level is about the Vce saturation voltage drop. At the same time, the first transistor Q1 is in forward bias conduction, and the voltage drop is approximately the Vce saturation voltage drop. According to the voltage division principle, a high-level voltage of nearly 5V can be obtained between the first connection terminal CS-SYN+ and the second connection terminal CS-SYN-.

[0027] The second state: the input end of the signal transmission circuit outputs a 0V low-level signal, the second primary light-emitting diode in the second optical coupler OPT2 reaches the conduction condition, the emitter and collector of the second secondary phototransistor are in a low-resistance state, causing the second transistor Q2 to be turned on, and the first connection end CS-SYN+ and the second connection end CS-SYN- are at a low level, and the level is approximately the Vce saturation voltage drop. At this time, the first primary light-emitting diode of the first optical coupler OPT1 is in forward bias conduction, and the voltage at both ends after conduction is the diode conduction voltage drop, the collector and emitter of the first secondary phototransistor are in a low-resistance state, and the output end RXD of the signal receiving circuit is pulled to a low level by the second resistor R2 and the first optical coupler OPT1, and the level is approximately the Vce saturation voltage drop.

[0028] Therefore, by sending a low frequency 3.3V amplitude square wave signal at the input end of the signal sending circuit, a same frequency positive logic 5V amplitude square wave can be obtained between the first connection end CS-SYN+ and the second connection end CS-SYN-.

[0029] Second, receiving mode

[0030] When the first connection terminal CS-SYN+ and the second connection terminal CS-SYN- receive an external 5V square wave low-frequency signal, the signal sent by the host micro-control unit to the input terminal TXD of the signal sending circuit is normally low level. At this time, the second primary side light-emitting diode of the second optocoupler OPT2 does not emit light, so that the second secondary side photosensitive transistor is cut off to a high impedance state.

[0031] The first state: when the first connection terminal CS-SYN+ and the second connection terminal CS-SYN- receive a 5V high level, since the power supply voltage is equal to the potential of the high level, the first transistor Q1 and the first primary light-emitting diode of the first optical coupler OPT1 are in a 0 voltage bias cut-off state, the collector and emitter of the first secondary photosensitive transistor of the first optical coupler OPT1 are in a high impedance state and are connected in series with R1 to obtain a voltage of about 3.3V, and the level of the output terminal RXD of the signal receiving circuit is also 3.3V. The signal receiving circuit receives an external 5V high level and outputs a high level of about 3.3V.

[0032] The second state: when the first connection terminal CS-SYN+ and the second connection terminal CS-SYN- receive a 0V low level, it is equivalent to the collector of the second transistor Q2 being connected to 5V_GND, the first transistor Q1 being forward biased and turned on, the collector and emitter voltage drop of the first transistor Q1 being the Vces saturation voltage drop, at which time the first primary side light emitting diode of the first optical coupler OPT1 is turned on and emits light due to the forward bias, and the collector and emitter voltage Vces of the first secondary side photosensitive transistor of the first optical coupler OPT1 is the saturation voltage drop. The signal receiving circuit receives an external 0V low level and outputs a low level of approximately the Vces saturation voltage drop.

[0033] Therefore, by inputting a low frequency 5V amplitude square wave signal at the first connection terminal CS-SYN+ and the second connection terminal CS-SYN-, a same frequency positive logic 3.3V amplitude square wave can be obtained at the output terminal RXD of the signal receiving circuit.

[0034] In summary, the host micro-control unit sends a synchronization signal through the input terminal TXD of the signal transmission circuit, and outputs it to the first connection terminal CS-SYN+ and the second connection terminal CS-SYN- port. The slave receives the synchronization signal from the first connection terminal CS-SYN+ and the second connection terminal CS-SYN- port, and after conversion, transmits it to the slave micro-control unit through the output terminal RXD of the signal receiving circuit.

[0035] The frequency synchronization signal circuit of the above-mentioned inverter wired parallel machine is used for mobile energy storage inverter output wired parallel machine or other inverter output wired parallel machine. The signal sending circuit and the signal receiving circuit realize the two-way transmission of the frequency synchronization signal, which can send the frequency synchronization signal and receive the frequency synchronization signal; at the same time, the sending end and the receiving end of the signal are isolated and processed by the photoelectric coupler, so that the circuit has good electrical insulation and anti-interference capabilities. This circuit is constructed by discrete components, which can realize the parallel machine of analog signals and reduce the circuit cost. The circuit structure of the utility model is simple, easy to implement, low cost, and easy to promote.

[0036] It should be noted that the present invention is not limited to the above-mentioned embodiments. According to the creative spirit of the present invention, those skilled in the art may also make other changes. These changes made according to the creative spirit of the present invention should be included in the scope of protection required by the present invention.

Claims

1. A frequency synchronization signal circuit for wired parallel inverters, used for sending and receiving frequency synchronization signals of two parallel inverters, wherein the two parallel inverters include a master and a slave, and characterized in that: It includes a signal sending circuit and a signal receiving circuit, the output end of the signal sending circuit and the input end of the signal receiving circuit are the same pair of connection ends, the pair of connection ends include a first connection end CS-SYN+ and a second connection end CS-SYN-, the first connection end CS-SYN+ and the second connection end CS-SYN- are connected to the slave synchronization signal end; the input end TXD of the signal sending circuit is connected to the output end of the host micro-control unit, and the output end RXD of the signal receiving circuit is connected to the input end of the slave micro-control unit, so that the frequency synchronization signal output by the host micro-control unit is transmitted to the slave synchronization signal end through the signal sending circuit, and then transmitted to the slave micro-control unit by the slave synchronization signal end, so as to realize the frequency synchronization between the slave and the host.

2. The frequency synchronization signal circuit for wired parallel inverter according to claim 1, characterized in that: The signal sending circuit includes a second optocoupler OPT2 and a ninth resistor R9, the second optocoupler OPT2 includes a second primary light-emitting diode and a second secondary photosensitive transistor, the cathode of the second primary light-emitting diode is the input terminal TXD of the signal sending circuit, and the anode of the second primary light-emitting diode is connected to a 3.3V power supply through the ninth resistor R9; the collector of the second secondary photosensitive transistor is connected to the first connection terminal CS-SYN+, and the emitter of the second secondary photosensitive transistor is connected to the second connection terminal CS-SYN- through the eighth resistor R8, and is also connected to the ground 5V_GND.

3. The frequency synchronization signal circuit for wired parallel inverter according to claim 2, characterized in that: A second transistor Q2 and a second capacitor C2 are also provided between the first connection terminal CS-SYN+ and the second connection terminal CS-SYN-, the base of the second transistor Q2 is connected to the emitter of the second secondary photosensitive transistor and the midpoint of the eighth resistor R8, and the two ends of the second capacitor C2 are respectively connected to the collector and emitter of the second transistor Q2, and are respectively connected to the first connection terminal CS-SYN+ and the second connection terminal CS-SYN-.

4. The frequency synchronization signal circuit for wired parallel inverter according to claim 2, characterized in that: The signal receiving circuit includes a first optocoupler OPT1, a first resistor R1, a first capacitor C1 and a second resistor R2. The first optocoupler OPT1 includes a first primary light-emitting diode and a first secondary photosensitive transistor. The collector of the first secondary photosensitive transistor is connected to a 3.3V power supply through the first resistor R1, and is connected to the output end RXD of the signal receiving circuit through the second resistor R2. The emitter of the first secondary photosensitive transistor is connected to the ground 3.3V_GND; the two ends of the first capacitor C1 are respectively connected to the collector and emitter of the first secondary photosensitive transistor.

5. The frequency synchronization signal circuit for wired parallel inverters according to claim 4, characterized in that: The anode of the first primary light-emitting diode is connected to a 5V power supply through a third resistor R3, the cathode of the first primary light-emitting diode is connected to the collector of the second secondary photosensitive transistor through a first transistor Q1 and a seventh resistor R7, the collector of the first transistor Q1 is connected to the cathode of the first primary light-emitting diode, and the emitter of the first transistor Q1 is connected to the first connection terminal CS-SYN+ through the seventh resistor R7.

6. The frequency synchronization signal circuit for wired parallel inverters according to claim 5, characterized in that: It also includes a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6 connected in series, wherein the two ends of the fourth resistor R4 are respectively connected to the anode and the cathode of the first primary light-emitting diode, the two ends of the fifth resistor R5 are respectively connected to the collector and the base of the first transistor Q1, and the two ends of the sixth resistor R6 are respectively connected to the base of the first transistor Q1 and the first connection terminal CS-SYN+.

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