Circuit board and electronic device
By setting vias of solder resist layer and conductive layer on the pad of the circuit board, the problems of poor volatility and blockage of solder paste caused by large pad area are solved, and the device is well dissipated and the connection stability is achieved, avoiding the risk of short circuit.
Patent Information
- Application Number
- CN202421065984.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-15
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2034-05-15
AI Technical Summary
In QFN and QFP packaging technologies, solder paste with large pad area is difficult to evaporate, resulting in poor connection between the chip and the circuit board, the solder paste flows into the vias and blocks the heat dissipation, and may cause short circuits of other devices.
A solder resist layer is arranged on the pad of the circuit board to divide multiple areas to be put on, and a via hole is opened on the solder resist layer. A conductive layer is provided on the inner wall of the via hole to form a solvent volatilization channel and a heat dissipation channel to prevent solder paste from flowing in through Holes to ensure the solder paste flows in the non-sprayed area.
It effectively avoids the problems of hollows and vias in the solder paste, ensures that the device operates normally under suitable temperature environments, and prevents short-circuiting of other devices.
Smart Images
Figure CN222302089U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of circuit boards, and in particular to a circuit board and an electronic device. Background Art
[0002] With the advancement of packaging technology, QFN packaging (Quad Flat No-leads Package) and QFP packaging (Quad Flat Package) have gradually developed. The chip obtained by this type of packaging technology will have a whole large pad in the middle. In order to facilitate the mounting of this type of chip on the circuit board, a whole large pad matching its area will be set on the circuit board. At the same time, considering the heat dissipation requirements, vias need to be opened in the pads on the circuit board for heat dissipation, and then the chip mounting is completed through soldering with solder paste.
[0003] In the process of chip mounting on circuit boards, solder paste needs to be sprayed on the surface of the pad first. On the one hand, because the solder paste surface is too large, the solvent contained in the solder paste is wrapped inside and difficult to volatilize, thus generating voids in the solder paste, resulting in poor soldering between the chip and the circuit board, affecting performance. On the other hand, the solder paste on the surface of the pad can easily flow into the via, blocking the via and affecting heat dissipation. Moreover, if the solder paste flows through the via to the back of the circuit board, it may cause a short circuit in other devices. Utility Model Content
[0004] The purpose of this application is to provide a circuit board and an electronic device to address the deficiencies in the above-mentioned prior art. By reasonably setting the pads on the circuit board, a solvent volatilization channel is constructed in the pads during the mounting process to help the solvent volatilize smoothly from the volatilization channel and avoid the formation of voids in the solder paste. On this basis, by reasonably utilizing the volatilization channel in the pads to set vias, the vias are located in the non-spraying area of the solder paste, avoiding the problem of via blockage caused by solder paste flowing into the vias, which helps to form a suitable temperature environment for the operation of the device, facilitates the normal performance of the device, and avoids the paste from passing through the vias to the back of the circuit board, which may cause short circuits in other devices.
[0005] To achieve the above objectives, the technical solutions adopted in this application are as follows:
[0006] In one aspect of the present application, a circuit board is provided, comprising a board body having a metal layer, a first soldering pad is arranged on the front side of the board body, a solder resist layer is arranged on the surface of the first soldering pad, the solder resist layer divides the surface of the first soldering pad into a plurality of areas to be tinned, and two adjacent areas to be tinned are isolated by the solder resist layer, a via hole is opened on the solder resist layer and is located on the board body and extends to the metal layer, a conductive layer is arranged on the inner wall of the via hole, and the first soldering pad is connected to the metal layer via the conductive layer.
[0007] Optionally, the ratio of the sum of the areas of the plurality of regions to be tinned to the area of the first soldering pad is greater than 1 / 2.
[0008] Optionally, the solder resist layer includes a plurality of vertical solder resist bars and horizontal solder resist bars that cross each other to form a grid, and the vertical solder resist bars and the horizontal solder resist bars expand outward at the intersection to form a solder resist portion, the via is located in the solder resist portion, and the opening area of the via is smaller than the area of the orthographic projection of the solder resist portion on the board.
[0009] Optionally, the width of the vertical solder resist strips and the horizontal solder resist strips is 4 mil to 8 mil.
[0010] Optionally, the via hole has a diameter of 6 mil to 10 mil.
[0011] Optionally, there are multiple via holes, and the distance between two adjacent via holes is greater than 1 mm.
[0012] Optionally, there are multiple vias, and some of the vias are distributed at the edge of the first pad.
[0013] Optionally, the vias correspond to non-hollow areas of the steel mesh.
[0014] Optionally, PIN pins distributed around the first pad are further provided on the front side of the circuit board.
[0015] Another aspect of an embodiment of the present application provides an electronic device, comprising a chip having a second solder pad and any of the above-mentioned circuit boards, wherein solder paste is coated on the area to be tinned of the circuit board, and the second solder pad of the chip is connected to the first solder pad on the circuit board via the solder paste.
[0016] The beneficial effects of this application include:
[0017] The present application provides a circuit board and an electronic device, including a plate body with a metal layer, a first solder pad is arranged on the front of the plate body, a solder mask is arranged on the surface of the first solder pad, the solder mask divides the surface of the first solder pad into a plurality of areas to be tinned, and two adjacent areas to be tinned are isolated by the solder mask, a via hole located in the plate body and extending to the metal layer is opened on the solder mask, a conductive layer is arranged on the inner wall of the via hole, and the first solder pad is connected to the metal layer through the conductive layer. By reasonably setting the solder pad on the circuit board, a solvent volatilization channel is constructed during the mounting process after spraying solder paste, which helps the solvent to volatilize smoothly from the volatilization channel, avoids the formation of voids in the solder paste, and thus affects the performance of the device. On this basis, by reasonably utilizing the volatilization channel in the solder pad to set the via hole, the via hole is located in the non-spraying area of the solder paste, and then the solder paste can be prevented from flowing into the via hole, resulting in poor heat dissipation caused by the blockage of the via hole and the problem of short circuit of other devices caused by the solder paste flowing to the back, which helps to form a suitable temperature environment for the operation of the device and facilitates the normal performance of the device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0019] Figure 1 A schematic diagram of the structure of a circuit board provided in an embodiment of the present application;
[0020] Figure 2 A schematic diagram of the structure of another circuit board provided in an embodiment of the present application.
[0021] Icon: 10-circuit board; 100-board body; 110-PIN foot; 200-first pad; 210-solder mask layer; 211-vertical solder mask bar; 212-horizontal solder mask bar; 213-solder mask part; 220-area to be tinned; 230-via. DETAILED DESCRIPTION
[0022] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0023] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. It should be noted that, in the absence of conflict, the various features in the embodiments of the present application can be combined with each other, and the combined embodiments are still within the scope of protection of the present application.
[0024] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0025] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0026] In addition, the terms "horizontal", "vertical" and the like do not mean that the components are required to be absolutely horizontal or suspended, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0027] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0028] Based on the characteristics of QFN (Quad Flat No-leads Package) and QFP (Quad Flat Package), a large pad is set on the chip and the circuit board. At the same time, a large number of vias need to be evenly opened in the pad on the circuit board to facilitate heat dissipation through the vias.
[0029] However, there are the following problems in the process of tinning the pad surface of the circuit board:
[0030] First, due to the large area of the pad, after the solder paste is sprayed on the entire surface of the pad, the solder paste surface will be larger. In addition, the solder paste contains a large amount of solvent, which is still wrapped by the solder paste after subsequent welding and cooling, making it difficult to achieve effective volatilization, which easily produces voids in the solder paste, resulting in poor soldering between the chip and the circuit board, which not only easily weakens the connection strength between the two, but also affects the electrical performance of both.
[0031] Secondly, since the pad area is large and multiple vias are opened in the pad for heat dissipation, after the solder paste is sprayed on the entire surface of the pad, the solder paste can easily flow into the vias, causing the vias to be blocked, making it difficult for the heat generated by the chip to be effectively conducted, easily causing the temperature to be too high, affecting the performance of the device and even reducing the service life of the device.
[0032] Third, the solder paste may flow through the vias to the back of the circuit board, causing the parts to short-circuit, affecting electrical performance and preventing them from working properly.
[0033] In view of the above problems existing in the prior art, one aspect of the embodiments of the present application provides a circuit board, which constructs a solvent volatilization channel in the mounting process after spraying solder paste by reasonably setting the solder pads on the circuit board, and helps the solvent to volatilize smoothly from the volatilization channel, so as to avoid the formation of voids in the solder paste, thereby affecting the performance of the device. On this basis, by reasonably utilizing the volatilization channel in the solder pad to set the via hole, the via hole is located in the non-spraying area of the solder paste, thereby avoiding the solder paste flowing into the via hole, resulting in poor heat dissipation caused by the blockage of the via hole, and the solder paste flowing to the back side causing other devices to short-circuit, which helps to form a suitable temperature environment for the operation of the device and facilitates the normal performance of the device.
[0034] It should be understood that the circuit board in the present application can be used to mount chips in QFN packages (Quad Flat No-leads Package) and chips in QFP packages (Quad Flat Package). The present application does not impose any specific restrictions on this and can be reasonably configured according to actual needs.
[0035] In order to facilitate a full understanding of the technical solution of the present application, the embodiments of the present application will be described below in conjunction with the accompanying drawings.
[0036] Figure 1 This is a schematic diagram of the structure of a circuit board provided in an embodiment of the present application. Figure 1 The circuit board 10 includes a board body 100, and the board body 100 has a metal layer (not shown in the figure). A first pad 200 is arranged on the front of the board body 100, wherein the metal layer can be a material with good electrical conductivity, such as copper, and the first pad 200 can be used for welding with a larger pad in the middle of the chip. It should be known that the metal layer in the present application can be located on the back of the board body or inside the board body, for example, the metal layer is located inside the board body: the board body is a multi-layer board, and the metal layer can be located between any two adjacent layers in the multi-layer board. The metal layer can be used as a large area of ground or power supply in the circuit board, and the present application does not limit it. The front and back sides in the present application are only used to distinguish the surfaces on the opposite sides of the board body 100, and should not be understood as indications or hints of other specific orientations.
[0037] Please continue to refer to Figure 1 A solder resist layer 210 is disposed on the surface of the first pad 200, wherein the solder resist layer 210 does not completely cover the surface of the first pad 200, but has both covered areas and uncovered areas. The area on the surface of the first pad 200 covered by the solder resist layer 210 is blocked during subsequent tinning, so there is no solder paste, while the area on the surface of the first pad 200 not covered by the solder resist layer 210 is exposed, so the exposed area will be sprayed with solder paste during subsequent tinning.
[0038] like Figure 1 As shown, the solder resist layer 210 divides the surface of the first pad 200 into a plurality of to-be-tinned areas 220, wherein the to-be-tinned areas 220 are areas not covered by the solder resist layer 210. Therefore, during subsequent tinning, the solder paste will be located in the to-be-tinned areas 220. The solder resist layer 210 can separate adjacent to-be-tinned areas 220, that is, each to-be-tinned area 220 is independent of each other, for example Figure 1 In the figure, the area to be tinned 220 in the upper left corner is separated from the area to be tinned 220 on the right by the solder resist layer 210, and the two areas do not contact each other. The area to be tinned 220 in the upper left corner is also separated from the area to be tinned 220 below it by the solder resist layer 210, and the two areas do not contact each other. Similarly, the area to be tinned 220 in the upper left corner is separated from the area to be tinned 220 in the lower right corner by the solder resist layer 210, and the two areas do not contact each other. Similarly, any area to be tinned 220 is separated from the area to be tinned 220 around it by the solder resist layer 210.
[0039] In this way, after the subsequent tinning, since there is no solder paste in the area where the solder resist layer 210 is located, there is solder paste only in each area 220 to be tinned, and because the adjacent areas 220 to be tinned are isolated by the solder resist layer 210, the solder pastes in the adjacent areas 220 to be tinned are also separated from each other by the solder resist layer 210, that is, the solder pastes in different areas 220 to be tinned do not contact each other. In this way, the large piece of solder paste originally covering the entire surface of the first solder pad 200 can be divided into multiple small pieces by the solder resist layer 210, and each small piece corresponds to In an area 220 to be tinned, adjacent small pieces of solder paste are separated and do not touch each other, and the solder resist layer 210 is not covered by the solder paste. In this way, the solder resist layer 210 located between adjacent areas 220 to be tinned can serve as a volatilization channel between adjacent small pieces of solder paste, and the volatilization channel extends from the edge of the first solder pad 200 into the middle of the first solder pad 200. In this way, the solvent contained in the solder paste near the middle area of the first solder pad 200 can be smoothly volatilized with the help of the volatilization channel beside it, thereby alleviating the phenomenon of voids in the solder paste and improving the performance of the device.
[0040] After tinning is completed, the chip can be mounted on the circuit board 10, for example, a whole large pad (called the second pad) in the middle of the chip is aligned with the first pad 200 on the circuit board 10, and the second pad is in contact with each small piece of solder paste on the surface of the first pad 200, and a reliable connection between the first pad 200 and the second pad is completed by using a process such as reflow soldering. According to the above, during the mounting process, the small pieces of solder paste located in each area 220 to be tinned can smoothly volatilize the solvent contained therein with the help of the volatilization channel next to it, thereby alleviating the phenomenon of voids in the solder paste.
[0041] When spraying solder paste on the surface of the first pad 200, a steel mesh can be used. The steel mesh has a hollow area (hollow area) and a non-hollow area (i.e., a solid area). The steel mesh is stacked on the front of the board 100. The area to be tinned 220 in this application corresponds to the hollow area of the steel mesh and is exposed. The solder resist layer 210 in this application corresponds to the non-hollow area in the steel mesh. Therefore, the solder resist layer 210 is covered by the non-hollow area of the steel mesh. In this way, when spraying solder paste, the area to be tinned 220 is coated with solder paste, and there is no solder paste on the solder resist layer 210. After the steel mesh is removed, the aforementioned multiple small pieces of solder paste separated from each other are formed.
[0042] Please continue to refer to Figure 1 In order to effectively improve heat dissipation and prevent solder paste from flowing into the via 230, the via 230 can be opened in the area where the solder resist layer 210 is located. Figure 1 As shown, a via 230 is opened on the board in the area where the solder resist layer 210 is located, and the via 230 extends all the way to the metal layer. When the metal layer is located on the back side of the board, the via 230 penetrates all the way to the back side of the board 100 to facilitate connection to the metal layer on the back side of the board 100. Since the via 230 is opened in the area where the solder resist layer 210 is located, combined with the above, it can be known that when spraying solder paste on the surface of the first pad 200, a steel mesh will be used. When the steel mesh is stacked on the front of the board 100, the solder resist layer 210 in the present application corresponds to the non-hollow area in the steel mesh, so the solder resist layer 210 is covered by the non-hollow area of the steel mesh. Similarly, the via 230 located in the area where the solder resist layer 210 is located will also be covered by the non-hollow area of the steel mesh. In this way, when spraying solder paste, solder paste is coated in the tinning area 220, and there is no solder paste on the solder resist layer 210. Of course, the problem of solder paste flowing into the via 230 can be effectively avoided, that is, it will not affect the normal spraying of solder paste, and it can also avoid solder paste flowing into the via 230, causing the via 230 to be blocked, resulting in poor heat dissipation and solder paste flowing to the back side causing other devices to short-circuit.
[0043] In order to achieve good heat dissipation, a conductive layer is provided on the inner wall of the via 230, and the first soldering pad 200 can be connected to the metal layer through the conductive layer. For example, the first soldering pad 200 can be connected to the metal layer on the back of the board 100 through the conductive layer. In this way, the heat generated on the front side of the board 100 can be quickly conducted to the metal layer on the back side of the board 100 through the hole 230 and the conductive layer. The metal layer with a larger area on the back side of the board 100 can be used to quickly dissipate heat, which helps to form a suitable temperature environment for the operation of the device and facilitates the normal performance of the device.
[0044] Optionally, the first pad 200 may be a ground pad, which may be grounded through the via 230, the conductive layer in the via 230, and the metal layer, thereby effectively ensuring the grounding performance of the device.
[0045] Optionally, the ratio of the sum of the areas of the plurality of tinning regions 220 to the area of the first soldering pad 200 is greater than 1 / 2. In other words, Figure 1 As shown, the total area of all the areas to be tinned 220 adds up to more than 50% of the area of the first pad 200, such as 55%, 60%, 65%, 70%, 75%, 80%, etc., so that the solder paste coating area of the first pad 200 can reach more than 50%, which helps to achieve a tinning rate of more than 50% for the first pad 200, and effectively avoids poor tinning between the chip and the circuit board 10, which easily leads to weak connection strength between the two and low conductivity between the two.
[0046] Based on this, when setting the solder resist layer 210, the parameters such as the width, length, and quantity of the solder resist layer 210 should be reasonably set so that most of the area of the first pad 200 can still be smoothly coated with solder paste, thereby alleviating the problem of poor soldering between the chip and the circuit board 10 while also taking into account the electrical performance between the chip and the circuit board 10.
[0047] Optionally, in order to improve the uniformity of tinning at various positions of the first soldering pad 200, as Figure 1 As shown, the multiple tinning areas 220 separated by the solder resist layer 210 can be evenly distributed on the surface of the first pad 200, so that the distribution of the solder resist layer 210 is relatively uniform, and the solvent volatilization at each position can be relatively consistent. Avoid the phenomenon that the solder resist layer 210 is densely distributed in some positions and sparsely distributed in some positions, resulting in inconsistent solvent volatilization at different positions. At the same time, the multiple tinning areas 220 are evenly distributed on the surface of the first pad 200, which can also make the first pad 200 have good connection strength at each position.
[0048] Optionally, for ease of preparation, such as Figure 1 As shown, the shape of the first pad 200 may be rectangular, such as a rectangle or a square.
[0049] Alternatively, if Figure 1 As shown, for better division, the shape of each area to be tinned 220 can be approximately rectangular, such as approximately a rectangle or a square.
[0050] Optionally, the areas of all the regions to be tinned 220 may be equal or different.
[0051] Alternatively, if Figure 1 As shown, in order to better divide the multiple areas 220 to be tinned, the solder resist layer 210 can be distributed in a grid shape on the surface of the first pad 200.
[0052] Specifically, Figure 1 As shown, the solder resist layer 210 includes a plurality of vertical solder resist strips 211 and a plurality of horizontal solder resist strips 212. The vertical solder resist strips 211 and the horizontal solder resist strips 212 intersect each other to present a grid shape, and at least part of the vias 230 may be located at the intersection of the vertical solder resist strips 211 and the horizontal solder resist strips 212. For example Figure 1 In the figure, the solder resist layer 210 includes 3 solder resist vertical strips 211 and 3 solder resist horizontal strips 212. The 3 solder resist vertical strips 211 are arranged in sequence in the horizontal direction, and the 3 solder resist horizontal strips 212 are arranged in sequence in the vertical direction. The 3 solder resist vertical strips 211 and the 3 solder resist horizontal strips 212 form a total of 9 intersections. Thus, the first solder pad 200 is divided into 16 tinning areas 220. After subsequent tinning, each tinning area 220 is coated with solder paste. A via 230 can be provided at each intersection.
[0053] Optionally, taking into account good heat dissipation performance, the via 230 should be maintained at a certain size, but the width of the vertical solder resist bar 211 and the horizontal solder resist bar 212 should not be too large, otherwise it will easily affect the tin eating rate of the first solder pad 200. Therefore, the aperture of the via 230 arranged at the intersection of the vertical solder resist bar 211 and the horizontal solder resist bar 212 can be larger than the width of the vertical solder resist bar 211, and the aperture of the via 230 arranged at the intersection of the vertical solder resist bar 211 and the horizontal solder resist bar 212 can also be larger than the width of the horizontal solder resist bar 212. In this way, it is possible to avoid the width of the vertical solder resist bar 211 and the horizontal solder resist bar 212 being too wide, and at the same time, it is also possible to make the via 230 have a suitable opening area.
[0054] In order to balance the size of the solder resist layer 210 and the aperture of the via hole 230, as shown in FIG. Figure 1As shown, the solder resist area can be expanded outward to form a solder resist portion 213 at the intersection of the vertical solder resist strip 211 and the horizontal solder resist strip 212, that is, the solder resist portion 213 provides an area sufficient to distribute the vias 230 by expanding outward at the intersection of the vertical solder resist strip 211 and the horizontal solder resist strip 212, and then the vias 230 are opened in the solder resist portion 213. Of course, the opening area of the via 230 is smaller than the area of the positive projection of the solder resist portion 213 on the board 100, so that the non-hollow area of the steel mesh can cover the solder resist portion 213 while also covering the vias 230 distributed therein.
[0055] Optionally, in order to make the width of the vertical solder resist strips 211 and the horizontal solder resist strips 212 be in an appropriate range, the width of the vertical solder resist strips 211 and the horizontal solder resist strips 212 can be set to 4 mil to 8 mil, such as 4 mil, 5 mil, 6 mil, 7 mil, 8 mil, etc.
[0056] Optionally, in order to make the aperture of the via hole 230 within an appropriate range to ensure heat dissipation performance, the aperture of the via hole 230 may be 6 mil to 10 mil, such as 6 mil, 7 mil, 8 mil, 9 mil, 10 mil, etc.
[0057] Alternatively, if Figure 1 As shown, there are multiple via holes 230 , and the distance between two adjacent via holes 230 is greater than 1 mm.
[0058] Alternatively, if Figure 1 As shown, there are multiple via holes 230 , and some of the via holes 230 are distributed at the edge of the first pad 200 , so as to further improve the heat dissipation performance.
[0059] Alternatively, if Figure 1 As shown, a solder resist area may also be provided at the corner of the first pad 200, and a via 230 may be provided in the solder resist area to further improve the heat dissipation performance.
[0060] Alternatively, if Figure 2 As shown, PIN pins 110 distributed around the first pads 200 are also provided on the front side of the circuit board 10 , and the PIN pins 110 can be conveniently connected to the pins or pads of the chip.
[0061] On the other hand, an electronic device is provided, including a chip with a second solder pad and any of the above-mentioned circuit boards 10, wherein the area 220 to be tinned of the circuit board 10 is coated with solder paste, and the second solder pad of the chip is connected to the first solder pad 200 on the circuit board 10 via the solder paste. By reasonably setting the solder pads on the circuit board 10, a solvent volatilization channel is constructed during the mounting process after the solder paste is sprayed, which helps the solvent to volatilize smoothly from the volatilization channel, thereby avoiding the formation of voids in the solder paste, thereby affecting the performance of the device. On this basis, by reasonably utilizing the volatilization channel in the solder pad to set the via 230, the via 230 is located in the non-spraying area of the solder paste, thereby avoiding the solder paste from flowing into the via 230, resulting in poor heat dissipation caused by the blockage of the via 230, and the solder paste flowing to the back to cause other devices to short-circuit, which helps to form a suitable temperature environment for the operation of the device and facilitates the normal performance of the device.
[0062] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A circuit board, characterized in that: It includes a board body with a metal layer, a first soldering pad is arranged on the front side of the board body, a solder resist layer is arranged on the surface of the first soldering pad, the solder resist layer divides the surface of the first soldering pad into a plurality of areas to be tinned, and two adjacent areas to be tinned are isolated by the solder resist layer, a via hole is opened on the solder resist layer, which is located on the board body and extends to the metal layer, a conductive layer is arranged on the inner wall of the via hole, and the first soldering pad is connected to the metal layer via the conductive layer.
2. The circuit board according to claim 1, characterized in that The ratio of the sum of the areas of the plurality of regions to be tinned to the area of the first soldering pad is greater than 1 / 2.
3. The circuit board according to claim 1, characterized in that: The solder resist layer includes a plurality of vertical solder resist bars and horizontal solder resist bars that cross each other to form a grid, and a solder resist portion is formed at the intersection of the vertical solder resist bars and the horizontal solder resist bars. The via hole is located in the solder resist portion, and the opening area of the via hole is smaller than the area of the positive projection of the solder resist portion on the board.
4. The circuit board according to claim 3, characterized in that: The width of the vertical solder resist strips and the horizontal solder resist strips is 4 mil to 8 mil.
5. The circuit board according to any one of claims 1 to 4, characterized in that: The via hole has a diameter of 6 mil to 10 mil.
6. The circuit board according to any one of claims 1 to 4, characterized in that: There are multiple via holes, and the distance between two adjacent via holes is greater than 1 mm.
7. The circuit board according to any one of claims 1 to 4, characterized in that: There are multiple via holes, and some of the via holes are distributed at the edge of the first pad.
8. The circuit board according to any one of claims 1 to 4, characterized in that: The via holes correspond to the non-hollowed-out areas of the steel mesh.
9. The circuit board according to any one of claims 1 to 4, characterized in that: PIN pins distributed around the first pad are also arranged on the front side of the circuit board.
10. An electronic device, characterized in that: It comprises a chip having a second solder pad and a circuit board as claimed in any one of claims 1 to 9, wherein solder paste is coated on the area to be tinned on the circuit board, and the second solder pad of the chip is connected to the first solder pad on the circuit board via the solder paste.