Laminated packaging structure

Abstract

The utility model discloses a laminated packaging structure, which relates to the technical field of semiconductor packaging, and comprises a storage chip, a storage substrate, a logic chip and a logic substrate, the storage chip is adhered on the storage substrate through an adhesive film, the storage chip is packaged on the storage substrate through plastic packaging resin, and the storage chip is electrically connected with the storage substrate; the logic chip is inversely arranged on the logic substrate through underfill, and the logic chip is electrically connected with the logic substrate; according to the scheme, the storage chip, the storage substrate, the logic chip and the logic substrate are arranged in a layered mode, a longitudinal double-layer structure of a top packaging structure and a bottom packaging structure is formed, the area of the substrate is saved, the substrate can have a larger longitudinal space, and therefore packaging of more layers is allowed; the memory device of the top packaging structure and the logic device of the bottom packaging structure are connected through the electric appliance, so that a higher data transmission rate is realized, and high-speed interconnection between the logic device and the memory device can be dealt with.

Description

Technical Field

[0001] The utility model relates to a stacked packaging structure and belongs to the technical field of semiconductor packaging. Background Art

[0002] The existing chip packaging structure usually packages the logic chip and the memory chip separately in the packaging factory, and then welds the two types of chips on the PCB board in the terminal factory. This packaging structure requires a relatively large plane space due to flat welding on the PCB, and is difficult to be used in space-limited devices such as mobile phones and wearables. In addition, the signal transmission path is longer, which limits the electrical performance of the chip. Therefore, a new solution is needed to solve this problem. Utility Model Content

[0003] The utility model aims to provide a stacked packaging structure in order to overcome the deficiencies of the prior art.

[0004] To achieve the above-mentioned purpose, the technical solution adopted by the utility model is: a stacked packaging structure, comprising a storage chip, a storage substrate, a logic chip and a logic substrate, wherein the storage chip is bonded to the storage substrate by an adhesive film, the storage chip is encapsulated on the storage substrate by a plastic encapsulation resin, and the storage chip and the storage substrate are electrically connected; the logic chip is flip-chip mounted on the logic substrate by bottom filling glue, and the logic chip and the logic substrate are electrically connected; the storage substrate is vertically arranged directly above the logic substrate, a plurality of solder balls are arranged between the storage substrate and the logic substrate, and the storage substrate and the logic substrate are matched through the plurality of solder balls.

[0005] Preferably, the molding resin has a cavity, and the storage chip is located in the cavity, so that the surroundings and the top of the storage chip are in contact with the molding resin.

[0006] Preferably, the storage chip is electrically connected to the storage substrate via a gold wire.

[0007] Preferably, a plurality of copper bumps are evenly arranged on the logic substrate, the logic chip is arranged on the top surface of the plurality of copper bumps, and the logic chip is electrically connected to the logic substrate via the plurality of copper bumps.

[0008] Preferably, a plurality of solder balls are also arranged on the bottom surface of the logic substrate.

[0009] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:

[0010] A stacked packaging structure of the utility model solution forms a vertical double-layer structure of a top packaging structure and a bottom packaging structure by layering a storage chip, a storage substrate, a logic chip and a logic substrate, thereby saving substrate area and allowing the substrate to have a larger vertical space, thereby allowing more layers of packaging; the storage device of the top packaging structure and the logic device of the bottom packaging structure are electrically connected to achieve a faster data transmission rate, which can cope with high-speed interconnection between the logic device and the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The technical solution of the utility model is further described below in conjunction with the accompanying drawings:

[0012] Attached Figure 1 The utility model is a schematic structural diagram of a stacked packaging structure.

[0013] In the figure: 1. Plastic encapsulation resin; 2. Gold wire; 3. Storage chip; 4. Adhesive film; 5. Storage substrate; 6. Solder ball; 7. Logic substrate; 8. Underfill; 9. Copper bump; 10. Logic chip. DETAILED DESCRIPTION

[0014] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0015] As attached Figure 1 As shown, a stacked packaging structure described in the present invention includes a storage chip 3, a storage substrate 5, a logic chip 10 and a logic substrate 7.

[0016] The storage chip 3 is bonded to the storage substrate 5 through an adhesive film 4, the storage chip 3 is encapsulated on the storage substrate 5 through a plastic encapsulation resin 1, and the storage chip 3 and the storage substrate 5 are electrically connected, and the storage chip 3 is electrically connected to the storage substrate 5 through a gold wire 2 to form a top encapsulation structure.

[0017] The logic chip 10 is flipped on the logic substrate 7 through the bottom filling glue 8, and the logic chip 10 is electrically connected to the logic substrate 7, wherein a plurality of copper bumps 9 are evenly arranged on the logic substrate 7, and the logic chip 10 is arranged on the top surface of the plurality of copper bumps 9, and the logic chip 10 is electrically connected to the logic substrate 7 through the plurality of copper bumps 9 to form a bottom packaging structure.

[0018] The storage substrate 5 is vertically arranged directly above the logic substrate 7, and a plurality of solder balls 6 are arranged between the storage substrate 5 and the logic substrate 7. The storage substrate 5 and the logic substrate 7 cooperate with each other through the plurality of solder balls 6, and the top packaging structure and the bottom packaging structure are combined together through the plurality of solder balls 6, thereby forming a longitudinal double-layer packaging structure, which saves the substrate area and allows the substrate to have a larger longitudinal space, thereby allowing more layers of packaging; at the same time, the storage devices in the top packaging structure and the logic devices in the bottom packaging structure can be tested and replaced separately, thereby ensuring the yield rate; in addition, the storage devices in the top packaging structure and the logic devices in the bottom packaging structure are electrically connected, thereby achieving a faster data transmission rate, which can cope with high-speed interconnection between logic devices and storage devices.

[0019] The plastic encapsulation resin 1 has a cavity, and the storage chip 3 is located in the cavity, so that the surroundings and the top of the storage chip 3 are against the plastic encapsulation resin 1 to increase the heat dissipation efficiency of the storage chip 3 .

[0020] A plurality of solder balls 6 are also arranged on the bottom surface of the logic substrate 7 .

[0021] The processing process of the packaging structure of this scheme is as follows:

[0022] Step 1: Print solder paste on PCB pads;

[0023] Step 2: Pick up the bottom package device;

[0024] Step 3: Mount the bottom package device;

[0025] Step 4: Apply flux or solder paste to the top package device;

[0026] Step 5: Mount the top package device on the bottom package device;

[0027] Step 6: Reflow soldering;

[0028] Step 7: X-ray inspection;

[0029] Step 8: If there are defective BGAs, they will be reworked on the rework station. If there are no defective ones, bottom filling and curing will be carried out.

[0030] This solution can mix and match DRAM, Flash and microprocessor along the vertical direction of PCB; it provides design flexibility for chips from different manufacturers, and can simply mix and match them together to meet customer needs, reducing design complexity and cost.

[0031] The above are only specific application examples of the utility model and do not constitute any limitation to the protection scope of the utility model; any technical solutions formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the utility model.

Claims

1. A stacked package structure, characterized in that: The invention comprises a storage chip (3), a storage substrate (5), a logic chip (10) and a logic substrate (7); the storage chip (3) is bonded to the storage substrate (5) by means of an adhesive film (4); the storage chip (3) is encapsulated on the storage substrate (5) by means of a plastic encapsulation resin (1); and the storage chip (3) and the storage substrate (5) are electrically connected; the logic chip (10) is flip-mounted on the logic substrate (7) by means of an underfill (8); and the logic chip (10) and the logic substrate (7) are electrically connected; the storage substrate (5) is vertically arranged directly above the logic substrate (7); a plurality of solder balls (6) are arranged between the storage substrate (5) and the logic substrate (7); and the storage substrate (5) and the logic substrate (7) are matched by means of the plurality of solder balls (6).

2. The stacked package structure according to claim 1, characterized in that: The plastic encapsulation resin (1) has a cavity, and the storage chip (3) is located in the cavity, so that the surroundings and the top of the storage chip (3) are in contact with the plastic encapsulation resin (1).

3. The stacked package structure according to claim 1, characterized in that: The storage chip (3) is electrically connected to the storage substrate (5) via a gold wire (2).

4. The stacked package structure according to claim 1, characterized in that: A plurality of copper bumps (9) are evenly arranged on the logic substrate (7), the logic chip (10) is arranged on the top surface of the plurality of copper bumps (9), and the logic chip (10) is electrically connected to the logic substrate (7) via the plurality of copper bumps (9).

5. The stacked package structure according to claim 1, characterized in that: A plurality of solder balls (6) are also arranged on the bottom surface of the logic substrate (7).

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