High-capacity TSOP multi-flash memory chip stacking packaging structure
By introducing a chip stacking design using an adapter substrate and epoxy resin in the TSOP package structure, the capacity limitation of traditional TSOP packages is solved, achieving high-capacity storage and simplified manufacturing process.
Patent Information
- Application Number
- CN202420910727.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-29
- Publication Date
- 2025-01-07
- Estimated Expiration
- 2034-04-29
AI Technical Summary
Traditional TSOP packaging structures have limited storage capacity, and capacity cannot be increased by increasing package size or unbalanced stacking of molds, leading to increased process complexity.
Using a TSOP frame and adapter substrate structure, two stacks of eight chip units are superimposed on the frame and encapsulated using an adapter substrate and epoxy resin to achieve a stepped stacking and electrical connection of the chips, providing physical and electrical protection.
It achieves high-capacity storage while simplifying the packaging process and improving the stability and resistance to external interference of the packaging.
Smart Images
Figure CN222322087U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a high-capacity TSOP multi-flash memory chip stacking packaging structure, belonging to the technical field of semiconductor packaging. Background Art
[0002] With the advent of the information age, the demand for high-capacity products is becoming more and more common. Traditional products used in TSOP packaging mostly only stack 4 or 8 chips, and the storage capacity of the products is relatively limited. It can only be achieved by changing the packaging form or replacing higher-capacity chips. In addition, in TSOP packaging, the product appearance is relatively fixed, and it is impossible to increase the product capacity by increasing the package size. At the same time, most TSOPs use 1:2.25 unbalanced molds. If 16 chips are stacked at one time, it will cause serious imbalance, which is not conducive to process operations. Utility Model Content
[0003] The utility model aims to provide a high-capacity TSOP multi-flash memory chip stacking packaging structure in order to overcome the deficiencies of the prior art.
[0004] To achieve the above-mentioned purpose, the technical solution adopted by the utility model is: a high-capacity TSOP multi-flash memory chip stacking packaging structure, comprising a TSOP frame and two chip units; a transfer substrate is arranged on the lower side of the TSOP frame, the transfer substrate is fixed to the TSOP frame by tape glue, and the pins of the transfer substrate are interconnected with the TSOP frame by wire bonding; the two chip units are respectively connected and fixed on both sides of the bottom surface of the transfer substrate, and are symmetrically distributed along the length direction of the transfer substrate, and the two chip units are electrically connected to the transfer substrate.
[0005] Preferably, epoxy resin is provided on both upper and lower sides of the TSOP frame, and the epoxy resin is used to fill the gap between the TSOP frame and the adapter substrate and the two chip units, and to wrap the TSOP frame, the adapter substrate and the two chip units.
[0006] Preferably, each of the chip units comprises a plurality of chips, and the plurality of chips are stacked in sequence in a vertical direction in a stepped shape; the upper and lower adjacent chips are connected and fixed by a DAF film, and the uppermost chip is bonded to the transfer substrate by the DAF film.
[0007] Preferably, the upper and lower adjacent chips are electrically connected via bonding wires, and the uppermost chip is electrically connected to the transfer substrate via bonding wires.
[0008] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:
[0009] The utility model provides a high-capacity TSOP multi-flash memory chip stacking packaging structure. By adding a transfer substrate on the TSOP frame, two chip units consisting of 8 chips are stacked at one time, which can not only achieve high-capacity storage but also simplify the packaging process. At the same time, the TSOP frame, the transfer substrate and the two chip units are wrapped with epoxy resin to provide physical and electrical protection to prevent external interference. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The technical solution of the utility model is further described below in conjunction with the accompanying drawings:
[0011] Attached Figure 1 The utility model is a structural schematic diagram of a high-capacity TSOP multi-flash memory chip stacking packaging structure.
[0012] In the figure: 1. TSOP frame; 2. Tape; 3. Transfer substrate; 4. Chip; 5. Bonding wire; 6. Epoxy resin; 7. Pins. DETAILED DESCRIPTION
[0013] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0014] As attached Figure 1 As shown, a high-capacity TSOP multi-flash memory chip stacking packaging structure described in the utility model comprises a TSOP frame 1 and two chip units.
[0015] A transfer substrate 3 is provided on the lower side of the TSOP frame 1. The transfer substrate 3 is connected and fixed to the TSOP frame 1 through Tape 2. The pins 7 of the transfer substrate 3 are interconnected with the TSOP frame 1 by wire bonding. The two chip units are respectively connected and fixed on both sides of the bottom surface of the transfer substrate 3, and are symmetrically distributed along the length direction of the transfer substrate 3. The two chip units are electrically connected to the transfer substrate 3.
[0016] Each chip unit includes a plurality of chips 4 , which are stacked in sequence along the vertical direction in a stepped shape. In this embodiment, the number of chips 4 in each chip unit is 8.
[0017] The upper and lower adjacent chips 4 are connected and fixed by the DAF film, and the uppermost chip 4 is bonded to the transfer substrate 3 through the DAF film; the upper and lower adjacent chips 4 are electrically connected by bonding wires 5, and the uppermost chip 4 is electrically connected to the transfer substrate 3 through the bonding wires 5.
[0018] Epoxy resin 6 is provided on both the upper and lower sides of the TSOP frame 1. The epoxy resin 6 is used to fill the gap between the TSOP frame 1 and the adapter substrate 3 and the two chip units, and wrap the TSOP frame 1, the adapter substrate 3 and the two chip units to provide physical and electrical protection and prevent external interference.
[0019] The processing process of this scheme is as follows:
[0020] The first step is to cut the substrate into single particles using a blade.
[0021] The second step is wafer cutting. The chip is cut by mechanical grinding and other methods. The wafer is ground to the appropriate thickness, and the saw blade is used to cut the entire wafer into independent chips, ensuring that the warpage is controlled within a reasonable range.
[0022] The third step is to mount the transfer substrate and chip. Apply a layer of epoxy resin glue on the TSOP frame. The transfer substrate is tightly bonded to the tape glue on the frame through the epoxy resin glue. The upper chip can be bonded to the substrate through the DAF film.
[0023] The fourth step is wire bonding, using gold wire to physically connect the transfer substrate to the TSOP frame and the transfer substrate to the chip to achieve conduction.
[0024] The fifth step is to plastic-encapsulate the surface of the transfer substrate, using epoxy resin and various additives (curing agent, modifier, release agent, dye, flame retardant, etc.) to wrap all chips, transfer substrates and TSOP frames in a molten state to provide physical and electrical protection and prevent external interference.
[0025] The sixth step is to remove the gate. Use a suitable blade to remove the connection between the pins on the outermost circle of the TSOP frame.
[0026] The seventh step is to cut and shape the pins. Use a blade to cut and shape the strip TSOP frame.
[0027] The above are only specific application examples of the utility model and do not constitute any limitation to the protection scope of the utility model; any technical solutions formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the utility model.
Claims
1. A high-capacity TSOP multi-flash memory chip stacking package structure, characterized in that: The invention comprises a TSOP frame (1) and two chip units; a transfer substrate (3) is arranged on the lower side of the TSOP frame (1); the transfer substrate (3) is connected and fixed to the TSOP frame (1) by means of a tape adhesive (2); pins (7) of the transfer substrate (3) are interconnected with the TSOP frame (1) by wire bonding; the two chip units are respectively connected and fixed to two sides of the bottom surface of the transfer substrate (3) and are symmetrically distributed along the length direction of the transfer substrate (3); and the two chip units are both electrically connected to the transfer substrate (3).
2. The high-capacity TSOP multi-flash memory chip stacking package structure according to claim 1, characterized in that: Epoxy resin (6) is provided on both the upper and lower sides of the TSOP frame (1), and the epoxy resin (6) is used to fill the gap between the TSOP frame (1) and the adapter substrate (3) and the two chip units, and to wrap the TSOP frame (1), the adapter substrate (3) and the two chip units.
3. The high-capacity TSOP multi-flash memory chip stacking package structure according to claim 1, characterized in that: Each of the chip units comprises a plurality of chips (4), and the plurality of chips (4) are stacked in sequence in a vertical direction in a stepped shape; the upper and lower adjacent chips (4) are connected and fixed via a DAF film, and the uppermost chip (4) is bonded to the transfer substrate (3) via the DAF film.
4. The high-capacity TSOP multi-flash memory chip stacking package structure according to claim 3, characterized in that: The upper and lower adjacent chips (4) are electrically connected via bonding wires (5), and the uppermost chip (4) is electrically connected to the transfer substrate (3) via bonding wires (5).