On-state power taking circuit and intelligent single-live-wire switch
By designing an open-state power-up circuit in the intelligent single fire switch, using comparator, voltage sampling and delay switch circuits, the problems of load power-up failed and abnormal flicker are solved, and stable power-up and efficient energy replenishment of the load are achieved .
Patent Information
- Application Number
- CN202420447683.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-08
- Publication Date
- 2025-01-17
- Estimated Expiration
- 2034-03-08
AI Technical Summary
In the case of different load types or multiple loads connected in parallel, existing smart single fire switches are prone to failure in power-on startup or repeated restarts, and the power withdrawal capacity is weak, which cannot effectively solve the abnormal flickering problem of load switch module.
An open-state power-search circuit is designed, including a comparator circuit, a voltage sampling circuit and a delay switch circuit. The power is fetched through the first rectifier diode and the second rectifier diode, and the power state is switched through the delay switch circuit. After powering on, quickly obtain the power through mode A, switch to mode B to avoid abnormal flickering, and set the switch control circuit to replenish energy in a timely manner in high-power consumption scenarios.
It realizes successful power-on of low-power loads, avoids abnormal flickering of loads such as incandescent lamps and fluorescent lamps, improves power withdrawal capacity, ensures the stable voltage of energy storage capacitors, and avoids system instability or failure in startup.
Smart Images
Figure CN222366200U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of electric power equipment, in particular to an open-state power-taking circuit and an intelligent single-fire switch. Background Art
[0002] Intelligent transformation of existing lighting scenes is a scenario where intelligent single-fire switches are applicable. Since most of the lighting switches used in previous lighting scenes control the live wire of the load separately, if users want to carry out intelligent transformation, there is no ready-made neutral wire at the original switch position. For smart switches that require neutral and live wires to draw power, they are not applicable to scenarios with only single live wires.
[0003] The existing intelligent single-fire switch is internally provided with an on-state power-taking circuit and an off-state power-taking circuit. The on-state power-taking circuit takes power and stores it when the load switch is closed, and the off-state power-taking circuit takes power and stores it when the load switch is disconnected; the stored power is supplied to the control circuit for controlling the state of the load. Taking the single-fire switch that controls the lamp as an example, when the lamp is in the "on state", the mains voltage basically falls on both ends of the lamp, the on-state power-taking circuit and the switch circuit are connected in series in the lamp circuit, the switch circuit is in the energized state, and the voltage difference between the live wire and the lamp wire is close to zero. At this time, the off-state power-taking circuit fails, so a power-taking circuit is realized in the lamp series circuit through the on-state power-taking circuit to provide the necessary driving power for the switch.
[0004] However, due to different types of loads, such as excessively large equivalent impedance of the load, RC step-down type load, and fast and frequent control of load power on and off, it is easy to cause load power-on startup failure or repeated restarts. Or, when multiple loads are connected in parallel, and the power-drawing capacity of the intelligent single-fire switch is weak, power-on abnormalities are also likely to occur when the load switch module changes from the open state to the closed state in sequence. Utility Model Content
[0005] The purpose of the utility model is to overcome the defects of the prior art and provide an open-state power-taking circuit and an intelligent single-fire switch.
[0006] In order to achieve the above purpose, the utility model adopts the following technical solutions:
[0007] An open-state power-taking circuit includes a comparator circuit and a voltage sampling circuit, wherein the voltage sampling circuit includes: a first rectifier diode D1, a second rectifier diode D2, a voltage regulator diode D4, an energy storage capacitor, and a delay switch circuit;
[0008] The positive electrode of the first rectifier diode D1 is connected to the live wire of the main circuit, the negative electrode of the first rectifier diode D1 is connected to the positive power input terminal of the comparator circuit 110, the positive electrode of the second rectifier diode D2 is connected to the live wire of the main circuit, the negative electrode of the second rectifier diode D2 is connected to the negative electrode of the voltage regulator diode D4, and the positive electrode of the voltage regulator diode D4 is connected to the positive signal input terminal of the comparator circuit;
[0009] The positive terminal of the energy storage capacitor is connected to the reverse input terminal of the comparator circuit through a step-down circuit;
[0010] The output end of the comparator circuit is connected to the main circuit conduction switch 130, which is used to control the main circuit conduction switch;
[0011] The delay switch circuit is arranged between the cathode of the first rectifier diode D1 and the cathode of the second rectifier diode D2, and is used to switch the power supply state of the first rectifier diode D1 and the second rectifier diode D2.
[0012] Preferably, the delay switch circuit includes: a controllable switch Q2, a first resistor R1 and a first capacitor C1, the first end of the first resistor R1 is connected to the cathode of the first rectifier diode D1, the second end of the first resistor R1 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is grounded, the first end and the second end of the controllable switch Q2 are respectively connected to the cathode of the first rectifier diode D1 and the second rectifier diode D2, and the control end of the controllable switch is connected to the second end of the first resistor R1.
[0013] Preferably, the controllable switch Q2 is a PMOS tube.
[0014] Preferably, it also includes a switch control circuit for controlling the conduction of the controllable switch Q2 according to the pulse signal of the switch module.
[0015] Preferably, the switch control circuit includes: a third controllable switch Q3, a NAND gate circuit and a pulse signal input circuit, the first end of the third controllable switch Q3 is grounded, the second end of the third controllable switch Q3 is connected to the first end of the first capacitor C1, the control end of the third controllable switch Q3 is connected to the output end of the NAND gate circuit, and the input end of the NAND gate circuit 14 is connected to the pulse signal input circuit.
[0016] Preferably, the NAND gate circuit includes: a fourth controllable switch Q4, a second resistor R2 and a ninth resistor R9, the second end of the fourth controllable switch Q4 is connected to the control end of the third controllable switch Q3 as an output end, the first end of the fourth controllable switch Q4 is grounded, the control end of the fourth controllable switch Q4 is connected to the pulse signal input circuit, the second resistor R2 is connected to the second end of the fourth controllable switch Q4 and connected to the power supply end VCC, and the pulse signal input circuit is connected to the ninth resistor R9 and connected to the power supply end VCC.
[0017] Preferably, the pulse signal input circuit includes at least two input circuits, wherein each input circuit is provided with a rectifier diode D5, D6 in one direction.
[0018] Preferably, the energy storage capacitor includes: a second capacitor C2 and a third polarity capacitor C3 connected in parallel, the first end of the second capacitor C2 is connected to the negative electrode of the first rectifier diode D1, and the other end is grounded, the positive end of the third polarity capacitor C3 is connected to the negative electrode of the first rectifier diode D1, and the negative end is grounded, and the first end of the second capacitor C2 and the positive end of the third polarity capacitor C3 are connected to the reverse input end of the comparator circuit.
[0019] Preferably, the comparator circuit includes: a comparator U1, a sixth resistor R6, a fourth capacitor C4, a fourth resistor R4, a fifth resistor R5, a fifth controllable switch Q5, a seventh resistor R7, an eighth resistor R8, and a fifth capacitor C5. The forward input terminal of the comparator U1 is connected to the anode of the voltage zener diode D4. One end of the fourth capacitor C4 is connected to the anode of the voltage zener diode D4, and the other end is grounded. One end of the sixth resistor R6 is connected to the anode of the voltage zener diode D4, and the other end is grounded. One end of the fourth resistor R4 is connected to the output terminal of the comparator U1, and the other end is connected to the control terminal of the fifth controllable switch Q5. The first end of the fifth controllable switch Q5 is grounded, and the second end is connected in series with the seventh resistor R7 and the eighth resistor R8 in sequence. The second end of the eighth resistor R8 is connected to the reverse input terminal of the comparator U1, and the first end is connected to the power supply terminal VCC. The first end of the eighth resistor R8 is also connected to one end of the fifth capacitor C5, and the other end of the fifth capacitor C5 is grounded.
[0020] The utility model also provides an intelligent single-fire switch, comprising any of the above-mentioned open-state power-taking circuits.
[0021] In the embodiment of the utility model, the on-state power supply circuit draws power by setting a first rectifier diode and a second rectifier diode D2, and by setting a delay switch circuit to switch the power supply state of the first rectifier diode D1 and the second rectifier diode D2. After the first power-on, power is first drawn through the first rectifier diode D1, and after a preset delay time, power is drawn through the second rectifier diode D2, so that the on-state power supply circuit can be switched from mode A to mode B.
[0022] After the first power-on, the A-mode open-state power-taking circuit can quickly obtain sufficient power to ensure that small-power loads can also be powered on successfully. The working time of the A-mode open-state power-taking circuit depends on the time from the charging voltage of C1 by R1 to the cut-off voltage of the gate of Q2. This time can be set by R1 and C1 to limit the power-taking time of the A-mode open-state power-taking circuit to a reasonable range. After switching to B mode, abnormal flickering of loads such as incandescent lamps and fluorescent lamps can be avoided.
[0023] Furthermore, by setting a switch control circuit, if the open-state power-taking circuit is connected in parallel with multiple controllable loads, the energy consumed by each action of the load switch is too large, and energy needs to be replenished in time to maintain the voltage stability of the energy storage capacitor. The switch control circuit receives the RELAY_PWR_CTL signal to control the controllable switch Q2, so that the B mode is switched to the A mode to improve the power-taking capacity, thereby avoiding the excessive energy consumption in the high-power consumption scenario in the B mode, which causes the control circuit voltage to be unstable, resulting in system instability or abnormal operation (startup failure, restart) BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 This is a schematic diagram of the circuit function module of the utility model intelligent single fire switch;
[0025] Figure 2 It is the principle diagram of the open-state power-taking circuit of the utility model;
[0026] Figure 3 This is the equivalent circuit principle diagram of the utility model when the controllable switch Q2 of the open-state power-taking circuit is turned on;
[0027] Figure 4 It is an equivalent circuit principle diagram of the utility model when the controllable switch Q2 of the open-state power-taking circuit is cut off.
[0028] The reference numerals in the figures are as follows:
[0029] On-state power taking module 100, off-state power taking module 200, voltage stabilizing power supply module 300, communication module 400, switch driving module 500 and switch module 600;
[0030] The comparator circuit 110 , the voltage sampling circuit 120 , the energy storage capacitor 121 , the delay switch circuit 122 , the main circuit conduction switch 130 , the switch control circuit 140 , the NAND gate circuit 141 , and the pulse signal input circuit 142 . DETAILED DESCRIPTION
[0031] The following embodiments are given in conjunction with the accompanying drawings to further illustrate the specific implementation of the open-state power-taking circuit of the present utility model. The open-state power-taking circuit of the present utility model is not limited to the description of the following embodiments.
[0032] like Figure 1 The figure shows a functional module schematic diagram of the intelligent single-fire switch of this embodiment, which includes: an on-state power supply module 100, an off-state power supply module 200, a voltage-stabilized power supply module 300, a communication module 400, a switch drive module 500 and a switch module 600; wherein, the on-state power supply module 100 is used to perform power supply during the load opening process; the off-state power supply module 200 is used to perform power supply during the closing process; the voltage-stabilized power supply module 300 is used to stabilize the voltage of the electric energy obtained by the on-state power supply module 100 and the off-state power supply module 200; the switch drive module 100 and the switch module 200 are used to perform opening and closing operations on the load; the communication module 400 is used to control the switch drive module 500 and the switch module 600.
[0033] like Figure 2As shown, the specific circuit of the open-state power supply module (i.e., the open-state power supply circuit) includes: a comparator circuit 110 and a voltage sampling circuit 120. The voltage sampling circuit 120 includes: a first rectifier diode D1, a second rectifier diode D2, a voltage regulator diode D4, an energy storage capacitor 121, and a delay switch circuit 122; the positive electrode of the first rectifier diode D1 is connected to the live wire of the main circuit, the negative electrode of the first rectifier diode D1 is connected to the positive power supply input terminal of the comparator circuit 110, the positive electrode of the second rectifier diode D2 is connected to the live wire of the main circuit, the negative electrode of the second rectifier diode D2 is connected to the negative electrode of the voltage regulator diode D4, and the positive electrode of the voltage regulator diode D4 is connected to the positive signal input terminal of the comparator circuit 110. The positive terminal of the energy storage capacitor 121 is connected to the reverse input terminal of the comparator circuit 110 through a step-down circuit to provide a VCC voltage; the output terminal of the comparator circuit 110 is connected to the main circuit conduction switch 130, which is used to control the main circuit conduction switch 130; the delay switch circuit 122 is arranged between the cathode of the first rectifier diode D1 and the cathode of the second rectifier diode D2, and the delay switch circuit 122 is used to switch the power supply state of the first rectifier diode D1 and the second rectifier diode D2. It should be noted that the step-down circuit can be set as needed, for example, according to the different energy storage capacitors 121 selected, or set in other positions, for example, before the energy storage capacitor 121, or in the comparator circuit 110.
[0034] The delay switch circuit 122 is used to charge the energy storage capacitor 121 by first drawing power through the first rectifier diode D1 after the first power-on, and the delay switch circuit 122 switches to drawing power through the second rectifier diode D2 to charge the energy storage capacitor 121 after a preset delay time. In addition, as a preferred embodiment, the delay switch circuit 122 can also receive a control signal to switch from the state of drawing power from the second rectifier diode D2 back to the state of drawing power from the first rectifier diode D1, or switch from the state of drawing power from the first rectifier diode D1 to the state of drawing power from the second rectifier diode D2. For example, according to the power consumption of the load feedback, the state of drawing power from the second rectifier diode D2 is switched back to the state of drawing power from the first rectifier diode D1.
[0035] In this embodiment, the delay switch circuit 122 includes: a controllable switch Q2, a first resistor R1 and a first capacitor C1, the first end of the first resistor R1 is connected to the cathode of the first rectifier diode D1, the second end of the first resistor R1 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is grounded, the first end and the second end of the controllable switch Q2 are respectively connected to the cathodes of the first rectifier diode D1 and the second rectifier diode D2, and the control end of the controllable switch is connected to the second end of the first resistor R1. As a specific implementation of the controllable switch Q2, the controllable switch Q2 is a PMOS tube. When the controllable switch Q2 is not turned on, the AC power grid voltage charges the first capacitor C1 through the rectifier diode D1 and the first resistor R1. At the initial stage of charging, the source voltage of the controllable switch Q2 is much higher than the gate voltage, so that the controllable switch Q2 is in the on state, and the current passes through the first rectifier diode D1 and the controllable switch Q2 to reach the Zener diode D4. When the first capacitor C1 is charged to a gate voltage close to the source voltage, the controllable switch Q2 is turned off. At this time, the current passes through the second rectifier diode D2 to reach the Zener diode D.
[0036] In the embodiment, a switch control circuit 140 is further included, which is used to control the conduction of the controllable switch Q2 according to the pulse signal of the switch module, and can be used to switch from the power-taking state of the second rectifier diode D2 back to the power-taking state of the first rectifier diode D1.
[0037] As a specific implementation, the switch control circuit 140 includes: a third controllable switch Q3, a NAND gate circuit 141 and a pulse signal input circuit 142, the first end of the third controllable switch Q3 is grounded, the second end of the third controllable switch Q3 is connected to the first end of the first capacitor C1, the control end of the third controllable switch Q3 is connected to the output end of the NAND gate circuit 141, and the input end of the NAND gate circuit 141 is connected to the pulse signal input circuit 142.
[0038] As a specific implementation, the NAND gate circuit 141 includes: a fourth controllable switch Q4, a second resistor R2 and a ninth resistor R9, the second end of the fourth controllable switch Q4 is connected to the control end of the third controllable switch Q3 as an output end, the first end of the fourth controllable switch Q4 is grounded, the control end of the fourth controllable switch Q4 is connected to the pulse signal input circuit 142, the second resistor R2 is connected to the second end of the fourth controllable switch Q4 and connected to the power supply end VCC, and the pulse signal input circuit 142 is connected to the ninth resistor R9 and connected to the power supply end VCC.
[0039] In this embodiment, the pulse signal input circuit 142 includes at least two input circuits, wherein each input circuit is provided with a rectifier diode in one direction, for example, Figure 2 There are two input paths, the first path includes a fifth unidirectional diode D5, and the second path includes a sixth unidirectional diode D6.
[0040] In this embodiment, the energy storage capacitor 121 includes: a second capacitor C2 and a third polarity capacitor C3 connected in parallel, the first end of the second capacitor C2 is connected to the cathode of the first rectifier diode D1, and the other end is grounded, the positive end of the third polarity capacitor C3 is connected to the cathode of the first rectifier diode D1, and the negative end is grounded, and the first end of the second capacitor C2 and the positive end of the third polarity capacitor C3 are connected to the reverse input end of the comparator circuit 110. Of course, as other embodiments, the energy storage capacitor 121 may include one or more capacitors.
[0041] In this embodiment, the comparator circuit 110 includes: a comparator U1, a sixth resistor R6, a fourth capacitor C4, a fourth resistor R4, a fifth resistor R5, a fifth controllable switch Q5, a seventh resistor R7, an eighth resistor R8, and a fifth capacitor C5. A forward input terminal of the comparator U1 is connected to the anode of the voltage zener diode D4. One end of the fourth capacitor C4 is connected to the anode of the voltage zener diode D4 and the other end is grounded. One end of the sixth resistor R6 is connected to the anode of the voltage zener diode D4 and the other end is grounded. One end of the fourth resistor R4 is connected to the output terminal of the comparator U1 and the other end is connected to the control terminal of the fifth controllable switch Q5. A first end of the fifth controllable switch Q5 is grounded and a second end is connected in series with the seventh resistor R7 and the eighth resistor R8 in sequence. A second end of the eighth resistor R8 is connected to the reverse input terminal of the comparator U1 and a first end is connected to the power supply terminal VCC. A first end of the eighth resistor R8 is also connected to one end of the fifth capacitor C5 and the other end of the fifth capacitor C5 is grounded. In this embodiment, the fifth controllable switch may be an NPN transistor, and may also be a controllable switch of other forms.
[0042] In this embodiment, the main circuit conduction switch 130 is an NMOS transistor Q1 , the output end of the comparator U1 is connected to the gate of the NMOS transistor Q1 , and the output signal of the comparator U1 is used as a control signal to control the conduction / cutoff of the main circuit conduction switch 130 .
[0043] like Figure 3FIG. 1 is an equivalent circuit diagram when the controllable switch Q2 is turned on. When the controllable switch Q2 is turned on, the operating principle of the open-state power-taking circuit is as follows: the AC voltage of the power grid charges the energy storage capacitor 121, namely, the second capacitor C2 and the third polarity capacitor C3, after passing through the first rectifier diode D1. When the voltage on the energy storage capacitor 121 causes the voltage-stabilizing diode D3 to generate a stable reverse current, the fourth capacitor C4 is charged; as the voltage on the second capacitor C2 and the third polarity capacitor C3 rises, the VCC_OPEN voltage causes the VCC voltage to be established after passing through the step-down circuit. The VCC voltage is connected to the reverse input terminal of the comparator U1 through the eighth resistor R8. At this time, the voltage at the forward input terminal of the comparator U1 is less than the voltage at the reverse input terminal, and the output of the op amp is stable at a low level. As the voltage on the second capacitor C2 and the third polarity capacitor C3 of the energy storage capacitor rises, the voltage generated by the current passing through the sixth resistor R6 causes the fourth capacitor C 4 The voltage continues to rise and exceeds VCC. The voltage at the positive input terminal of the comparator U1 is greater than the voltage at the reverse input terminal, and the comparator U1 outputs a high level. The current flows through the third resistor R3. At this time, the NMOS tube Q1 of the main circuit is turned on, and the energy storage capacitor second capacitor C2 and the third polarity capacitor C3 finish charging. At the same time, the NPN transistor Q5 is turned on, so that the seventh resistor R7 is pulled down to GND (live wire), and the voltage at the reverse input terminal of the comparator U1 drops to a voltage approximately equal to VCC*R7 / (R7+R8). The voltage on the energy storage capacitor is discharged through the capacitor-related load (not shown in the figure), so that the voltage drops to a level that cannot break through the voltage-stabilizing diode D4. The charge of the fourth capacitor C4 is discharged through the sixth resistor R6. The voltage at the positive input terminal of the comparator U1 drops below VCC*R7 / (R7+R8), and the comparator U1 outputs a low level. The NMOS tube Q1 is turned off, and the next charging link is entered.
[0044] like Figure 4The figure shows an equivalent circuit diagram when the controllable switch Q2 is turned off. When the controllable switch Q2 is turned off, the operating principle of the open-state power-taking circuit is as follows: the AC grid voltage passes through the second rectifier diode D2 to the cathode of the voltage regulator tube D4. When the voltage causes the voltage regulator tube D4 to generate a stable reverse current, the fourth capacitor C4 starts to be charged; at the same time, the grid AC passes through the first rectifier diode D1 to charge the energy storage capacitor 121. As the voltage on the energy storage capacitor 121 rises, the VCC_OPEN voltage passes through the step-down circuit to establish the VCC voltage. The VCC voltage is connected to the reverse input terminal of the comparator U1 through the eighth resistor R8. At this time, the voltage at the forward input terminal of the comparator U1 is less than the voltage at the reverse input terminal. The comparator U1 outputs a low level, and the comparator U1 outputs a stable low level. When the grid voltage rises, the voltage regulator tube D4 generates a stable reverse current. The current passes through the sixth resistor R6 to generate The voltage charges the fourth capacitor C4, and the capacitor voltage continues to rise and the voltage exceeds VCC. The voltage at the positive input terminal of the comparator U1 is greater than the voltage at the reverse input terminal, and the comparator U1 outputs a high level; the current flows through the third resistor R3, and at this time, the NMOS tube Q1 of the main circuit is turned on, and the energy storage capacitor 121 ends charging; at the same time, the NPN transistor Q5 is turned on, so that the seventh resistor R7 is pulled down to GND, and the voltage at the reverse input terminal of the comparator U1 drops to approximately equal to the voltage of VCC*R7 / (R7+R8), and the voltage on the energy storage capacitor is discharged through the capacitor-related load (not shown in the figure), so that the voltage drops to a level that cannot break through the voltage-stabilizing diode D4, and the charge of the fourth capacitor C4 is discharged through the sixth resistor R6. The voltage at the positive input terminal of the comparator U1 drops below VCC*R7 / (R7+R8), the comparator U1 outputs a low level, the NMOS tube Q1 is turned off, and the next charging link is entered.
[0045] Figure 3 The mode shown (referred to as mode A) is that after the load switch is closed, the electric energy of half a voltage cycle of the AC grid is intercepted until the voltage of the energy storage capacitor reaches a preset value. The smaller the load power, the longer it takes to complete a charging cycle. Figure 4 Mode (denoted as Mode B) is that after the load switch is closed, a portion of the electric energy of a preset voltage value is intercepted from each half voltage cycle of the AC power grid, and the charging cycle is consistent with the voltage cycle of the AC power grid.
[0046] Among them, the A mode open-state power supply can effectively ensure the power-on success rate of small power loads during the open-state power supply process, but the charging circuit impedance of the energy storage capacitor in its open-state power supply circuit is relatively high, and the charging time is too long, which can easily cause the load to flicker abnormally in the open state, such as incandescent lamps, fluorescent lamps, etc.; the B mode open-state power supply can effectively avoid the abnormal flickering of the aforementioned incandescent lamps and fluorescent lamps, but its power supply capacity is weak. When the load power is small, the energy storage capacitor voltage cannot be replenished in time, and the voltage is too low, which can easily cause the load to fail to power on or restart repeatedly. In addition, if there are multiple loads in parallel when the B mode is open-state power supply, the switch modules of the loads will change from open to closed state in turn, which will also affect the energy storage capacitor charge and cause abnormal power-on.
[0047] In this embodiment, a delay switch circuit 122 is provided. When the circuit is powered on for the first time, the AC voltage of the power grid charges the energy storage capacitor 121 after passing through the rectifier diode D1. As the voltage rises, the source voltage of the PMOS tube Q2 (i.e., the controllable switch Q2) also rises. At the same time, the rectified voltage is applied to the first resistor R1 to charge the first capacitor C1. At the initial stage of charging, the source voltage of the PMOS tube Q2 is much higher than the gate voltage, so that the PMOS tube Q2 is turned on. At this time, the open-state power-taking circuit is equivalent to the A-mode open-state power-taking circuit ( Figure 3 Then, the rectified voltage continues to charge the first capacitor C1 so that the gate voltage of the PMOS tube Q2 rises to a value close to the source voltage of the PMOS tube Q2, and the PMOS tube Q2 is cut off. At this time, the open-state power-taking circuit is equivalent to the open-state power-taking circuit of mode B ( Figure 4 After the first power-on, the A-mode open-state power circuit can quickly obtain enough power to ensure that even small power loads can be powered on successfully. The working time of the A-mode open-state power circuit depends on the time from the charging voltage of C1 by R1 to the cut-off voltage of the gate of Q2. This time can be set by R1 and C1 to limit the power-taking time of the A-mode open-state power circuit to a reasonable range to avoid abnormal flickering of loads such as incandescent lamps and fluorescent lamps.
[0048] At the same time, by setting the switch control circuit 140, when the third controllable switch Q3 is turned on, the first capacitor C1 can be discharged, the source of the fourth controllable switch Q4 is connected to GND, the drain is connected to the gate of the third controllable switch Q3, and is pulled up to VCC through the second resistor R2; the multi-way switch module driving circuit pulse signal RELAY_PWR_CTL is input to the gate of the fourth controllable switch Q4; wherein, the multi-way switch module drives the power pulse signal to the gate of the fourth controllable switch Q4 for AND logic access, when the on / off state of any switch module in the multi-way changes, it indicates that the driving circuit corresponding to the switch module receives the pulse signal, and the pulse signal is simultaneously connected to The on-state power-taking circuit, that is, the driving circuit pulse signal RELAY_PWR_CTL, at this time RELAY_PWR_CTL is a low level; at this time, the ninth resistor R9 pulls up VCC to form a high level to turn on the unidirectional diode D5 or D6, and the voltage connected to the gate of the fourth controllable switch Q4 is a low level, and the fourth controllable switch Q4 is cut off; therefore, the voltage of the gate of the third controllable switch Q3 is high, the third controllable switch Q3 is turned on, the first capacitor C1 discharges to GND through the third controllable switch Q3, the voltage of the gate of the second controllable switch Q2 is reduced, and the second controllable switch Q2 is turned on. At this time, the on-state power-taking circuit is equivalent to the A-mode on-state power-taking circuit.
[0049] Based on the above, in this embodiment, after the open-state power supply mode A is converted to mode B, the open-state power supply circuit operates in mode B; if the open-state power supply circuit is connected in parallel with multiple controllable loads, the energy consumed by the load switch each time it operates is too large, and energy needs to be replenished in time to maintain the voltage stability on the energy storage capacitor. At this time, switching from mode B to mode A can improve the power supply capacity, thereby avoiding the high power consumption scenario in mode B, which causes excessive energy consumption in the control circuit voltage to be unstable, resulting in system instability or abnormal operation (startup failure, restart).
[0050] It should be noted that in the description of the present invention, the terms "upper", "lower", "left", "right", "inner", "outer", etc. indicate directions or positional relationships based on directions or positional relationships shown in the drawings, or directions or positional relationships that are usually placed when in use, and are only for the convenience of description, rather than indicating that the device or element referred to must have a specific direction, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish descriptions, and cannot be understood as indicating relative importance.
[0051] The above contents are further detailed descriptions of the present invention in combination with specific preferred implementations, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.
Claims
1. An open-state power supply circuit, comprising a comparator circuit (110) and a voltage sampling circuit (120), characterized in that: The voltage sampling circuit (120) comprises: a first rectifying diode D1, a second rectifying diode D2, a voltage stabilizing diode D4, an energy storage capacitor (121) and a time delay switch circuit (122); The positive electrode of the first rectifier diode D1 is connected to the live wire of the main circuit, the negative electrode of the first rectifier diode D1 is connected to the positive power input terminal of the comparator circuit (110), the positive electrode of the second rectifier diode D2 is connected to the live wire of the main circuit, the negative electrode of the second rectifier diode D2 is connected to the negative electrode of the voltage regulator diode D4, and the positive electrode of the voltage regulator diode D4 is connected to the positive signal input terminal of the comparator circuit (110); The positive terminal of the energy storage capacitor (121) is connected to the reverse input terminal of the comparator circuit (110); The output end of the comparator circuit (110) is connected to the main circuit conduction switch (130) and is used to control the main circuit conduction switch (130); The time-delay switch circuit (122) is provided between the cathode of the first rectifier diode D1 and the cathode of the second rectifier diode D2, and is used for switching the power supply states of the first rectifier diode D1 and the second rectifier diode D2.
2. The open-state power supply circuit according to claim 1, characterized in that: The time-delay switch circuit (122) comprises: a controllable switch Q2, a first resistor R1 and a first capacitor C1, wherein the first end of the first resistor R1 is connected to the cathode of the first rectifier diode D1, the second end of the first resistor R1 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is grounded, the first end and the second end of the controllable switch Q2 are respectively connected to the cathodes of the first rectifier diode D1 and the second rectifier diode D2, and the control end of the controllable switch is connected to the second end of the first resistor R1.
3. The open-state power supply circuit according to claim 2, characterized in that: The controllable switch Q2 is a PMOS tube.
4. The open-state power supply circuit according to claim 2, characterized in that: It also includes a switch control circuit (140) for controlling the conduction of the controllable switch Q2 according to the pulse signal of the switch module.
5. The open-state power supply circuit according to claim 4, characterized in that: The switch control circuit (140) comprises: a third controllable switch Q3, a NAND gate circuit (141) and a pulse signal input circuit (142); the first end of the third controllable switch Q3 is grounded, the second end of the third controllable switch Q3 is connected to the first end of the first capacitor C1, the control end of the third controllable switch Q3 is connected to the output end of the NAND gate circuit (141), and the input end of the NAND gate circuit (141) is connected to the pulse signal input circuit (142).
6. The open-state power supply circuit according to claim 5, characterized in that: The NAND gate circuit (141) comprises: a fourth controllable switch Q4, a second resistor R2 and a ninth resistor R9, the second end of the fourth controllable switch Q4 being connected to the control end of the third controllable switch Q3 as an output end, the first end of the fourth controllable switch Q4 being grounded, the control end of the fourth controllable switch Q4 being connected to the pulse signal input circuit (142), the second resistor R2 being connected to the second end of the fourth controllable switch Q4 and connected to a power supply end VCC, and the pulse signal input circuit (142) being connected to the ninth resistor R9 and connected to the power supply end VCC.
7. The open-state power supply circuit according to claim 6, characterized in that: The pulse signal input circuit (142) comprises at least two input circuits, wherein each input circuit is provided with a rectifying diode (D5, D6) in one direction.
8. The open-state power supply circuit according to claim 1, characterized in that: The energy storage capacitor (121) comprises: a second capacitor C2 and a third polarity capacitor C3 connected in parallel, wherein the first end of the second capacitor C2 is connected to the negative electrode of the first rectifier diode D1, and the other end is grounded, and the positive end of the third polarity capacitor C3 is connected to the negative electrode of the first rectifier diode D1, and the negative end is grounded; the first end of the second capacitor C2 and the positive end of the third polarity capacitor C3 are connected to the reverse input end of the comparator circuit (110).
9. The open-state power supply circuit according to claim 1, characterized in that: The comparator circuit (110) comprises: a comparator U1, a sixth resistor R6, a fourth capacitor C4, a fourth resistor R4, a fifth resistor R5, a fifth controllable switch Q5, a seventh resistor R7, an eighth resistor R8, and a fifth capacitor C5; a forward input terminal of the comparator U1 is connected to the positive electrode of the voltage stabilizing diode D4; one end of the fourth capacitor C4 is connected to the positive electrode of the voltage stabilizing diode D4 and the other end is grounded; one end of the sixth resistor R6 is connected to the positive electrode of the voltage stabilizing diode D4 and the other end is grounded; one end of the fourth resistor R4 is connected to the output terminal of the comparator U1 and the other end is connected to the control terminal of the fifth controllable switch Q5; a first end of the fifth controllable switch Q5 is grounded and a second end is connected in series with the seventh resistor R7 and the eighth resistor R8 in sequence; a second end of the eighth resistor R8 is connected to the reverse input terminal of the comparator U1 and a first end is connected to a power supply terminal VCC; a first end of the eighth resistor R8 is also connected to one end of the fifth capacitor C5 and the other end of the fifth capacitor C5 is grounded.
10. An intelligent single fire switch, characterized in that: It comprises an open-state power supply circuit as described in any one of claims 1-9.