Wafer structure
By designing a wafer structure with a detachable fixed structure, the problems of low NPW usage and high cost in the ALD process are solved, enabling multiple uses of NPW and improving usage efficiency.
Patent Information
- Application Number
- CN202421087563.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-17
- Publication Date
- 2025-01-21
- Estimated Expiration
- 2034-05-17
AI Technical Summary
The use rate of NPW in the ALD process is low and the cost is high, so it cannot be reused multiple times, resulting in waste of costs.
Design a wafer structure that includes stacked wafer sub-layers and a detachable fixed structure. By disassembling or removing the fixed structure, multiple wafer sub-layers can be separated and reused.
It increases the usage rate of NPW, reduces the usage cost, enables multiple uses of the wafer structure, and improves usage efficiency and convenience.
Smart Images
Figure CN222380566U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the field of semiconductor equipment, and in particular relates to a wafer structure. Background Art
[0002] Thin film deposition technology plays an important role in the entire semiconductor manufacturing process. As the size of integrated circuit components continues to shrink, traditional PVD (physical vapor deposition) and CVD (chemical vapor deposition) have certain limitations in terms of accuracy, uniformity, composition control, and complex structure preparation. In contrast, ALD (atomic layer deposition) technology is particularly capable of controlling film uniformity, and can deposit thin films with more uniform thickness in locations with large depth-to-width ratios such as deep trenches, providing key support for high-performance and high-reliability device manufacturing.
[0003] In the traditional PVD method, the NPW (non-productive wafer) usually needs to be deposited with a front layer before use to protect the NPW. After one use, the front layer is cleaned and recycled. When it is used again, the front layer is re-deposited to achieve multiple reuse of the NPW. In the ALD reaction, due to the thin deposition thickness, the ALD film cannot cover the unevenness of the front layer surface, resulting in the ALD film being greatly affected by the unevenness of the front layer and affecting the measurement, and unable to accurately reflect the characteristics of the film; the unevenness of the front layer will also interfere with the subsequent measurement of the ALD film. Therefore, the front layer is usually not deposited in the ALD process, and ALD deposition is performed directly on the NPW, and the NPW cannot be protected by the front layer; at the same time, the cleaning process of the NPW after the ALD process will also have a slight effect on the surface of the NPW. Therefore, the NPW in the ALD process cannot be recycled and reused. It will be scrapped or downgraded to a pseudo film after one use, resulting in a great waste of cost.
[0004] Therefore, a structure that can improve the NPW utilization rate of the ALD process and reduce the NPW use cost is urgently needed. It should be noted that the above introduction to the technical background is only for the convenience of a clear and complete description of the technical solution of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present application. Utility Model Content
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a non-productive wafer structure to solve the problems of low control wafer utilization rate and high use cost in the ALD process in the prior art.
[0006] In order to achieve the above purpose and other related purposes, the utility model provides the following technical solutions:
[0007] In the first aspect, the utility model provides a wafer structure, which includes: at least two stacked wafer sub-layers and a fixed structure; the fixed structure is at least arranged in the edge area between two adjacent wafer sub-layers, and is used to fix the two adjacent wafer sub-layers to be connected; the fixed structure between the two adjacent wafer sub-layers can be disassembled or removed, so as to separate the two adjacent wafer sub-layers.
[0008] Optionally, a card slot is provided at the edge of the wafer sub-layer; the first direction is a direction perpendicular to the wafer sub-layer, and the projections of the card slots of two adjacent layers of the wafer sub-layers in the first direction overlap, and the two card slots of two adjacent layers of the wafer sub-layers whose projections in the first direction overlap form a card slot group, and the two card slots in the card slot group are detachably engaged with the fixed structure.
[0009] Optionally, when there are adjacent wafer sub-layers above and below a layer of the wafer sub-layer, the slot group where the slots whose projections of the middle wafer sub-layer and the upper wafer sub-layer overlap in the first direction are located is the first slot group, and the slot group where the slots whose projections of the middle wafer sub-layer and the lower wafer sub-layer overlap in the first direction are located is the second slot group, and the projections of the first slot group and the second slot group in the first direction do not overlap.
[0010] Optionally, two adjacent wafer sub-layers have n groups of slot groups, where n is greater than or equal to 2.
[0011] Optionally, each group of the slot groups is symmetrically distributed relative to a diameter of the wafer sub-layer passing through a center point.
[0012] Optionally, the fixing structure is a detachable snap-on structure, which includes a male snap and a female snap; the male snap and the female snap can be detachably snap-on fixed through the slot groups of two adjacent layers of the wafer sub-layers, respectively, so that the positions of the two adjacent layers of the wafer sub-layers where the slot groups are located are fixed in a direction parallel to the wafer sub-layers.
[0013] Optionally, the fixing structure is a fixing rod, which passes through and engages in the two slots of the slot group, so that the positions of the two adjacent wafer sub-layers where the slot group is located are fixed in a direction parallel to the wafer sub-layers.
[0014] Optionally, the card slot is a C-shaped slot; or the card slot is a countersunk through hole, the countersunk through hole includes a countersunk hole part and a through hole part that are interconnected, and the countersunk hole part of each card slot is located above the through hole part.
[0015] Optionally, when the slot is a countersunk through hole and the fixed structure is engaged in the slot, a fixing structure is fixed to the fixed structure at a position corresponding to the countersunk hole part; the projection area of the fixing structure on the wafer sub-layer is larger than the projection area of the through hole part of the slot where the fixing structure is located on the wafer sub-layer and is less than or equal to the projection area of the countersunk hole part of the slot where the fixing structure is located on the wafer sub-layer; the projection of the fixing structure on the wafer sub-layer covers the projection of the through hole part of the slot where the fixing structure is located on the wafer sub-layer, and the fixing structure falls on the bottom step surface of the countersunk hole part.
[0016] Optionally, the length of the fixing structure in the first direction is less than or equal to the sum of the thicknesses of two wafer sub-layers where two slots of the slot group engaged by the fixing structure are located.
[0017] As described above, the wafer structure of the utility model has the following beneficial effects:
[0018] The utility model provides a wafer structure including stacked wafer sub-layers and a fixing structure, and utilizes the detachable or removable fixing structure to obtain multiple wafer sub-layers by slicing an NPW in the prior art, so that an NPW in the prior art can be used as an NPW multiple times, thereby reducing the use cost of the NPW and improving the use rate of the NPW at the same cost;
[0019] The utility model sets the wafer sub-layer and the fixed structure to be made of the same material, so that the wafer sub-layer will not be scratched by friction during the disassembly or removal of the fixed structure, thereby further reducing the use cost of the wafer sub-layer;
[0020] The utility model realizes convenient disassembly and assembly of the fixed structure by arranging a card slot group to place the fixed structure, shortens the time of separating the wafer sub-layers, and improves the use efficiency and convenience of NPW;
[0021] The utility model can further reduce the influence of the positions of other wafer sub-layers below when separating the wafer sub-layers by setting the first slot group and the second slot group not to overlap, thereby ensuring the use efficiency of the wafer structure and improving the reliability of the wafer structure;
[0022] The utility model can ensure the reliability of fixed connection between two adjacent wafer sub-layers by arranging more than or equal to 2 groups of slot groups on two adjacent wafer sub-layers;
[0023] The utility model further improves the stability and reliability of the wafer structure by arranging the slot groups to be symmetrically distributed, and avoids misalignment between adjacent wafer sub-layers;
[0024] The utility model improves the disassembly efficiency of the fixed structure and ensures the alignment stability between adjacent wafer sub-layers by setting the fixed structure as a detachable buckle structure;
[0025] The utility model sets the fixing structure as a fixing rod, so that the fixing structure is simple and easy to operate, and the improvement cost is lower;
[0026] The utility model sets the card slot as a C-shaped slot, so that the card engagement of the fixed structure is reliable and the disassembly is convenient, thereby improving the use efficiency of the wafer structure;
[0027] The utility model sets the card slot as a countersunk through hole, so that when the fixing structure is placed from above the countersunk through hole, the fixing structure will be stuck on the bottom step surface of the countersunk through hole, thereby realizing the locking of the fixing structure in the card slot. At the same time, compared with the C-shaped groove, this method does not need to generate strong friction between the fixing structure and the card slot during the locking and disassembly, so the wear speed is greatly reduced, which is conducive to improving the service life of the wafer structure.
[0028] The utility model sets the thickness relationship between the fixed structure and the wafer sub-layer so that the fixed structure does not affect the fixed connection of other wafer sub-layers, thereby improving the convenience of disassembly and assembly and the structural reliability of the wafer structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 Shown is a structural schematic diagram of the wafer structure in the present invention.
[0030] Figure 2 Shown is a schematic diagram of the structure of a single wafer sub-layer in an example of the present invention.
[0031] Figure 3 Shown is a structural schematic diagram of a wafer structure in an example of the present invention.
[0032] Component number description
[0033] 1. Wafer sublayer; 2. Edge; 3. Slot; 4. Fixing rod. DETAILED DESCRIPTION
[0034] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0035] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.
[0036] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.
[0037] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0038] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.
[0039] The utility model provides a wafer structure, such as Figure 1 As shown, the wafer structure includes: at least two stacked wafer sub-layers 1 and a fixed structure (not shown in the figure); the fixed structure is at least arranged in the edge 2 area between two adjacent wafer sub-layers 1, and is used to fix the two adjacent wafer sub-layers 1 to be connected; the fixed structure between the two adjacent wafer sub-layers 1 can be disassembled or removed, so as to separate the two adjacent wafer sub-layers 1.
[0040] In the prior art, NPW (non-productive wafer) usually needs to be deposited with a front layer before use to protect the NPW, so that after one use, the front layer is cleaned and recycled, and the front layer is re-deposited when it is used again to achieve multiple reuse of NPW; while in the ALD reaction, due to the thin deposition thickness, the ALD film cannot cover the unevenness of the front layer surface, and the characteristics of the obtained ALD film cannot be accurately measured. Therefore, the front layer is usually not deposited in the ALD process, and ALD deposition is performed directly on the NPW, resulting in the NPW not being protected by the front layer, and the cleaning process of the NPW after the ALD process will also have a slight effect on the surface of the NPW. Therefore, the NPW in the ALD process is usually difficult to be recycled and reused, and it will be scrapped or downgraded to a pseudo film after one use, resulting in a great waste of cost.
[0041] The utility model sets a wafer structure including stacked wafer sub-layers 1 and a fixed structure, and utilizes the detachable or removable fixed structure to obtain multiple wafer sub-layers 1 by slicing an NPW in the prior art, so that an NPW in the prior art can be used as an NPW multiple times, thereby reducing the use cost of the NPW and improving the utilization rate of the NPW at the same cost.
[0042] In one embodiment, the material of the wafer sub-layer 1 is consistent with the material of the fixed structure.
[0043] The utility model sets the wafer sub-layer 1 and the fixed structure to be made of the same material, so that no friction scratches are generated on the wafer sub-layer 1 during the disassembly or removal of the fixed structure, thereby further reducing the use cost of the wafer sub-layer 1.
[0044] In one embodiment, the material of the wafer sub-layer 1 and the material of the fixed structure are both silicon.
[0045] In one embodiment, the thickness of the wafer sublayer 1 at the bottom layer is 755 microns to 795 microns, and the thickness of other non-bottom wafer sublayers 1 is 10 microns. Specifically, the thickness of each wafer sublayer 1 can be selected appropriately according to actual application.
[0046] In one embodiment, the wafer structure includes four wafer sub-layers 1. Specifically, the number of appropriate wafer sub-layers 1 can be selected according to actual applications.
[0047] Specifically, Figure 1 As shown, the wafer structure includes 6 layers of wafer sub-layers 1, wherein the bottom wafer sub-layer 1 is thicker than other non-bottom wafer sub-layers 1.
[0048] In one embodiment, an area 1-2 mm away from the edge 2 of the wafer sub-layer 1 is used to set the fixing structure.
[0049] In one embodiment, an area 3-5 mm away from the edge 2 of the wafer sub-layer 1 is used to set the fixing structure.
[0050] In one embodiment, the fixing structure between two adjacent wafer sub-layers 1 is an adhesive layer, a coating layer, a metal, a non-metal, a semiconductor material or other bonding material provided at the edge 2 of the contact surface between the two adjacent wafer sub-layers 1, so as to provide a fixed connection between the two adjacent wafer sub-layers 1. Specifically, the bonding material can be disassembled or removed by heating, cleaning with chemical reagents, irradiating ultraviolet rays or the like to separate the two adjacent wafer sub-layers 1.
[0051] In one embodiment, Figure 2 The structure of a single wafer sub-layer 1 is shown, and a card slot 3 is provided at the edge 2 of the wafer sub-layer 1; the first direction is a direction perpendicular to the wafer sub-layer 1, and the projections of the card slots 3 of two adjacent layers of the wafer sub-layers 1 in the first direction overlap, and the two card slots 3 of two adjacent layers of the wafer sub-layers 1 whose projections in the first direction overlap form a card slot group, and the two card slots 3 in the card slot group are detachably engaged with the fixed structure.
[0052] The utility model realizes convenient disassembly and assembly of the fixed structure by arranging the fixed structure in the card slot group, shortens the time for separating the wafer sub-layers 1, and improves the use efficiency and convenience of the NPW.
[0053] In one embodiment, when there are adjacent wafer sub-layers 1 above and below a layer of the wafer sub-layer 1, the slot group where the slots 3 whose projections of the middle wafer sub-layer 1 and the upper wafer sub-layer 1 overlap in the first direction are located is the first slot group, and the slot group where the slots 3 whose projections of the middle wafer sub-layer 1 and the lower wafer sub-layer 1 overlap in the first direction are located is the second slot group, and the projections of the first slot group and the second slot group in the first direction do not overlap.
[0054] The utility model can further reduce the influence of the positions of other wafer sublayers 1 below when separating the wafer sublayer 1 by setting the first slot group and the second slot group not to overlap, thereby ensuring the use efficiency of the wafer structure and improving the reliability of the wafer structure.
[0055] In one embodiment, two adjacent wafer sub-layers 1 have n groups of slot groups, where n is greater than or equal to 2.
[0056] The utility model sets more than or equal to 2 slot groups in two adjacent wafer sub-layers 1, and since the projections of the two slots 3 in each slot group in the first direction overlap, the reliability of the fixed connection between the two adjacent wafer sub-layers 1 can be ensured.
[0057] In one embodiment, two adjacent wafer sub-layers 1 have two groups of the slot groups, so as to improve the efficiency of disassembling the fixing structure while ensuring the reliability of the fixed connection between the two adjacent wafer sub-layers 1.
[0058] In one embodiment, each group of the slot groups is symmetrically distributed relative to a diameter of the wafer sub-layer 1 passing through the center point.
[0059] The utility model further improves the stability and reliability of the wafer structure and avoids misalignment between adjacent wafer sub-layers 1 by arranging the slot groups to be symmetrically distributed.
[0060] In one embodiment, the fixing structure is a detachable snap-on structure, which includes a male snap and a female snap; the male snap and the female snap can be detachably snap-on fixed through the slot groups of two adjacent layers of the wafer sub-layers 1, respectively, so that the positions of the two adjacent layers of the wafer sub-layers 1 where the slot groups are located are fixed in a direction parallel to the wafer sub-layer 1.
[0061] The utility model improves the disassembly efficiency of the fixed structure and ensures the alignment stability between adjacent wafer sub-layers 1 by setting the fixed structure as a detachable buckle structure.
[0062] In one embodiment, Figure 3 As shown, the fixing structure is a fixing rod 4, which penetrates and engages in the two slots 3 of the slot group, so that the positions of the two adjacent wafer sub-layers 1 where the slot group is located are fixed in a direction parallel to the wafer sub-layer 1. Specifically, there is no gap between the two adjacent wafer sub-layers 1. Figure 3 In order to more clearly reflect the relationship between the fixing rod 4 and the wafer sub-layer 1 , a distance is set between the wafer sub-layers 1 .
[0063] The utility model sets the fixing structure as the fixing rod 4, so that the fixing structure is simple and easy to operate, and the improvement cost is lower.
[0064] In one embodiment, the fixing rod 4 is a silicon rod.
[0065] In one embodiment, Figure 2 As shown, the card slot 3 is a C-shaped slot; or the card slot 3 is a countersunk through hole, and the countersunk through hole includes a countersunk hole part and a through hole part that are interconnected, and the countersunk hole part of each card slot 3 is located above the through hole part.
[0066] The utility model arranges the clamping slot 3 as a C-shaped slot, so that the clamping of the fixing structure is reliable and the disassembly is convenient, thereby improving the use efficiency of the wafer structure.
[0067] Specifically, the card slot 3 may also be set to be in other suitable shapes.
[0068] In one embodiment, when the slot 3 is a countersunk through hole and the fixed structure is engaged in the slot 3, the fixed structure is fixed with a fixing structure at a position corresponding to the countersunk hole part; the projection area of the fixing structure on the wafer sub-layer 1 is larger than the projection area of the through hole part of the slot 3 where the fixing structure is located on the wafer sub-layer 1 and is less than or equal to the projection area of the countersunk hole part of the slot 3 where the fixing structure is located on the wafer sub-layer 1; the projection of the fixing structure on the wafer sub-layer 1 covers the projection of the through hole part of the slot 3 where the fixing structure is located on the wafer sub-layer 1; and the fixing structure falls on the bottom step surface of the countersunk hole part.
[0069] The utility model sets the card slot 3 as a countersunk through hole, so that when the fixing structure is placed from above the countersunk through hole, the fixing structure will be stuck on the bottom step surface of the countersunk through hole, thereby realizing the engagement of the fixing structure in the card slot 3. At the same time, compared with the C-shaped groove, this method does not need to generate strong friction between the fixing structure and the card slot 3 during engagement and disassembly, so the wear rate is greatly reduced, which is beneficial to improving the service life of the wafer structure.
[0070] In one embodiment, the length of the fixing structure in the first direction is less than or equal to the sum of the thicknesses of the two wafer sub-layers 1 where the two slots 3 of the slot group engaged with the fixing structure are located.
[0071] The utility model sets the thickness relationship between the fixed structure and the wafer sub-layer 1 so that the fixed structure does not affect the fixed connection of other wafer sub-layers 1, thereby improving the convenience of disassembly and assembly and the structural reliability of the wafer structure.
[0072] In one embodiment, the wafer structure is a NPW (non-productive wafer) in an atomic layer deposition process. Specifically, the utility model is mainly used to solve the problem that control wafers in atomic layer deposition are difficult to be recycled, but can also be used in other suitable process methods to increase the utilization rate of NPW and reduce the use cost of NPW.
[0073] Specifically, the method of using the wafer structure is:
[0074] Step 1: placing the wafer structure at a preset position for processing;
[0075] Step 2: Processing the wafer sub-layer 1 located on the top;
[0076] Step 3: After the process is completed, a preset measurement is performed on the top wafer sub-layer 1; the fixed structure between the top wafer sub-layer 1 and the lower wafer sub-layer 1 is disassembled or removed;
[0077] Step 4: performing a process on the top wafer sub-layer 1 exposed after removing the top wafer sub-layer 1;
[0078] Step 5: Repeat steps 3-4 until the bottom wafer sub-layer 1 has completed the process and measurement, and replace the wafer structure.
[0079] Specifically, the method of use may also be improved according to specific application requirements.
[0080] To sum up, the wafer structure of the utility model can realize multiple uses of the same control chip structure by setting wafer sub-layers, thereby reducing the overall use cost and improving the use efficiency; at the same time, the position of the wafer sub-layer is kept fixed during use by setting the card slot group and the fixed structure, thereby improving reliability; in addition, by setting the card slot as a countersunk through hole, the influence of the fixed structure on the wafer sub-layers is reduced, and the stability of the fixed structure is improved; finally, by setting the fixing structure, the reliability and ease of use of the fixed structure are improved.
[0081] Therefore, the utility model effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
[0082] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.
Claims
1. A wafer structure, characterized in that: The wafer structure includes: at least two stacked wafer sub-layers and a fixed structure; the fixed structure is at least arranged in the edge area between two adjacent wafer sub-layers, and is used to fix the two adjacent wafer sub-layers to be connected; the fixed structure between the two adjacent wafer sub-layers can be disassembled or removed, so as to separate the two adjacent wafer sub-layers.
2. According to the wafer structure of claim 1, a card slot is provided at the edge of the wafer sub-layer; the first direction is a direction perpendicular to the wafer sub-layer, and the projections of the card slots of two adjacent layers of the wafer sub-layers in the first direction overlap, and the two card slots of two adjacent layers of the wafer sub-layers whose projections in the first direction overlap form a card slot group, and the two card slots in the card slot group are detachably engaged with the fixed structure.
3. The wafer structure according to claim 2, characterized in that: When there are adjacent wafer sub-layers above and below a layer of the wafer sub-layer, the slot group where the slots of the middle wafer sub-layer and the upper wafer sub-layer whose projections in the first direction overlap are located is the first slot group, and the slot group where the slots of the middle wafer sub-layer and the lower wafer sub-layer whose projections in the first direction overlap are located is the second slot group, and the projections of the first slot group and the second slot group in the first direction do not overlap.
4. The wafer structure according to claim 2, characterized in that: Two adjacent wafer sub-layers have n groups of slot groups, where n is greater than or equal to 2.
5. The wafer structure according to claim 4, characterized in that: Each group of the slot groups is symmetrically distributed relative to a diameter of the wafer sub-layer passing through the center point.
6. The wafer structure according to claim 2, characterized in that: The fixing structure is a detachable snap-on structure, which includes a male snap and a female snap; the male snap and the female snap can be detachably snap-on fixed through the slot groups of the two adjacent layers of the wafer sub-layers, respectively, so that the positions of the two adjacent layers of the wafer sub-layers where the slot groups are located are fixed in a direction parallel to the wafer sub-layers.
7. The wafer structure according to claim 2, characterized in that: The fixing structure is a fixing rod, which penetrates and engages in the two slots of the slot group, so that the positions of the two adjacent wafer sub-layers where the slot group is located are fixed in a direction parallel to the wafer sub-layers.
8. The wafer structure according to any one of claims 2 to 7, characterized in that: The card slot is a C-shaped slot; or the card slot is a countersunk through hole, and the countersunk through hole includes a countersunk hole part and a through hole part that are interconnected, and the countersunk hole part of each card slot is located above the through hole part.
9. The wafer structure according to claim 8, characterized in that: When the slot is a countersunk through hole and the fixed structure is engaged in the slot, the fixed structure is fixed with a fixing structure at a position corresponding to the countersunk hole part; the projection area of the fixing structure on the wafer sub-layer is larger than the projection area of the through hole part of the slot where the fixing structure is located on the wafer sub-layer and is less than or equal to the projection area of the countersunk hole part of the slot where the fixing structure is located on the wafer sub-layer; the projection of the fixing structure on the wafer sub-layer covers the projection of the through hole part of the slot where the fixing structure is located on the wafer sub-layer, and the fixing structure falls on the bottom step surface of the countersunk hole part.
10. The wafer structure according to claim 2, characterized in that: The length of the fixing structure in the first direction is less than or equal to the sum of the thicknesses of the two wafer sub-layers where the two slots of the slot group engaged by the fixing structure are located.