Chip routing structure

Abstract

The utility model provides a chip routing structure which is formed between a chip and a substrate, the chip is provided with a pin layer, the substrate is provided with a pin structure, and the chip routing structure comprises a plurality of reverse routing leads which are connected between the pin layer and the pin structure; and the plurality of forward lead wires are connected between the pin layers, and the two ends of the plurality of reverse lead wires are respectively provided with at least one forward lead wire. The problem that in chip packaging in a compact space, a routing structure of chip packaging cannot meet the requirements for miniaturization and stability at the same time is solved.

Description

Technical Field

[0001] The utility model relates to the technical field of chip packaging, in particular to a chip wire bonding structure. Background Art

[0002] The description in this section merely provides background information related to the disclosure of the present utility model and does not constitute prior art.

[0003] In the field of chip packaging technology, especially in the field of integrated packaging technology, wire bonding is usually used to connect pads on a wafer and ports on a substrate using wires. There are two different ways of wire bonding, namely, positive bonding and reverse bonding. The two connection methods will bring different connection effects. Positive bonding is to use the pad of the wafer as the first welding point, and the port on the substrate as the second welding point. The lead is first welded from the first welding point, and then pulled to the second welding point for welding. Therefore, positive bonding has high requirements on the height of the wire arc, resulting in large material consumption, and the lead occupies too large a package volume, which cannot be applied to chip packaging in a smaller space. On the contrary, the reverse bonding method is adopted, that is, the pad on the substrate is used as the first welding point, and the pad of the wafer is used as the second welding point. The lead is first welded from the first welding point, and then pulled to the second welding point for welding. The reverse bonding process uses a smaller lead volume and can meet the chip packaging in a smaller space. However, the lead supporting force of the reverse bonding process is weak. During the plastic sealing process, as the plastic sealing material (Epoxy Molding Compound, EMC) melts, the leads generated by the reverse bonding process will slowly move to both sides along the mold flow direction, resulting in wire arc deviation, punching, chip exposure, or breakage.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the utility model and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the utility model. Utility Model Content

[0005] The utility model aims to provide a chip wire bonding structure, which solves the problem that the chip packaging wire bonding structure cannot meet the requirements of miniaturization and stability at the same time in a chip packaging in a compact space.

[0006] The above-mentioned implementation purpose of the utility model is mainly achieved by the following technical solutions:

[0007] The utility model provides a chip wire bonding structure, which is formed between a chip and a substrate, wherein the chip has a pin layer, and the substrate has a pin structure. The chip wire bonding structure includes:

[0008] A plurality of back-punch leads connected between the pin layer and the pin structure;

[0009] A plurality of positive leads are connected between the lead layer and the lead structure, and at least one positive lead is respectively disposed at both ends of the plurality of negative leads.

[0010] In a specific embodiment, the pin structure has multiple first pins, the pin layer has multiple second pins, and the distance between the first pin connected to the positive lead and the second pin is greater than the distance between the first pin connected to the reverse lead and the second pin.

[0011] In a specific embodiment, at least one end of the plurality of reverse-tying leads is provided with a plurality of forward-tying leads, and the distances between the first pin and the second pin connected to at least two of the forward-tying leads are unequal.

[0012] In a specific embodiment, the distance between the first pin and the second pin connected to the positive lead arranged adjacent to the multiple reverse leads is greater than the distance between the first pin and the second pin connected to the positive lead arranged non-adjacent to the multiple reverse leads.

[0013] In a specific embodiment, a plurality of the first pins are spaced apart along a direction parallel to the pin layer, a plurality of the second pins are spaced apart along an extension direction of the pin layer, and the number of the second pins is greater than the number of the first pins.

[0014] In a specific embodiment, the vertical distance between the first pin connected to the bonding lead and the chip is a first distance, the first distance is greater than or equal to the height of the chip, and the first distance is less than or equal to 1.4 times the height of the chip.

[0015] In a specific embodiment, the vertical distance between the first pin connected to the back-bonded lead and the chip is a second distance, the second distance is greater than or equal to 0.6 times the height of the chip, and the second distance is less than or equal to 0.7 times the height of the chip.

[0016] In a specific embodiment, at least one auxiliary positive lead is interspersed between the plurality of reverse leads, and the auxiliary positive lead is connected between the lead layer and the lead structure.

[0017] In a specific embodiment, at least one auxiliary back-punch lead is respectively provided at two ends of the lead structure, and the auxiliary back-punch lead is connected between the lead layer and the lead structure.

[0018] In a specific embodiment, the extension direction of the first pin and the extension direction of the pin structure are arranged at a certain angle, and the angle is greater than or equal to 0° and less than or equal to 90°.

[0019] The utility model also provides a chip bonding structure, which is formed between a chip and a substrate, wherein the chip has a pin layer, and the substrate has a pin structure. The chip bonding structure includes:

[0020] A plurality of positive leads connected between the pin layer and the pin structure;

[0021] A plurality of reverse-punch leads are connected between the lead layer and the lead structure, and at least one reverse-punch lead is respectively disposed at both ends of the plurality of forward-punch leads.

[0022] Compared with the prior art, the technical solution described in the utility model has the following characteristics and advantages:

[0023] The utility model can form a chip bonding structure that is stable and resistant to fluid impact by providing positive bonding leads at both ends of multiple reverse bonding leads. The positive bonding leads can provide a stable support function at both ends of the chip bonding structure, limit the flow of mold flow generated by the melting of the plastic molding compound (Epoxy Molding Compound, EMC) in the chip bonding structure, provide a relatively stable structural state inside the chip bonding structure, and avoid the occurrence of arc deviation, wire collision, chip exposure, or breakage caused by the deviation of the reverse bonding leads. At the same time, the number of positive bonding leads at both ends of the multiple reverse bonding leads can be multiple, which can further improve the overall fluid impact resistance of the chip bonding structure and achieve a more stable connection relationship. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a cross-sectional view of the chip bonding structure of the utility model;

[0025] Figure 2 A top view of a first embodiment of a chip bonding structure of the present invention;

[0026] Figure 3 A top view of a second embodiment of the chip bonding structure of the present invention;

[0027] Figure 4 It is a top view of a third embodiment of the chip bonding structure of the present invention.

[0028] Description of Figure Numbers:

[0029] 1. chip; 11. pin layer; 111. second pin;

[0030] 2. substrate; 21. pin structure; 211. first pin;

[0031] 31. Reverse hit lead; 32. Forward hit lead; 33. Auxiliary reverse hit lead;

[0032] H1, first distance;

[0033] H2, second distance;

[0034] F. Extension direction of the pin layer;

[0035] E. Extension direction of the pin structure;

[0036] D. The extension direction of the first pin. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0038] It should be noted that when an element is referred to as being "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only embodiment.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0040] Implementation method 1:

[0041] like Figure 1 and Figure 2 As shown, the utility model provides a chip bonding structure, which is formed between a chip 1 and a substrate 2, wherein the chip 1 has a pin layer 11, and the substrate 2 has a pin structure 21. The chip bonding structure includes:

[0042] A plurality of back-punched leads 31 connected between the pin layer 11 and the pin structure 21;

[0043] A plurality of positive leads 32 are connected between the lead layer 11 and the lead structure 21 , and at least one positive lead 32 is respectively disposed at both ends of the plurality of negative leads 31 .

[0044] The chip bonding structure provided by the utility model forms a stable bonding structure resistant to fluid impact by respectively providing positive bonding leads 32 at both ends of a plurality of reverse bonding leads 31. The positive bonding leads 32 play a supporting role of stabilizing the two ends of the chip bonding structure, limiting the flow of mold flow generated by the melting of the plastic molding compound (Epoxy Molding Compound, EMC) in the chip bonding structure, providing a relatively stable structural state inside the chip bonding structure, and avoiding the arc deviation, wire punching, chip 1 exposure, or breakage caused by the reverse bonding leads 31 being affected by the mold flow. At the same time, the number of positive bonding leads 32 located at both ends of the plurality of reverse bonding leads 31 can be multiple, which can further enhance the strength of the overall chip bonding structure resistant to fluid impact and achieve a more stable connection relationship.

[0045] Exemplarily, in this embodiment, the chip 1 is stacked on the upper surface of the substrate 2, the pin layer 11 of the chip 1 is arranged on the upper surface of the chip 1, and the pin structure 21 of the substrate 2 is also arranged on the upper surface of the substrate 2. In other embodiments, the specific positions of the pin layer 11 and the pin structure 21 are not limited; in this embodiment, the pin structure 21 is arranged close to a bottom side of the chip 1, and the pin layer 11 is arranged on a side of the upper surface of the chip 1 close to the pin structure 21 to save the wire bonding length. In other embodiments, it can also be arranged on other sides, and there is no specific limitation on this. In this embodiment, the reverse leads 31 are arranged at equal intervals along the extension direction of the bottom side of the chip 1. In other embodiments, multiple reverse leads 31 can also be arranged at different intervals or staggered, and there is no specific limitation on this. In this embodiment, a positive lead 32 is respectively provided at both ends of the plurality of reverse leads 31, that is, at both ends of the arrangement direction of the plurality of reverse leads 31, that is, at both ends of the mold flow direction generated when the epoxy molding compound (EMC) melts. In other embodiments, two positive leads 32 may also be respectively provided, and there is no specific limitation on this.

[0046] like Figure 2As shown, in a specific embodiment, the pin structure 21 has a plurality of first pins 211, the pin layer 11 has a plurality of second pins 111, and the distance between the first pin 211 connected to the positive lead 32 and the second pin 111 is greater than the distance between the first pin 211 connected to the reverse lead 31 and the second pin 111.

[0047] The chip bonding structure provided by the utility model avoids the situation that the length of the positive bonding lead 32 is shorter than the length of the reverse bonding lead 31 by adjusting the distance between the first pin 211 and the second pin 111, resulting in excessive offset of the reverse bonding lead 31 and contact with the positive bonding lead 32 during mold flow, thereby causing a short circuit and the like. At the same time, the length of the positive bonding lead 32 is greater than that of the reverse bonding lead 31, and a larger bracket space can be formed at both ends of the reverse bonding lead 31, that is, the fluid in the space between the two positive bonding leads 32 can maintain a relatively gentle flow state when mold flow occurs, thereby reducing the offset of the reverse bonding lead 31.

[0048] Exemplarily, in this embodiment, the first pin 211 is formed on the upper surface of the substrate 2, and the second pin 111 is formed on the upper surface of the chip 1. The connection method of the reverse lead 31 is to use the first pin 211 as the first welding point, pull the reverse lead 31 from the substrate 2 to the upper surface of the chip 1, and use the second pin 111 as the second welding point to achieve welding of the reverse lead 31; the connection method of the positive lead 32 is to use the second pin 111 as the first welding point, pull the positive lead 32 from the upper surface of the chip 1 and then pull it downward to the upper surface of the substrate 2, and use the first pin 211 as the second welding point to achieve welding of the positive lead 32. In this embodiment, the distance between the first pin 211 and the second pin 111 is the projection distance between the first pin 211 and the second pin 111 on the upper surface of the substrate 2, that is, the spacing in a top-down perspective; in other embodiments, the distance between the first pin 211 and the second pin 111 can also be the spatial connection distance between the first pin 211 and the second pin 111, and there is no specific limitation on this; in this embodiment, the distance between the first pin 211 connected to the positive lead 32 and the second pin 111 is greater than the distance between the first pin 211 and the second pin 111 connected to the reverse lead 31, that is, the vertical distance between the first pin 211 connected to the positive lead 32 and the bottom edge of the chip 1 is greater than the vertical distance between the first pin 211 connected to the reverse lead 31 and the bottom edge of the chip 1. In other embodiments, there is no specific limitation on the definition of distance.

[0049] like Figure 4As shown, in a specific embodiment, at least one end of the plurality of reverse leads 31 is provided with a plurality of forward leads 32 , and the distances between the first pin 211 and the second pin 111 connected to at least two of the forward leads 32 are not equal.

[0050] The chip bonding structure provided by the utility model can improve the stability of the chip bonding structure by setting up multiple positive bonding leads 32 at at least one end of the multiple reverse bonding leads 31, and at the same time, the distance between the first pin 211 and the second pin 111 connected to at least two of the positive bonding leads 32 is staggered, which can better reduce the width of the packaging structure and further reduce the size of the packaging structure so that it can adapt to a narrower installation space, such as a smaller chip 1 or device.

[0051] Exemplarily, in the present embodiment, two normal leads 32 are respectively arranged at both ends of the plurality of reverse leads 31. In other embodiments, four or five normal leads 32 may be respectively arranged at both ends of the plurality of reverse leads 31, and no specific limitation is made thereto. In another other embodiment, two normal leads 32 may be arranged at one end of the plurality of reverse leads 31, and one normal lead 32, or four or five normal leads 32 may be arranged at the other end of the plurality of reverse leads 31, and no specific limitation is made thereto. In the present embodiment, two normal leads 32 located at either end of the plurality of reverse leads 31 are arranged at intervals, wherein the vertical distance between the first pin 211 connected to the normal lead 32 close to the plurality of reverse leads 31 and the bottom edge of the chip 1 is greater than the vertical distance between the first pin 211 connected to the normal lead 32 far from the plurality of reverse leads 31 and the bottom edge of the chip 1. In other embodiments, the vertical distance between the first pin 211 connected to the normal lead 32 close to the plurality of reverse leads 31 and the bottom edge of the chip 1 may be less than There is no specific restriction on the vertical distance between the first pin 211 connected to the positive lead 32 away from the multiple reverse leads 31 and the bottom edge of the chip 1; in another embodiment, the two positive leads 32 at either end of the multiple reverse leads 31 can also be cross-arranged, and in other embodiments, a high-low setting can also be adopted, that is, the vertical lines between the two first pins 211 and the bottom edge of the chip 1 are arranged in a colinear manner. In this embodiment, the vertical distance between the first pin 211 connected to one of the positive leads 32 and the bottom edge of the chip 1 is smaller than the vertical distance between the first pin 211 connected to the other positive lead 32 and the bottom edge of the chip 1, and the second pins 111 respectively connected to the two positive leads 32 are arranged at intervals on the upper surface of the chip 1; in another embodiment, three positive leads 32 are provided at one end of the multiple reverse leads 31, and the distances between the first pin 211 and the second pin 111 connected to the three positive leads 32 are not equal. In other embodiments, there is no specific restriction on which specific setting method is adopted.

[0052] like Figure 4 As shown, in a specific embodiment, the distance between the first pin 211 and the second pin 111 connected to the positive lead 32 arranged adjacent to the plurality of the reverse leads 31 is greater than the distance between the first pin 211 and the second pin 111 connected to the positive lead 32 arranged non-adjacent to the plurality of the reverse leads 31.

[0053] The chip bonding structure provided by the utility model can realize a more stable support structure by limiting the distance between the first pin 211 and the second pin 111 connected to the positive bonding lead 32 arranged adjacent to the plurality of the reverse bonding leads 31, and the distance between the first pin 211 and the second pin 111 connected to the positive bonding lead 32 arranged non-adjacent to the plurality of the reverse bonding leads 31, that is, narrowing the length of the positive bonding lead 32 along the mold flow direction, reducing the mold flow velocity and flow tendency, and avoiding excessive deviation of the reverse bonding lead 31 and the positive bonding gold wires at both ends. At the same time, the length of the positive bonding leads 32 at both ends is shortened, which can leave more chamfering space in the length direction of the packaging structure. The volume of the packaging structure is further narrowed, and it is better applied in narrow spaces.

[0054] Exemplarily, in this embodiment, two positive leads 32 are respectively arranged at both ends of the plurality of reverse leads 31, wherein the vertical distance between the first pin 211 connected to the positive lead 32 close to the plurality of reverse leads 31 and the second pin 111 is greater than the vertical distance between the first pin 211 connected to the positive lead 32 far from the plurality of reverse leads 31 and the second pin 111, that is, the vertical distance between the first pin 211 connected to the positive lead 32 close to the plurality of reverse leads 31 and the bottom edge of the chip 1 is greater than the vertical distance between the first pin 211 connected to the positive lead 32 far from the plurality of reverse leads 31 and the bottom edge of the chip 1. In other embodiments, Three, four or five positive leads 32 may be respectively arranged at both ends of the plurality of reverse leads 31, wherein the distance between the first pin 211 and the second pin 111 connected to the positive lead 32 arranged adjacent to the plurality of reverse leads 31 is the largest, and the distance between the first pin 211 and the second pin 111 connected to the positive lead 32 arranged non-adjacent to the plurality of reverse leads 31 is equal to and smaller than the distance between the first pin 211 and the second pin 111 connected to the positive lead 32 arranged adjacent to the plurality of reverse leads 31. In other embodiments, no specific limitation is made to this.

[0055] like Figure 2 , Figure 3 and Figure 4As shown, in a specific embodiment, a plurality of first pins 211 are arranged at intervals along a direction parallel to the pin layer 11 , a plurality of second pins 111 are arranged at intervals along an extension direction F of the pin layer 11 , and the number of the second pins 111 is greater than the number of the first pins 211 .

[0056] The chip wire bonding structure provided by the utility model can more conveniently connect the first pin 211 with the second pin 111 by arranging the plurality of first pins 211 in a direction parallel to the pin layer 11, thereby avoiding the situation that the leads are easily in contact with each other and short-circuited under the impact of mold flow due to the misaligned arrangement of the pins. At the same time, the arrangement of the second pin 111 is extended along the arrangement direction of the plurality of second pins 111, so that the plurality of second pins 111 can roughly correspond to the plurality of first pins 211, thereby avoiding the situation that the leads connected to the second pin 111 are in contact with each other and short-circuited under the influence of mold flow.

[0057] Exemplarily, in this embodiment, the first pins 211 are arranged at intervals along a direction parallel to the pin layer 11, that is, they are arranged at intervals along a direction parallel to the arrangement of the plurality of second pins 111. In other embodiments, they can also be arranged at intervals along a length direction parallel to the pin layer 11. In this embodiment, the arrangement direction of the first pins 211 is limited to the extension arrangement direction parallel to the second pins 111. In this embodiment, the spacing distances of the plurality of first pins 211 along the direction parallel to the pin layer 11 are the same, and the vertical distances between the plurality of first pins 211 and the bottom edge of the chip 1 are also the same. In other embodiments, the spacing distances of the plurality of first pins 211 along the direction parallel to the pin layer 11 are the same, but the vertical distances between the plurality of first pins 211 and the bottom edge of the chip 1 are different. In this embodiment, the plurality of second pins 111 are arranged at intervals along the extension direction F of the pin layer 11, that is, they extend along the length direction of the pin layer 11. In this embodiment, the number of second pins 111 is greater than the number of first pins 211 , and the extra pins are not connected to the positive leads 32 or the reverse leads 31 , and the extra second pins 111 can be used for other functions of the chip 1 .

[0058] like Figure 2 and Figure 4 As shown, in a specific embodiment, the vertical distance between the first pin 211 connected to the positive lead 32 and the chip 1 is a first distance H1, the first distance H1 is greater than or equal to the height of the chip 1, and the first distance H1 is less than or equal to 1.4 times the height of the chip 1.

[0059] The chip bonding structure provided by the utility model provides a more stable chip bonding structure of the bonding lead 32 by limiting the positional relationship between the vertical distance between the first pin 211 connected to the bonding lead 32 and the chip 1 and the height of the chip 1, that is, limiting the specific structural proportion of the bonding lead 32 connected between the first pin 211 and the second pin 111, thereby avoiding the problem of weak supporting force caused by the excessively large ratio of the length of the bonding lead 32 to the height difference, and also avoiding the problem of being unable to connect between the first pin 211 and the second pin 111 or causing the risk of easy breakage due to the excessively small ratio of the length of the bonding lead 32 to the height difference, thereby achieving a more stable chip bonding structure.

[0060] For example, in this embodiment, the height of the chip 1 of this embodiment is 0.5 mm. In other embodiments, the height of the chip 1 can also be determined according to the required packaging structure, and there is no specific limitation on this. In this embodiment, the vertical distance between the first pin 211 connected to the positive lead 32 and the chip 1 is the first distance H1, the first distance H1 is greater than or equal to 0.5 mm, and the first distance H1 is less than or equal to 0.7 mm.

[0061] like Figure 2 and Figure 4 As shown, in a specific embodiment, the vertical distance between the first pin 211 connected to the back-punch lead 31 and the chip 1 is a second distance H2, and the second distance H2 is greater than or equal to 0.6 times the height of the chip 1, and the second distance H2 is less than or equal to 0.7 times the height of the chip 1.

[0062] The chip bonding structure provided by the utility model provides a more stable chip bonding structure of the back-bonding lead 31 by limiting the positional relationship between the vertical distance between the first pin 211 connected to the back-bonding lead 31 and the chip 1 and the height of the chip 1, that is, limiting the specific structural proportion of the back-bonding lead 31 connected between the first pin 211 and the second pin 111, thereby avoiding the problem of weak supporting force caused by the excessively large ratio of the back-bonding lead 31 line length to the height difference, and also avoiding the problem of the back-bonding lead 31 being unable to connect between the first pin 211 and the second pin 111 or causing the risk of easy breakage due to the excessively small ratio of the back-bonding lead line length to the height difference, thereby achieving a chip bonding structure with better stability.

[0063] For example, in this embodiment, the height of the chip 1 of this embodiment is 0.5 mm. In other embodiments, the height of the chip 1 can also be determined by the required packaging structure, and there is no specific limitation on this. In this embodiment, the vertical distance between the first pin 211 connected to the back-up lead 31 and the chip 1 is the second distance H2, the second distance H2 is greater than or equal to 0.3 mm, and the second distance H2 is less than or equal to 0.35 mm.

[0064] In a specific implementation, at least one auxiliary positive lead is interspersed between the plurality of reverse leads 31 , and the auxiliary positive lead is connected between the lead layer 11 and the lead structure 21 .

[0065] The chip bonding structure provided by the utility model can enhance the fluid impact resistance of the chip bonding structure by inserting at least one auxiliary positive bonding lead between the multiple reverse bonding leads 31. At the same time, the auxiliary positive bonding lead can also form a relatively stable liquid flow area together with other auxiliary positive bonding leads, or the auxiliary positive bonding lead and the positive bonding leads 32 at both ends of the multiple reverse bonding leads 31, thereby avoiding the reverse bonding leads 31 located in the area between the auxiliary positive bonding leads and other auxiliary positive bonding leads, or the reverse bonding leads 31 located in the area between the auxiliary positive bonding leads and the positive bonding leads 32 at both ends of the multiple reverse bonding leads 31. Transitional deviation occurs under the impact of mold flow.

[0066] Illustratively, in the present embodiment, the connection method of the auxiliary positive hitting lead is the same as that of the positive hitting lead 32, and an auxiliary positive hitting lead is provided between two adjacent reverse hitting leads 31. In another embodiment, multiple auxiliary positive hitting leads are provided between two adjacent reverse hitting leads 31. In yet another embodiment, the number of auxiliary positive hitting leads is one, and the auxiliary positive hitting lead is provided between any two adjacent reverse hitting leads 31 among the multiple reverse hitting leads 31. In other embodiments, there is no restriction on the specific form of the auxiliary positive hitting lead interspersed between the multiple reverse hitting leads 31, and there is no specific restriction on whether there is one reverse hitting lead 31 or multiple reverse hitting leads 31 between the multiple auxiliary positive leads.

[0067] like Figure 3 As shown, in a specific embodiment, at least one auxiliary back-punch lead 33 is respectively provided at both ends of the lead structure 21 , and the auxiliary back-punch lead 33 is connected between the lead layer 11 and the lead structure 21 .

[0068] The chip bonding structure provided by the utility model can reduce the lead height at both ends of the chip bonding structure when the upper side of the packaging structure needs to be chamfered, thereby avoiding damage to the leads at both ends of the chip bonding structure during chamfering, affecting the normal electrical connection of the leads, and also taking into account the purpose of narrowing the chip 1.

[0069] Illustratively, in the present embodiment, the connection method of the auxiliary back-hit lead 33 is the same as that of the back-hit lead 31. The auxiliary back-hit lead 33 is located at both ends of the pin structure 21, that is, it is arranged on the side of the positive lead 32 away from the multiple back-hit leads 31. In the present embodiment, an auxiliary back-hit lead 33 is respectively provided at both ends of the pin structure 21. In other embodiments, two or three auxiliary back-hit leads 33 can also be respectively provided at both ends of the pin structure 21. There is no specific limitation on the number of the auxiliary back-hit leads 33.

[0070] like Figure 2 , Figure 3 and Figure 4 As shown, in a specific embodiment, the extension direction D of the first pin 211 and the extension direction E of the pin structure 21 are arranged at a certain angle, and the angle is greater than or equal to 0°, and the angle is less than or equal to 90°.

[0071] The chip bonding structure provided by the utility model can make more effective use of the space of the substrate 2 by setting the angle relationship between the extension direction D of the first pin 211 and the extension direction E of the pin structure 21, thereby achieving a more compact arrangement and minimizing the extension length of the pin structure 21 to the maximum extent, so that the packaging structure can be installed in a smaller installation space.

[0072] Exemplarily, in this embodiment, the first pin 211 is generally elliptical, and in other embodiments, the first pin 211 may also be other shapes with extension directions. The extension direction D of the first pin 211 in this embodiment is the extension direction of the major axis of the ellipse; the extension direction E of the pin structure 21 in this embodiment is the arrangement direction of the plurality of first pins 211, and the extension direction D of the first pin 211 is arranged at a certain angle to the extension direction E of the pin structure 21, that is, the extension direction D of the first pin 211 may not be parallel to the extension direction E of the pin structure 21; further, the angle is less than or equal to 90° , that is, the extension direction D of the first pin 211 may not be perpendicular to the extension direction E of the pin structure 21, that is, the distance between adjacent reverse leads 31 may be smaller than the distance between adjacent first pins 211, so as to achieve a compression effect; further, in other embodiments, the vertical connection lines between two adjacent first pins 211 and the bottom edge of the chip 1 may also be arranged in a colinear manner. In this embodiment, the vertical distance between the first pin 211 connected by one of the forward leads 32 and the bottom edge of the chip 1 is smaller than the vertical distance between the first pin 211 connected by the other forward lead 32 and the bottom edge of the chip 1, and no specific limitation is made to this.

[0073] Implementation method 2:

[0074] like Figure 3As shown, the utility model provides a chip bonding structure, which is formed between a chip 1 and a substrate 2, wherein the chip 1 has a pin layer 11, and the substrate 2 has a pin structure 21. The chip bonding structure includes:

[0075] A plurality of positive leads 32 connected between the pin layer 11 and the pin structure 21;

[0076] A plurality of reverse-bonding leads 31 are connected between the lead layer 11 and the lead structure 21 , and at least one reverse-bonding lead 31 is respectively disposed at both ends of the plurality of forward-bonding leads 32 .

[0077] The chip bonding structure provided by the utility model can maintain a stable bonding structure that resists fluid impact by respectively providing reverse bonding leads 31 at both ends of a plurality of positive bonding leads 32, that is, the plurality of positive bonding leads 32 play the role of a bracket for stabilizing the two ends of the chip bonding structure, restricting the flow of mold flow generated by the melting of the plastic molding compound (Epoxy Molding Compound, EMC) in the chip bonding structure, providing a relatively stable structural state inside the chip bonding structure, and avoiding the reverse bonding leads 31 located at both ends of the plurality of positive bonding leads 32 from being affected by the mold flow to produce arc deviation, line collision, exposure of the chip 1, or breakage. At the same time, the highest point of the reverse bonding leads 31 located at both ends of the plurality of positive bonding leads 32 is lower than the highest point of the positive bonding leads 32. Therefore, the reverse bonding leads 31 provided at both ends of the plurality of positive bonding leads 32 are conducive to avoiding the situation that the leads are exposed to the chip 1 when the side edges in the height direction of the chip 1 are chamfered, resulting in breakage. There may be a plurality of reverse-bonded leads 31 located at both ends of the plurality of forward-bonded leads 32 , which can further prevent the leads from being exposed from the chip 1 .

[0078] Exemplarily, in this embodiment, the chip 1 is stacked on the upper surface of the substrate 2, the pin layer 11 of the chip 1 is arranged on the upper surface of the chip 1, and the pin structure 21 of the substrate 2 is also arranged on the upper surface of the substrate 2. In other embodiments, the specific positions of the pin layer 11 and the pin structure 21 are not limited; in this embodiment, the pin structure 21 is arranged near a bottom side of the chip 1, and the pin layer 11 is arranged on a side of the upper surface of the chip 1 near the pin structure 21 to save the wire bonding length of the lead. In other embodiments, it can also be arranged on other sides, and there is no specific limitation on this. In this embodiment, the positive bonding leads 32 are arranged at equal intervals along the extension direction of the bottom side of the chip 1. In other embodiments, multiple positive bonding leads 32 can also be arranged at different intervals or staggered, and there is no specific limitation on this. In this embodiment, at both ends of the multiple positive bonding leads 32, that is, at both ends of the arrangement direction of the multiple positive bonding leads 32, there is a reverse bonding lead 31 respectively. In other embodiments, two or more reverse bonding leads 31 can also be arranged at both ends, and there is no specific limitation on this.

[0079] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the utility model in detail. It should be understood that the above description is only a specific embodiment of the utility model and is not intended to limit the scope of protection of the utility model. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the utility model should be included in the scope of protection of the utility model.

Claims

1. A chip bonding structure, characterized in that: Formed between a chip and a substrate, the chip has a pin layer, the substrate has a pin structure, and the chip wiring structure includes: A plurality of back-punch leads connected between the pin layer and the pin structure; A plurality of positive leads are connected between the lead layer and the lead structure, and at least one positive lead is respectively disposed at both ends of the plurality of negative leads.

2. The chip bonding structure according to claim 1, characterized in that: The pin structure has a plurality of first pins, the pin layer has a plurality of second pins, and the distance between the first pin connected to the positive lead and the second pin is greater than the distance between the first pin connected to the reverse lead and the second pin.

3. The chip bonding structure according to claim 2, characterized in that: At least one end of the plurality of reverse-punching leads is provided with a plurality of forward-punching leads, and the distances between the first pin and the second pin connected to at least two of the forward-punching leads are unequal.

4. The chip bonding structure according to claim 3, characterized in that: The distance between the first pin and the second pin connected to the positive lead arranged adjacent to the plurality of reverse leads is greater than the distance between the first pin and the second pin connected to the positive lead arranged non-adjacent to the plurality of reverse leads.

5. The chip bonding structure according to claim 2, characterized in that: A plurality of the first pins are arranged at intervals along a direction parallel to the pin layer, a plurality of the second pins are arranged at intervals along an extension direction of the pin layer, and the number of the second pins is greater than the number of the first pins.

6. The chip bonding structure according to claim 2, characterized in that: A vertical distance between the first pin connected to the positive lead and the chip is a first distance, the first distance is greater than or equal to the height of the chip, and the first distance is less than or equal to 1.4 times the height of the chip.

7. The chip bonding structure according to claim 2 or 6, characterized in that: The vertical distance between the first pin connected to the back-bonding lead and the chip is a second distance, the second distance is greater than or equal to 0.6 times the height of the chip, and the second distance is less than or equal to 0.7 times the height of the chip.

8. The chip bonding structure according to claim 1, characterized in that: At least one auxiliary positive lead is interspersed between the plurality of reverse leads, and the auxiliary positive lead is connected between the lead layer and the lead structure.

9. The chip bonding structure according to claim 1 or 8, characterized in that: At least one auxiliary back-punch lead is respectively disposed at two ends of the lead structure, and the auxiliary back-punch lead is connected between the lead layer and the lead structure.

10. The chip bonding structure according to claim 2 or 3, characterized in that: An extension direction of the first pin and an extension direction of the pin structure are arranged at a certain angle, wherein the angle is greater than or equal to 0° and less than or equal to 90°.

11. A chip bonding structure, characterized in that: Formed between a chip and a substrate, the chip has a pin layer, the substrate has a pin structure, and the chip wiring structure includes: A plurality of positive leads connected between the pin layer and the pin structure; A plurality of reverse-punch leads are connected between the lead layer and the lead structure, and at least one reverse-punch lead is respectively disposed at both ends of the plurality of forward-punch leads.

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