Chip interconnection structure and chip thereof
By setting capacitor units in the first interconnect layer of the chip interconnect structure and using gel electrolyte and molybdenum disulfide graphene material, the problem that traditional capacitors cannot meet the needs of modern electronic equipment is solved, and smaller area occupation and higher Effects of capacity density.
Patent Information
- Application Number
- CN202420537972.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-19
- Publication Date
- 2025-02-07
- Estimated Expiration
- 2034-03-19
AI Technical Summary
Traditional ultra-small multi-layer ceramic capacitors cannot meet the needs of modern electronic devices for high integration, miniaturization and high frequency response, and the capacity density of wafer-level three-dimensional capacitors is limited and manufacturing costs are high, which limits their wide application in the chip field. .
By adopting a chip interconnect structure, by providing capacitor units in the first interconnect layer and connecting conductor groups to the capacitor, the wafer area is reduced, thereby reducing the chip area. The insulating medium of the capacitor is gel electrolyte, and the electrode materials are molybdenum disulfide and graphene, which improves the capacity density of the capacitor.
It effectively reduces the chip's area and manufacturing cost, simplifies the manufacturing process, increases the capacity density of capacitors, and allows the chip to be better and widespread.
Smart Images
Figure CN222440594U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of capacitors, and more specifically, to a chip interconnection structure and a chip thereof. Background Art
[0002] Capacitors play a very important role in circuits, such as bypass, coupling, filtering, etc., and are an indispensable part of ensuring the normal operation of circuits. At present, the most widely used are ultra-small multilayer ceramic capacitors. However, as modern electronic systems develop towards multi-functions, high integration, and miniaturization, traditional ultra-small multilayer ceramic capacitors can no longer meet people's growing needs.
[0003] In recent years, with the advancement of semiconductor processing technology, a wafer-level three-dimensional capacitor has emerged. It is a new type of capacitor manufactured on a silicon wafer using semiconductor processing technology. Compared with ultra-small multilayer ceramic capacitors, wafer-level three-dimensional capacitors have significant advantages in terms of volume, frequency response, temperature coefficient, etc. However, since the capacity density of wafer-level three-dimensional capacitors is still limited, and they require a large wafer area and high manufacturing costs, wafer-level three-dimensional capacitors have not been better and more widely used in the chip field. In some chip designs, capacitors are manufactured in the semiconductor layer of the wafer. This setting method not only has a more complicated manufacturing process and higher cost, but also has a limited capacity density. It is often necessary to connect multiple capacitors in parallel to increase the capacitor capacity. Utility Model Content
[0004] The purpose of the utility model is to overcome the deficiencies of the prior art and provide a chip interconnection structure and a chip thereof, which can reduce the occupied wafer area, thereby reducing the occupied area of the chip, and enable the chip to be better and more widely used.
[0005] In order to solve the above technical problems, the technical solution adopted by the utility model is:
[0006] A chip interconnection structure is provided, comprising a first covering layer, a first interconnection layer, a second covering layer, and a second interconnection layer which are stacked in sequence, wherein a capacitor unit is arranged in the first interconnection layer, and the capacitor unit comprises a capacitor and an insulating structure wrapping the capacitor, and a connecting conductor group is arranged in the second interconnection layer, wherein one end of the connecting conductor group is connected to the capacitor, and the other end is used for connecting to the outside world.
[0007] The utility model includes a chip interconnection structure, which is connected to a capacitor through a connecting conductor group, and the capacitor is located in the first interconnection layer, which can reduce the occupied wafer area, thereby reducing the occupied area of the chip, and can make the chip more widely used.
[0008] Preferably, the capacitor comprises a first electrode, a second electrode, and an insulating medium disposed between the first electrode and the second electrode, the insulating structure is an insulating groove, and the capacitor is disposed in the insulating groove.
[0009] Preferably, the first electrode comprises a first reinforcement layer, a second reinforcement layer, and an energy storage layer disposed between the first reinforcement layer and the second reinforcement layer.
[0010] Preferably, the first reinforcement layer and the second reinforcement layer are both molybdenum disulfide layers, and the energy storage layer is a graphene layer. The configuration of the first reinforcement layer and the second reinforcement layer being both molybdenum disulfide layers and the configuration of the energy storage layer being a graphene layer can increase electron mobility and effectively improve the capacity density of the capacitor.
[0011] Preferably, the insulating medium is a gel electrolyte. The setting of the insulating medium being a gel electrolyte can have better conductivity and effectively improve the capacity density of the capacitor.
[0012] Preferably, the second covering layer is provided with a plurality of through holes, the connecting conductor group comprises a first connecting conductor and a second connecting conductor, the first connecting conductor is connected to the first electrode after passing through the through holes, and the second connecting conductor is connected to the second electrode after passing through the through holes.
[0013] Preferably, the first connecting conductor and the second connecting conductor are both metal connecting conductors.
[0014] Preferably, a plurality of capacitor units are arranged in the first interconnect layer, and each capacitor unit is connected to the connection conductor group.
[0015] Preferably, the capacitor unit comprises a plurality of capacitors arranged in an array, the insulating structure wraps the plurality of capacitors, and each capacitor is connected to the connecting conductor group.
[0016] The utility model also includes a chip, comprising the above-mentioned chip interconnection structure.
[0017] Compared with the prior art, the beneficial effects of the utility model are:
[0018] The utility model discloses a chip interconnection structure and a chip thereof. The capacitor is located at the first interconnection layer, which can reduce the occupied wafer area, thereby reducing the occupied area of the chip, and can also make the manufacturing process simpler, can reduce the manufacturing cost, and enable the chip to be better and more widely used; the first reinforcement layer and the second reinforcement layer are both molybdenum disulfide layers, and the energy storage layer is a graphene layer, which can increase the electron mobility and effectively improve the capacity density of the capacitor; the insulating medium is a gel electrolyte, which can have better conductivity and effectively improve the capacity density of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 This is a schematic diagram of a chip interconnection structure embodiment 1 of the utility model;
[0020] Figure 2 This is a schematic diagram of a chip interconnection structure embodiment 2 of the utility model;
[0021] Figure 3 This is a schematic structural diagram of a chip interconnection structure embodiment 3 of the present utility model.
[0022] The illustrations are as follows:
[0023] 1-first covering layer, 2-first interconnecting layer, 21-first dielectric, 3-second covering layer, 4-second interconnecting layer, 41-second dielectric, 5-capacitor unit, 51-first electrode, 511-first reinforcement layer, 512-second reinforcement layer, 513-energy storage layer, 52-second electrode, 53-insulating medium, 54-insulating structure, 6-first connecting conductor, 7-second connecting conductor, 8-through hole. DETAILED DESCRIPTION
[0024] The utility model is further described below in conjunction with specific implementation methods. The drawings are only used for exemplary descriptions, and are only schematic diagrams, not actual pictures, and cannot be understood as limitations on this patent; in order to better illustrate the embodiments of the utility model, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.
[0025] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation to the present invention.
[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present utility model, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0027] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0028] In the present utility model, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.
[0029] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.
[0030] Example 1
[0031] like Figure 1The figure shows a first embodiment of a chip interconnection structure of the utility model, comprising a first covering layer 1, a first interconnection layer 2, a second covering layer 3, and a second interconnection layer 4 which are stacked in sequence. A capacitor unit 5 is arranged in the first interconnection layer 2. The capacitor unit 5 includes a capacitor and an insulating structure 54 wrapping the capacitor. A connecting conductor group is arranged in the second interconnection layer 4. One end of the connecting conductor group is connected to the capacitor, and the other end is used to connect to the outside world.
[0032] By connecting the conductor group to the capacitor and locating the capacitor in the first interconnect layer 2, the occupied wafer area can be reduced, thereby reducing the occupied area of the chip, making the manufacturing process simpler, reducing the manufacturing cost, and enabling the chip to be more widely used.
[0033] In this embodiment, the first interconnection layer 2 is filled with a first dielectric 21, the second interconnection layer 4 is filled with a second dielectric 41, and the first interconnection layer 2 and the second interconnection layer 4 are both metal interconnection layers; in this embodiment, the first covering layer 1 and the second covering layer 3 are both dielectric covering layers.
[0034] In this embodiment, the capacitor includes a first electrode 51, a second electrode 52, an insulating medium 53 disposed between the first electrode 51 and the second electrode 52, and an insulating structure 54 is an insulating groove, and the capacitor is disposed in the insulating groove. Specifically, the insulating groove is an insulating shell structure with an open top, and the accommodating cavity of the insulating shell structure matches the capacitor.
[0035] In this embodiment, the first electrode 51 includes a first reinforcement layer 511, a second reinforcement layer 512, and an energy storage layer 513 disposed between the first reinforcement layer 511 and the second reinforcement layer 512. Among them, the first reinforcement layer 511 and the second reinforcement layer 512 are both molybdenum disulfide layers, the energy storage layer 513 is a graphene layer, and the insulating medium 53 is a gel electrolyte. The first reinforcement layer 511 and the second reinforcement layer 512 are both molybdenum disulfide layers, and the energy storage layer 513 is a graphene layer, which can increase the electron mobility and effectively improve the capacity density of the capacitor; the insulating medium 53 is a gel electrolyte, which can have better conductivity and effectively improve the capacity density of the capacitor. Specifically, the first reinforcement layer 511 and the second reinforcement layer 512 are both molybdenum disulfide sheets, and the energy storage layer 513 is a graphene sheet. It should be noted that the thickness of the molybdenum disulfide sheet and the graphene sheet is less than or equal to 50 microns.
[0036] In this embodiment, a plurality of through holes 8 are provided in the second covering layer 3, and the connecting conductor group includes a first connecting conductor 6 and a second connecting conductor 7. The first connecting conductor 6 is connected to the first electrode 51 after passing through the through hole 8, and the second connecting conductor 7 is connected to the second electrode 52 after passing through the through hole 8. In order to facilitate the connection between the connecting conductor group and the capacitor, the through holes 8 are arranged corresponding to the positions where the first electrode 51 and the second electrode 52 are located. Specifically, the first connecting conductor 6 and the second connecting conductor 7 are both metal connecting conductors. Preferably, the metal connecting conductor can be selected from aluminum connecting conductors or copper connecting conductors.
[0037] The utility model provides a method for preparing a chip interconnection structure, comprising the following steps:
[0038] S1. A first covering layer 1 is provided, and a first interconnect layer 2 is provided on the first covering layer 1;
[0039] S2. A first placement position is etched in the first dielectric 21 of the first interconnect layer 2, and the first placement position runs through the first interconnect layer 2;
[0040] S3. An insulating groove is placed in the first placement position, and a first electrode 51, a second electrode 52 and an insulating medium 53 are placed in the insulating groove;
[0041] S4. A second cover layer 3 is disposed on the first interconnect layer 2, and a second interconnect layer 4 is disposed on the second cover layer 3, so that insulation is achieved between the first interconnect layer 2 and the second interconnect layer 4;
[0042] S5. Etching two through holes 8 at the second cover layer 3, and the two through holes 8 correspond to the positions of the first electrode 51 and the second electrode 52 respectively; and etching two second placement positions at the second dielectric 41, the second placement positions penetrate the second interconnection layer 4, and the two placement positions are connected to the two through holes 8 respectively;
[0043] S6. Extend the first connecting conductor 6 into one of the second placement positions in turn, through the hole 8, and connect the first connecting conductor 6 to the first electrode 51; and extend the second connecting conductor 7 into another second placement position in turn, through the hole 8, and connect the second connecting conductor 7 to the second electrode 52.
[0044] It should be noted that in step S3, the insulating groove, the first electrode 51, the gel electrolyte and the second electrode 52 can be first manufactured into a capacitor unit 5, and then the capacitor unit 5 is placed in the first placement position. Compared with ordinary capacitors using metal oxides as electrode materials, the electron mobility will be relatively limited, and the chip interconnection structure of the utility model can increase the electron mobility and the capacitance density of the capacitor by using molybdenum disulfide as the electrode material and adding graphene to the electrode material; using gel electrolyte as the insulating medium of the capacitor, compared with solid dielectrics, it has higher conductivity, which can increase the capacitance density of the capacitor; the arrangement of the capacitor in the first interconnection layer 2 does not occupy the area of the wafer, so that the manufacturing cost can be reduced, and compared with the manufacturing process of setting the capacitor in the semiconductor layer, it can be more convenient, improve the manufacturing efficiency, and also reduce the manufacturing cost; the capacitor unit 5 is first manufactured as a whole, and after mass production, it is directly embedded in the metal interconnection layer of the chip, which can further simplify the manufacturing process and reduce the manufacturing cost.
[0045] Example 2
[0046] This embodiment is similar to embodiment 1, except that Figure 2 As shown, in this embodiment, a plurality of capacitor units 5 are arranged in the first interconnection layer 2, and each capacitor unit 5 is connected to a connection conductor group. Specifically, the insulation structure 54 includes a plurality of arranged insulation slots, each insulation slot has a capacitor placed therein, and each capacitor electrode is connected to a connection conductor.
[0047] Example 3
[0048] This embodiment is similar to embodiment 1, except that Figure 3 As shown, in this embodiment, the capacitor unit 5 includes a plurality of capacitors arranged in an array, the insulating structure 54 wraps the plurality of capacitors, and each capacitor is connected to a connecting conductor group. Specifically, the insulating structure 54 is an insulating groove, and the insulating groove can accommodate at least two capacitors, and each capacitor electrode is connected to a connecting conductor.
[0049] Example 4
[0050] The utility model also includes a first embodiment of a chip, including the chip interconnection structure as described in any one of embodiments 1 to 3. The chip interconnection structure in this embodiment can be applied to a CMOS chip.
[0051] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present invention. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present invention.
[0052] Obviously, the above embodiments of the utility model are only examples for clearly explaining the utility model, and are not intended to limit the implementation methods of the utility model. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made on the basis of the above description. It is not necessary and impossible to list all the implementation methods here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the utility model should be included in the protection scope of the claims of the utility model.
Claims
1. A chip interconnection structure, characterized in that: The invention comprises a first covering layer (1), a first interconnecting layer (2), a second covering layer (3), and a second interconnecting layer (4) which are stacked in sequence, wherein a capacitor unit (5) is arranged in the first interconnecting layer (2), wherein the capacitor unit (5) comprises a capacitor and an insulating structure (54) wrapping the capacitor, and wherein a connecting conductor group is arranged in the second interconnecting layer (4), wherein one end of the connecting conductor group is connected to the capacitor and the other end is used for connecting to the outside.
2. The chip interconnection structure according to claim 1, characterized in that: The capacitor comprises a first electrode (51), a second electrode (52), and an insulating medium (53) arranged between the first electrode (51) and the second electrode (52); the insulating structure (54) is an insulating groove, and the capacitor is arranged in the insulating groove.
3. The chip interconnection structure according to claim 2, characterized in that: The first electrode (51) comprises a first reinforcement layer (511), a second reinforcement layer (512), and an energy storage layer (513) disposed between the first reinforcement layer (511) and the second reinforcement layer (512).
4. The chip interconnection structure according to claim 3, characterized in that: The first reinforcement layer (511) and the second reinforcement layer (512) are both molybdenum disulfide layers, and the energy storage layer (513) is a graphene layer.
5. The chip interconnection structure according to claim 2, characterized in that: The insulating medium (53) is a gel electrolyte.
6. The chip interconnection structure according to claim 2, characterized in that: The second covering layer (3) is provided with a plurality of through holes (8), the connecting conductor group comprises a first connecting conductor (6) and a second connecting conductor (7), the first connecting conductor (6) is connected to the first electrode (51) after passing through the through holes (8), and the second connecting conductor (7) is connected to the second electrode (52) after passing through the through holes (8).
7. The chip interconnection structure according to claim 6, characterized in that: The first connecting conductor (6) and the second connecting conductor (7) are both metal connecting conductors.
8. The chip interconnection structure according to any one of claims 1 to 7, characterized in that: A plurality of capacitor units (5) are arranged in the first interconnection layer (2), and each capacitor unit (5) is connected to the connection conductor group.
9. The chip interconnection structure according to any one of claims 1 to 7, characterized in that: The capacitor unit (5) comprises a plurality of capacitors arranged in an array, the insulating structure (54) wraps the plurality of capacitors, and each capacitor is connected to the connecting conductor group.
10. A chip, characterized in that: The invention comprises a chip interconnection structure as claimed in any one of claims 1 to 9.