Chip module
By deploying chip modules on the circuit board, including chip modules, peripheral component modules and pin pad modules, and expanding pin spacing, the operation difficulty, low efficiency and low yield during touch chip access is solved. The problem is that higher operating efficiency and yield rate have been achieved.
Patent Information
- Application Number
- CN202421116249.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-17
- Publication Date
- 2025-02-14
- Estimated Expiration
- 2034-05-17
AI Technical Summary
In the prior art, touch chips have problems such as high operation difficulty, low efficiency and low yield during the process of connecting to the touch screen.
A chip module is provided, which includes a chip module, a peripheral component module and a pin pad module on a circuit board. The chip module is connected to the peripheral component module, and the pin pad module is connected to the chip module and the peripheral component module, which is used to lead the interface between the pins and peripheral component modules of the chip module. The pin pad module has at least one pair of adjacent pins that have a spacing greater than the spacing of adjacent pins of the chip module.
Through this chip module, the operation difficulty of touch chips in the access circuit is reduced, the operation efficiency and yield rate are improved, and the production cost is reduced.
Smart Images
Figure CN222483924U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip technology, and in particular to a chip module. Background Art
[0002] In the touch screen industry, it is often necessary to attach the touch chip to the flexible cable of the touch screen and connect the chip to the corresponding peripheral components. For touch chips packaged in ball grid array (BGA), there are usually many pins and the pin spacing is small, so the connection has high technical requirements, low connection efficiency and low yield rate. Utility Model Content
[0003] The present application provides a chip module to solve the problems of difficult operation, low efficiency and low yield rate in the process of connecting a touch chip to a touch screen in the prior art.
[0004] In a first aspect, the present application provides a chip module, the module being on a circuit board, comprising: a chip module, a peripheral component module, and a pin pad module;
[0005] The chip module is connected to the peripheral component module;
[0006] The pin pad module is connected to the chip module and the peripheral component module to lead out the pins of the chip module and the interface of the peripheral component module;
[0007] The spacing between at least one pair of adjacent pins in the pin pad module is greater than the spacing between adjacent pins in the chip module.
[0008] Optionally, the chip module includes a touch chip; the pin pad module includes a plurality of first drive channel pins and a plurality of first sensing channel pins; the touch chip includes a plurality of second drive channel pins and a plurality of second sensing channel pins;
[0009] The plurality of first drive channel pins are connected to the plurality of second drive channel pins correspondingly to lead out the second drive channel pins; the distance between two adjacent first drive channel pins is greater than the distance between two adjacent second drive channel pins;
[0010] The plurality of first sensing channel pins are correspondingly connected to the plurality of second sensing channel pins to lead out the second sensing channel pins; and a distance between two adjacent first sensing channel pins is greater than a distance between two adjacent second sensing channel pins.
[0011] Optionally, the chip module further includes a first power pin, the peripheral component module includes a power chip, and the pin pad module further includes a second power pin;
[0012] The first end of the power chip is connected to the first power pin of the chip module, and the second end is connected to the second power pin of the pin pad module; the spacing between the second power pin and the adjacent pin is greater than the spacing between the first power pin and the adjacent pin.
[0013] Optionally, the pin pad module further includes a first data negative pin and a first data positive pin of a universal serial bus interface; the touch chip includes a second data negative pin and a second data positive pin;
[0014] The first data negative pin is connected to the second data negative pin by accessing the first interface of the peripheral component module to lead out the second data negative pin;
[0015] The first data positive pin is connected to the second data positive pin by accessing the second interface of the peripheral component module to lead out the second data positive pin.
[0016] Optionally, the pin pad module further includes a first transmission exchange data pin of a transistor-transistor logic level; the touch control chip further includes a second transmission exchange data pin of a transistor-transistor logic level;
[0017] The first transmission exchange data pin is connected to the second transmission exchange data pin to lead out the second transmission exchange data pin.
[0018] Optionally, the first transmission exchange data pin is connected to the second transmission exchange data pin by accessing a third interface of the peripheral component module.
[0019] Optionally, the pin pad module further includes a first serial port pin of 232 level, and the touch chip further includes a second serial port pin of 232 level;
[0020] The first serial port pin is connected to the second serial port pin by accessing the fourth interface of the peripheral component module to lead out the second serial port pin.
[0021] Optionally, the pin pad module further includes a first serial data line pin of an integrated circuit bus, and a first serial clock line pin; the touch control chip further includes a second serial data line pin of the integrated circuit bus, and a second serial clock line pin;
[0022] The first serial data line pin is connected to the second serial data line pin to lead out the second serial data line pin; the first serial clock line pin is connected to the second serial clock line pin to lead out the second serial clock line pin.
[0023] Optionally, the first serial data line pin is connected to the second serial data line pin by accessing the fifth interface of the peripheral component module; the first serial clock line pin is connected to the second serial clock line pin by accessing the sixth interface of the peripheral component module.
[0024] Optionally, the module further includes a shielding cover module;
[0025] The shielding cover module covers the first surface of the circuit board and is used to cover the chip module and the peripheral component module. The first surface is the surface on which the chip module and the peripheral component module are deployed.
[0026] The pin pad module is located on the second surface of the circuit board, and the second surface is the reverse side of the first surface.
[0027] Optionally, the height of the chip module is greater than 1.5 mm and less than 4 mm; the mainboard is rectangular, and at least two sides have a length greater than 15 mm and less than 25 mm; the pin pad module and the chip module, as well as the peripheral component module, are located on different surfaces of the mainboard.
[0028] Optionally, the pin pad module includes 4 partitions, each of which is located in the edge area of the mainboard; each of the partitions includes multiple pins; the spacing between the pins of each partition is greater than 0.2mm and less than 1cm; the width of each pin is greater than 0.2mm and less than 0.8mm.
[0029] Optionally, the distance between two opposite partitions of the pin pad module is greater than 10 mm and less than 28 mm; the distance between two opposite partitions of the pin pad module that are away from each other is greater than 15 mm and less than 32 mm.
[0030] The chip module provided by the present application, since the chip module directly deploys the peripheral component module on the circuit board, the peripheral components required by the chip module can be deployed in the peripheral component module to realize the corresponding functions of the chip module, and the pins of the chip module and the corresponding interfaces of the peripheral component module are also led out to the pin pad module, and there is at least one pair of adjacent pins with a spacing greater than the spacing between adjacent pins of the chip module. Therefore, the operational difficulty of the chip in the chip module during the process of connecting to the circuit can be reduced, the operational efficiency and the yield rate can be improved, and the production cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0032] Figure 1 A schematic diagram of the structure of the first chip module provided in this application;
[0033] Figure 2 A schematic diagram of the structure of the second chip module provided in this application;
[0034] Figure 3 A schematic diagram of the structure of the third chip module provided in this application.
[0035] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION
[0036] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.
[0037] In the touch screen industry, it is often necessary to attach the touch chip to the flexible cable of the touch screen and connect the chip to the corresponding peripheral components. The touch chip includes multiple drive channel pins, sensing channel pins, and other functional pins (such as Universal Serial Bus (USB) pins) to achieve the touch function. Limited by the chip size and the number of pins, the spacing between each pin is often small. This results in more complicated operations when attaching the touch chip to the flexible cable of the touch screen, resulting in low access efficiency. Moreover, due to the small spacing between pins, errors are prone to occur during operation, resulting in low yield and increased manufacturing costs.
[0038] In view of this, the present application provides a chip module, which can realize the packaging of touch chips and peripheral components, and lead the pins of the touch chip and the interfaces of the peripheral components to the pin pads of the chip module, which is equivalent to expanding the spacing between the pins of the touch chip and reducing the difficulty of attaching the touch chip to the touch screen flexible cable, thereby improving manufacturing efficiency and yield rate and reducing manufacturing costs.
[0039] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.
[0040] Figure 1 The schematic diagram of the structure of the first chip module 11 provided in this application is as follows: Figure 1 As shown, the chip module 11 is on a circuit board, and includes: a chip module 11 , a peripheral component module 12 , and a pin pad module 13 .
[0041] Reference Figure 1 , the connection relationship between the various modules of the chip module 1 is as follows:
[0042] The chip module 11 is connected to the peripheral component module 12 ; the pin pad module 13 is connected to the chip module 11 and the peripheral component module 12 .
[0043] The chip module 11 may include only a single chip, such as a touch chip, or other components, which is not limited in this application. The peripheral component module 12 may include components required to realize the control function of the chip module 11, such as power chips, resistors, capacitors, diodes, transistors, and one or more components. The specific number and connection method of each component are determined according to actual needs. The pin pad module 13 may be located on the same side of the circuit board as the chip module 11 and the peripheral component module 12, or on different sides, which is not limited in this application.
[0044] The pin pad module 13 may, for example, include a plurality of pins, and there is at least a pair of adjacent pins whose spacing is greater than the spacing of adjacent pins of the chip module 11. The present application does not limit the types and quantities of the above-mentioned plurality of pins. The pin pad module 13 is used to lead out the pins of the chip module 11 and the interface of the peripheral component module 12. The present application does not limit the type and quantity of the pins of the chip module 11, which is specifically related to the type and quantity of the chips included in the chip module 11. The present application does not limit the type and quantity of the interface of the peripheral component module 12, which is specifically related to the circuit structure of the peripheral component module 12.
[0045] As described above, since the chip module directly deploys the peripheral component module on the circuit board, the peripheral components required by the chip module can be deployed in the peripheral component module to realize the corresponding functions of the chip module, and the pins of the chip module and the corresponding interfaces of the peripheral component module are also led out to the pin pad module, and there is at least one pair of adjacent pins with a spacing greater than the spacing between adjacent pins of the chip module. Therefore, the operational difficulty of the chip in the chip module during the process of connecting to the circuit can be reduced, the operational efficiency and yield rate can be improved, and the production cost can be reduced.
[0046] Taking the chip module 11 including a touch chip as an example, how the pin pads lead out the pins of the chip module and the interface of the peripheral component module are exemplarily described below through specific embodiments. Figure 2 A schematic diagram of the structure of the second chip module provided in this application, such as Figure 2 As shown, the pin pad module may include, for example, a plurality of first drive channel pins and a plurality of first sensing channel pins; the touch chip may include, for example, a plurality of second drive channel pins and a plurality of second sensing channel pins. This schematic diagram is a schematic diagram taking the pin pad module and the chip module as not being on the same side of the circuit board as an example.
[0047] Continue to refer to Figure 2 A plurality of first drive channel pins are connected to a plurality of second drive channel pins to lead out second drive channel pins; the spacing between two adjacent first drive channel pins is greater than the spacing between two adjacent second drive channel pins. A plurality of first sensing channel pins are connected to a plurality of second sensing channel pins to lead out second sensing channel pins; the spacing between two adjacent first sensing channel pins is greater than the spacing between two adjacent second sensing channel pins.
[0048] The present application does not limit the specific values of the spacing between two adjacent first drive channel pins, the spacing between two adjacent second drive channel pins, the spacing between two adjacent first sensing channel pins, and the spacing between two adjacent second sensing channel pins; the spacing between different adjacent first drive channel pins, the spacing between two adjacent second drive channel pins, the spacing between two adjacent first sensing channel pins, and the spacing between two adjacent second sensing channel pins may be the same or different, and those skilled in the art may set them according to actual needs.
[0049] The number of the first drive channel pins and the second drive channel pins may be the same. Figure 2 Regarding the corresponding connection mode of the plurality of first drive channel pins and the plurality of second drive channel pins, for example, the first drive channel pin 1 (such as Figure 2 Tx1 shown) and the second drive channel pin 1 (as shown Figure 2Correspondingly, the first sensing channel pin 1 (such as Figure 2 Rx1 shown) and the second sensing channel pin 1 (as shown Figure 2 Rx'1) shown in the figure is connected, and so on.
[0050] Multiple first drive channel pins and multiple second drive channel pins of the touch chip can be directly connected; or, multiple first drive channel pins and multiple second drive channel pins of the touch chip can be connected by accessing the peripheral component interface. For example, the peripheral component module 12 may include multiple resistors, and the number of resistors is the same as the number of first drive channel pins and the number of second drive channel pins. The first end of each resistor is connected to the corresponding first drive channel pin, and the second end is connected to the corresponding second drive channel pin. It should be understood that the above is only an example. How to connect multiple first drive channel pins and multiple second drive channel pins of the touch chip by accessing the interface of the peripheral component module 12 can be set by those skilled in the art according to actual needs. This way of connecting by accessing the peripheral component interface can realize the control of the required working environment of the touch chip by designing the circuit of the peripheral components, thereby expanding the application scenario of the chip module 1.
[0051] Optionally, continue to take the chip module 11 including a touch chip as an example, and continue to refer to Figure 2 The pin pad module 13 may also include a first data minus (DM) pin (eg Figure 2 DM pin shown), and the first data plus (Data Plus, DP) pin (as shown Figure 2 The touch chip may include, for example, a second negative data pin of a universal serial bus interface (such as Figure 2 DM' pin shown), and the second data positive pin (as shown Figure 2 DP' pin shown).
[0052] The first data positive pin can be directly connected to the second data positive pin to lead out the second data positive pin of the touch chip; the first data negative pin can also be directly connected to the second data negative pin to lead out the second data negative pin of the touch chip. Alternatively, the first data negative pin can be connected to the second data negative pin by connecting to the first interface of the peripheral component module 12 to lead out the second data negative pin; the first data positive pin can be connected to the second data positive pin by connecting to the second interface of the peripheral component module 12 to lead out the second data positive pin.
[0053] For example, the peripheral component module 12 may include a first resistor and a second resistor. The first end of the first resistor is a first interface, and the second end is connected to the first data negative pin; the first end of the second resistor is a second interface, and the second end is connected to the first data positive interface. In this way, the current limiting of the circuit can be achieved through the first resistor and the second resistor, thereby achieving protection of the circuit. In actual application, this application does not limit the first interface, and the connection method of the electrical components in the peripheral component module connected to the second interface, and those skilled in the art can set it according to actual needs.
[0054] The spacing between the first data positive pin and the adjacent pin can be greater than the spacing between the second data positive pin and the adjacent pin; the spacing between the second data negative pin and the adjacent pin can be greater than the spacing between the second data negative pin and the adjacent pin. Through this implementation, the difficulty of operating the universal serial bus interface pin of the touch chip during the circuit access process can be reduced, thereby improving the operating efficiency and the yield rate.
[0055] Optionally, continue to refer to Figure 2 The pin pad module 13 may also include a first transmission external data (TXD) pin (such as a first pin) of a transistor-transistor logic (TTL) level. Figure 2 The touch chip may also include a second transmission exchange data pin (such as a TTL_TXD pin shown in FIG. 1 ) of a transistor-transistor logic level. Figure 2 TTL'_TXD pin shown).
[0056] The first transmission exchange data pin is connected to the second transmission exchange data pin to lead out the second transmission exchange data pin.
[0057] Exemplarily, the first transmission exchange data pin can be directly connected to the second transmission exchange data pin of the TTL level of the touch chip; or, the first transmission exchange data pin is connected to the second transmission exchange data pin of the transistor-transistor logic level of the touch chip by accessing the third interface of the peripheral component module 12. The specific structure of the circuit connected to the third interface in the specific peripheral component module 12 can be set by those skilled in the art according to actual conditions, and will not be repeated here. Through this implementation method, corresponding components can be set in the peripheral component module 12 according to actual needs to meet the use requirements of the touch chip and expand the application scenarios of the chip module 1.
[0058] The spacing between the first transmission and exchange data pin and the adjacent pin can be greater than the spacing between the second transmission and exchange data pin and the adjacent pin. Through this implementation method, the operating difficulty of the TTL level transmission and exchange data pin of the touch chip during the circuit access process can be reduced, thereby improving the operating efficiency and the yield rate.
[0059] Optional, continue to refer to Figure 3 The pin pad module 13 may also include a first serial port pin at a 232 level (eg Figure 2 The touch chip may also include a second serial port pin of 232 level (such as RS232_TXD pin shown in FIG. Figure 2 RS232'_TXD pin shown).
[0060] In this case, the first serial port pin can be directly connected to the second serial port pin; or the first serial port pin can be connected to the second serial port pin by accessing the fourth interface of the peripheral component module 12. The specific structure of the circuit connected to the fourth interface in the specific peripheral component module 12 can be set by those skilled in the art according to actual conditions, and will not be repeated here. Through this implementation method, corresponding components can be set in the peripheral component module 12 according to actual needs to meet the use requirements of the touch chip and expand the application scenarios of the chip module 1.
[0061] The spacing between the first serial port pin and the adjacent pins may be greater than the spacing between the second serial port pin and the adjacent pins. This implementation method can reduce the difficulty of operating the serial port pin of the touch chip 232 level during the circuit access process, thereby improving the operating efficiency and the yield rate.
[0062] Optionally, the pin pad module further includes a first serial data line (SerialData, SDA) pin (such as Figure 2 The IIC_SDA pin shown in FIG. 1 ) and the first serial clock line (Serial Clock, SCL) pin (as shown in FIG. Figure 2 The touch chip may also include a first serial data line pin of the integrated circuit bus (such as Figure 2 IIC'_SDA pin shown), and the first serial clock line pin (as shown Figure 2 IIC'_SCL pin shown).
[0063] In this case, the first serial data line pin can be directly connected to the second serial data line pin to lead out the second serial data line pin; the first serial clock line pin can be directly connected to the second serial clock line pin to lead out the second serial clock line pin.
[0064] Alternatively, the first serial data line pin is connected to the second serial data line pin by accessing the fifth interface of the peripheral component module 12; the first serial clock line pin is connected to the second serial clock line pin by accessing the sixth interface of the peripheral component module 12. The specific structure of the circuit connected to the fifth interface and the sixth interface in the specific peripheral component module 12 can be set by those skilled in the art according to actual conditions, and will not be repeated here. Through this implementation method, corresponding components can be set in the peripheral component module 12 according to actual needs to meet the use requirements of the touch chip, such as increasing resistance to limit current and expanding the application scenario of the chip module 1.
[0065] Optionally, the chip module 11 may also include a first power pin, the peripheral component module 12 may include a power chip, and the pin pad module may also include a second power pin; the first end of the power chip is connected to the first power pin of the chip module 11, and the second end is connected to the second power pin of the pin pad module. The present application does not limit the specific type and structure of the above-mentioned power chip, and those skilled in the art can set it according to actual needs. The spacing between the second power pin and the adjacent pin is greater than the spacing between the first power pin and the adjacent pin. Through this implementation method, the operating difficulty of the touch chip in the process of connecting to the power circuit can be reduced, thereby improving the operating efficiency and the yield rate.
[0066] Optionally, the chip module 1 may also include a shielding cover module; wherein the shielding cover module covers the first side of the circuit board, and is used to cover the chip module 11 and the peripheral component module 12, and the first side is the side where the chip module 11 and the peripheral component module 12 are deployed; the pin pad module 13 is located on the second side of the circuit board, and the second side is the reverse side of the first side. The above-mentioned shielding cover module may, for example, include a metal shielding cover, or a shielding cover made of other materials, and the present application does not limit the material of the shielding cover module. The present application does not limit the specific shape of the shielding cover module, for example, it may be a square or a rectangle, or it may be consistent with the shape of the circuit board to achieve full coverage of the circuit board. Through this implementation method, the chip module 11 and the peripheral component module 12 can be protected by the shielding cover module, and the damage to the above two modules by the external environment can be avoided, thereby improving the availability of the chip module 1.
[0067] On the basis of the above embodiments, in actual application, the present application does not limit the size specifications of each component in the chip model, and those skilled in the art can set them according to actual conditions.
[0068] In some embodiments, the height (Height, H) of the chip module may be greater than 1.5 mm and less than 4 mm. The height mentioned here may also be referred to as thickness in some embodiments. Table 1 is a schematic table of the size specifications of a chip module provided by the present application. As shown in Table 1, the height of the chip module may be, for example, 1.85 mm.
[0069] Figure 3 The schematic diagram of the structure of the third chip module provided in this application is as follows: Figure 3 As shown, optionally, the main board may be a rectangle, and at least two sides have the same length (such as Figure 3 D1 and E1 shown are greater than 15 mm and less than 32 mm. As shown in Table 1, the motherboard on which the chip module is deployed can be square with a side length of 20.3 mm.
[0070] Optional, continue to refer to Figure 3 In some embodiments, the pin pad module may include four partitions (eg Figure 3 As shown in Z1-Z4), each partition is located at the edge area of the mainboard. The application does not limit the range covered by the edge area, for example, it can be the range covered by the edge of the mainboard translated toward the center of the mainboard by nmm, where n is greater than 0.
[0071] In the above case, each partition may include multiple pins. The spacing of the pins in each partition (e.g. Figure 3 q) shown in FIG. 1 can be greater than 0.2 mm and less than 1 cm. Continuing to refer to Table 1, the spacing between the pins of each partition can be, for example, 0.4 mm. Optionally, the width of each pin (e.g. Figure 3 b) shown is greater than 0.2 mm and less than 0.8 mm, for example, it can be 0.4 mm as shown in Table 1.
[0072] In some embodiments, the distance between two opposite partitions of the pin pad module (eg Figure 3 The distances D2 and E2 shown in Table 1 can be greater than 10 mm and less than 28 mm, for example, 17 mm as shown in Table 1. The distances between the two opposite partitions of the pin pad module and the sides away from each other (as shown in Table 1) can be greater than 10 mm and less than 28 mm, for example, 17 mm as shown in Table 1. Figure 3 D and E) shown are greater than 15 mm and less than 32 mm, for example, can be 20.3 mm as shown in Table 1.
[0073] Table 1
[0074] D 21.5mm D2 17mm E 21.5mm E2 17mm D1 20.3mm E1 20.3mm B 0.41mm H 2.85mm q 0.39mm
[0075] In the above embodiments, the description of each embodiment has its own emphasis. For the part not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0076] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the utility model disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.
[0077] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.
Claims
1. A chip module, characterized in that: The chip module is on the circuit board and includes: a chip module, a peripheral component module, and a pin pad module; The chip module is connected to the peripheral component module; The pin pad module is connected to the chip module and the peripheral component module to lead out the pins of the chip module and the interface of the peripheral component module; The spacing between at least one pair of adjacent pins in the pin pad module is greater than the spacing between adjacent pins in the chip module; The chip module includes a touch chip; the pin pad module includes a plurality of first drive channel pins and a plurality of first sensing channel pins; the touch chip includes a plurality of second drive channel pins and a plurality of second sensing channel pins; The plurality of first drive channel pins are connected to the plurality of second drive channel pins correspondingly to lead out the second drive channel pins; the distance between two adjacent first drive channel pins is greater than the distance between two adjacent second drive channel pins; The plurality of first sensing channel pins are connected to the plurality of second sensing channel pins correspondingly to lead out the second sensing channel pins; the distance between two adjacent first sensing channel pins is greater than the distance between two adjacent second sensing channel pins; The chip module also includes a first power pin, the peripheral component module includes a power chip, and the pin pad module also includes a second power pin; the pin pad module also includes a first data negative pin and a first data positive pin of a universal serial bus interface; the touch chip includes a second data negative pin and a second data positive pin.
2. The chip module according to claim 1, characterized in that: The first end of the power chip is connected to the first power pin of the chip module, and the second end is connected to the second power pin of the pin pad module; the spacing between the second power pin and the adjacent pin is greater than the spacing between the first power pin and the adjacent pin.
3. The chip module according to claim 1, characterized in that: The first data negative pin is connected to the second data negative pin by being connected to the first interface of the peripheral component module to lead out the second data negative pin; The first data positive pin is connected to the second data positive pin by accessing the second interface of the peripheral component module to lead out the second data positive pin.
4. The chip module according to claim 3, characterized in that: The pin pad module further includes a first transmission exchange data pin of a transistor-transistor logic level; the touch control chip further includes a second transmission exchange data pin of a transistor-transistor logic level; The first transmission exchange data pin and the second transmission exchange data pin are connected to lead out the second transmission exchange data pin.
5. The chip module according to claim 4, characterized in that: The first transmission exchange data pin is connected to the second transmission exchange data pin by accessing the third interface of the peripheral component module.
6. The chip module according to claim 1, characterized in that: The pin pad module further includes a first serial port pin of 232 level, and the touch chip further includes a second serial port pin of 232 level; The first serial port pin is connected to the second serial port pin by being connected to the fourth interface of the peripheral component module, so as to lead out the second serial port pin.
7. The chip module according to any one of claims 1 to 6, characterized in that: The pin pad module further includes a first serial data line pin of the integrated circuit bus and a first serial clock line pin; the touch control chip further includes a second serial data line pin of the integrated circuit bus and a second serial clock line pin; The first serial data line pin is connected to the second serial data line pin to lead out the second serial data line pin; the first serial clock line pin is connected to the second serial clock line pin to lead out the second serial clock line pin.
8. The chip module according to claim 7, characterized in that: The first serial data line pin is connected to the second serial data line pin by accessing the fifth interface of the peripheral component module; the first serial clock line pin is connected to the second serial clock line pin by accessing the sixth interface of the peripheral component module.
9. The chip module according to any one of claims 1 to 6, characterized in that: The height of the chip module is greater than 1.5 mm and less than 4 mm; the chip module also includes a mainboard, which is rectangular and has at least two sides with a length greater than 15 mm and less than 25 mm; the pin pad module and the chip module, as well as the peripheral component module, are located on different surfaces of the mainboard.
10. The chip module according to claim 9, characterized in that: The pin pad module includes 4 partitions, each of which is located in the edge area of the mainboard; each of the partitions includes multiple pins; the spacing between the pins in each partition is greater than 0.2mm and less than 1cm; the width of each pin is greater than 0.2mm and less than 0.6mm.
11. The chip module according to claim 10, characterized in that: The distance between two opposite partitions of the pin pad module is greater than 10 mm and less than 25 mm; the distance between two opposite partitions of the pin pad module that are away from each other is greater than 15 mm and less than 26 mm.