MOS transistor
By using a work function composite layer and a polysilicon gate structure composed of at least two metal compound film layers in the MOS transistor, the GIDL effect problem that the embedded MOS transistor occurs at the junction of the gate structure and drain region is achieved. The effect of reducing GIDL current improves the performance of the transistor.
Patent Information
- Application Number
- CN202421039137.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-13
- Publication Date
- 2025-02-25
- Estimated Expiration
- 2034-05-13
AI Technical Summary
Existing embedded MOS transistors are prone to severe GIDL effect at the junction of gate structure and drain region.
A work function composite layer consisting of at least two different metal compound film layers is used to cover the trench sidewalls and fill the polysilicon gate to form at least two layers of lateral adjustment material, adjust the gate work function and reduce the GIDL current.
Effectively improves the GIDL effect, reduces the GIDL current, thereby improving the performance of MOS transistors.
Smart Images
Figure CN222532102U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, in particular to a MOS transistor. Background Art
[0002] MOS (metal-oxide-semiconductor) transistors are one of the most important components in modern integrated circuits, such as Figure 1 As shown, the basic structure of a MOS transistor includes a substrate 1, a gate structure 2 located on the surface of the substrate 1, and source and drain regions located on both sides of the gate structure 2. In this structure, since the arrangement of the gate structure 2 is fixed, its miniaturization cost is high and the difficulty is great.
[0003] Therefore, in order to achieve miniaturization and place more MOS transistors in the same area, embedded MOS transistors were introduced, such as Figure 2 As shown, the embedded MOS transistor includes a substrate 1, a first trench in the substrate 1, a gate structure 3 formed in the first trench, the gate structure 3 includes a gate oxide layer and a work function layer sequentially located on the surface of the first trench, and a polysilicon gate filling the inner side of the work function layer; wherein the work function layer is a single metal alloy material layer. Current embedded MOS transistors are prone to severe GIDL (gate-induced drain leakage) effect at the junction of the gate structure and the drain region (i.e., A). Utility Model Content
[0004] The purpose of the utility model is to provide a MOS transistor which can improve the GIDL effect.
[0005] In order to solve the above problems, the utility model provides a MOS transistor, including a substrate, a first groove located in the substrate, a gate structure is arranged in the first groove, a source region and a drain region are arranged in the substrate on both sides of the gate structure, the gate structure includes a work function composite layer covering the sidewall of the first groove and a polysilicon gate filling the first groove inside the work function composite layer, and the work function composite layer is composed of at least two different metal compound film layers.
[0006] Optionally, the work function composite layer includes a first work function layer and a second work function layer, the first work function layer covers the sidewalls of the first groove, and the second work function layer covers the sidewalls of the first work function layer with uniform thickness, wherein the first work function layer is provided with a film layer of a metal compound material different from that of the second work function layer.
[0007] Furthermore, the material of the second work function layer is TiN.
[0008] Furthermore, the first work function layer includes at least one sub-work function layer, and all of the sub-work function layers directly or indirectly cover the sidewalls and bottom wall of the first trench with uniform thickness.
[0009] Furthermore, the material of at least one of the sub-work function layers is TiAl or TaN, and the material of the remaining sub-work function layers is any one of TiN, TiAl, and TaN.
[0010] Furthermore, the gate structure also includes a gate oxide layer, which covers the first trench, all the sub-work function layers directly or indirectly cover the gate oxide layer with uniform thickness, and the polysilicon gate fills the first trench inside the second work function layer.
[0011] Furthermore, the opening size of the first groove is
[0012] Furthermore, a ratio of the first work function layer to the opening size of the first groove is 1:5 to 1:30, and a ratio of the thickness of the second work function layer to the opening size of the first groove is 1:5 to 1:25.
[0013] Furthermore, a ratio of the first work function layer to the opening size of the first groove is 1:10 to 1:16, and a ratio of the thickness of the second work function layer to the opening size of the first groove is 1:9 to 1:15.
[0014] Optionally, an oxide layer is provided on the surface of the substrate, and the surface of the oxide layer is flush with the surface of the gate structure.
[0015] Compared with the prior art, the utility model has the following unexpected beneficial effects:
[0016] The utility model provides a MOS transistor, comprising a substrate, a first groove in the substrate, a gate structure arranged in the first groove, a source region and a drain region arranged in the substrate on both sides of the gate structure, the gate structure comprising a work function composite layer covering the sidewall of the first groove and a polysilicon gate filling the first groove inside the work function composite layer, the work function composite layer being composed of at least two different metal compound film layers; the utility model adjusts the gate work function by forming at least two lateral adjustment material layers on the outside of the polysilicon gate through the work function composite layer being composed of at least two different metal compound film layers, thereby reducing GIDL current and improving GIDL effect. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1-Figure 2 It is a schematic diagram of the structure of a MOS transistor in the prior art.
[0018] Figure 3 A schematic diagram of the structure of a MOS transistor provided in one embodiment of the utility model.
[0019] Figure 4 for Figure 3 An enlarged schematic diagram of the middle block diagram.
[0020] Figure 5-Figure 9 A schematic diagram of the structure of the MOS transistor provided in this embodiment during the preparation process.
[0021] Description of reference numerals:
[0022] Figure 1-Figure 2 Middle: 1-substrate; 2, 3-gate structure;
[0023] Figure 3-Figure 9 In the figure: 100 - substrate; 101 - first trench; 102 - second trench; 110 - oxide layer; 120 - stop layer; 130 - hard mask layer; 200 - gate structure; 210 - gate oxide layer; 221 - sub-work function layer; 222 - second work function layer; 230 - polysilicon gate. DETAILED DESCRIPTION
[0024] A MOS transistor of the present invention will be described in further detail below. The present invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation to the present invention.
[0025] For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would make the utility model confusing with unnecessary details. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just routine work for those skilled in the art.
[0026] In order to make the purpose and features of the utility model more obvious and easy to understand, the specific implementation of the utility model is further described below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model.
[0027] like Figure 3-Figure 4 See also Fig. 9The present embodiment provides a MOS transistor, including a substrate 100, a first trench 101 in the substrate 100, a gate structure 200 in the first trench 101, a source region and a drain region in the substrate 100 on both sides of the gate structure 200, the gate structure 200 includes a work function composite layer covering the sidewalls of the first trench 101 and a polysilicon gate 230 filling the first trench 101 inside the work function composite layer, the work function composite layer is composed of at least two different metal compound film layers, and the present embodiment forms at least two lateral adjustment material layers on the outside of the polysilicon gate 230 to adjust the gate work function, reduce GIDL current, and thus improve the GIDL effect.
[0028] In detail, the substrate 100 may be single crystal silicon, polycrystalline silicon or amorphous silicon; the substrate 100 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, etc.; the substrate 100 may be a composite structure, such as silicon on insulator; the substrate 100 may also be other semiconductor materials, which are not listed here one by one. In this embodiment, the material of the substrate 100 is silicon.
[0029] In this embodiment, the substrate 100 is provided with shallow trench isolation structures (STI) arranged at intervals, and the shallow trench isolation structures isolate adjacent active regions, and each of the first trenches 101 is located in one of the active regions, that is, a MOS transistor can be formed in each of the active regions. The opening size of the first trench 101 is
[0030] The substrate 100 can also be doped with different impurity ions according to the type of MOS transistor to be formed, so as to adjust the threshold voltage of the MOS transistor. When an N-type MOS transistor is to be formed, P-type ions are doped in the semiconductor substrate 100; when a P-type MOS transistor is to be formed, N-type ions are doped in the semiconductor substrate 100. An oxide layer 110 is provided on the surface of the substrate 100 outside the first trench 101, and the surface of the oxide layer 110 is flush with the surface of the gate structure 200. The oxide layer 110 can be a silicon dioxide layer.
[0031] A gate oxide layer 210 and a work function composite layer are sequentially arranged on the inner wall of the first trench 101, the gate oxide layer 210 covers the inner wall (side wall and bottom wall) of the first trench 101 with uniform thickness, the work function composite layer covers the gate oxide layer 210 on the inner wall of the first trench 101, and a polysilicon gate 230 is filled in the first trench 101 inside the work function composite layer.
[0032] The work function composite layer includes a first work function layer and a second work function layer 222, wherein the second work function layer 222 is disposed in contact with the polysilicon gate 230, and the second work function layer 222 covers the sidewall of the first work function layer with a uniform thickness. The material of the second work function layer 222 may be titanium nitride (TiN).
[0033] The first work function layer includes at least one sub-work function layer 221, each of which directly or indirectly covers the gate oxide layer 210 with a uniform thickness, and the thickness of each of the sub-work function layers 221 is a preset value, so that the thickness of each of the sub-work function layers 221 can be precisely controlled, so that the sub-work function layers 221 with precise and uniform thickness in this embodiment can further adjust the gate work function, thereby further reducing the GIDL current and improving the GIDL effect.
[0034] Among all the sub-work function layers 221, at least one of the sub-work function layers 221 is made of TiAl or TaN, and the remaining sub-work function layers 221 are made of any one of TiN, TiAl, and TaN, so as to provide a metal compound layer with good thermal stability and high conductivity. It should be noted that the thickness of each sub-work function layer 221 can be adjusted according to actual needs.
[0035] For example, the first work function layer includes a first sub-work function layer, and the first sub-work function layer covers the gate oxide layer 210 on the sidewall of the first trench 101 with a uniform thickness. For another example, the first work function layer includes a first sub-work function layer and a second sub-work function layer, and the first sub-work function layer covers the gate oxide layer 210 on the sidewall of the first trench 101 with a uniform thickness, and the second sub-work function layer covers the first sub-work function layer on the sidewall of the first trench 101 with a uniform thickness. For another example, the first work function layer includes a first sub-work function layer, a second sub-work function layer, and a third sub-work function layer, and the first sub-work function layer covers the gate oxide layer 210 on the sidewall of the first trench 101 with a uniform thickness, and the second sub-work function layer covers the first sub-work function layer on the sidewall of the first trench 101 with a uniform thickness, and the third sub-work function layer covers the second sub-work function layer on the sidewall of the first trench 101 with a uniform thickness.
[0036] An active region and a drain region are formed in the substrate 100 on both sides of the gate structure 200. Since the distance between the gate structure 200 and the drain region of this structure is smaller than the distance between the gate structure 200 and the drain region formed on the existing substrate 100, more MOS transistors can be placed in the same area, which has the advantage of miniaturization. At the same time, as the drain region voltage increases, the MOS transistor of this embodiment is more likely to experience band-to-band tunneling at the junction of the gate structure 200 and the drain region to cause the GIDL effect, and the gate structure 200 composed of at least two metal compound layers composed of at least one sub-work function layer 221 and the second work function layer 222 and the polysilicon gate 230 can effectively adjust the gate work function, thereby improving the GIDL effect and improving the performance of the MOS transistor.
[0037] MOS transistor GIDL current I D The formula is:
[0038]
[0039]
[0040] Among them, E S is the electric field at the silicon interface; A is the coefficient; B = 21.3 MV / cm; m* is the effective mass of the electron; V DG is the voltage difference from drain to source; V FB is the flat band voltage; tox is the thickness of the gate oxide layer; Eg is the energy gap of silicon; η is Planck's constant.
[0041] From the above formula, we can see that the GIDL current I D V FB The influence of E S With V FB is negatively correlated, and the work function recombination layer in this embodiment can reduce E S , thereby adjusting the gate work function to achieve the purpose of reducing the GIDL current.
[0042] The method for preparing the MOS transistor of this embodiment is as follows:
[0043] like Figure 5 As shown, first, a substrate 100 is provided, wherein shallow trench isolation structures (STI) arranged at intervals are provided in the substrate 100, wherein the shallow trench isolation structures isolate adjacent active regions, and wherein an oxide layer 110 and a stop layer 120 are provided on the surface of the substrate 100, wherein the material of the stop layer 120 is silicon nitride, and is used as a grinding stop layer 120. A first trench 101 is formed in each of the active regions, wherein the first trench 101 penetrates the stop layer 120 and the oxide layer 110, and stops in the substrate 100.
[0044] like Figure 6 As shown, a gate oxide layer 210 is formed on the inner wall of the first trench 101 by an oxidation process, and the gate oxide layer 210 can also repair the etching damage caused by etching the first trench 101; then all sub-work function layers 221 are formed by atomic deposition (ALD) to obtain each sub-work function layer 221 with a precise thickness; then a second work function material layer is filled inside all sub-work function layers 221, and the surface of the second work function material layer is lower than the surface of the stop layer 120. Among them, the ratio of the thickness of the first work function layer to the opening size of the first trench 101 is 1:5 to 1:30, and the ratio of the thickness of the second work function layer to the opening size of the first trench 101 is 1:5 to 1:25. Further, the ratio of the thickness of the first work function layer to the opening size of the first trench 101 is 1:10 to 1:16, and the ratio of the thickness of the second work function layer to the opening size of the first trench 101 is 1:9 to 1:15.
[0045] In this embodiment, taking the example that the first work function layer only includes the first sub-work function layer, the thickness of the first sub-work function layer is precisely controlled at x thickness, and the second work function layer 222 is precisely controlled at y thickness, wherein the ratio of the thickness x of the first sub-work function layer to the opening size of the first groove is 1:10 to 1:16, and the ratio of the thickness y of the second work function layer 222 to the opening size of the first groove is 1:9 to 1:15.
[0046] like Figure 7 As shown, a hard mask layer 130 is deposited on the stop layer 120, and the hard mask layer 130 covers the upper surfaces of all sub-work functions in the first trench 101 and the upper surface of the second work function material layer; the hard mask layer 130 is etched to expose a portion of the upper surface of the second work function material layer. The material of the hard mask layer 130 is silicon nitride.
[0047] like Figure 8 As shown, the second work function material layer is dry-etched using the hard mask as a mask to form a second work function layer 222 , wherein the second work function layer 222 has a sidewall with uniform thickness, and a second trench 102 is formed.
[0048] like Fig. 9 As shown, a polysilicon material is filled in the second trench 102 , and the polysilicon material covers the hard mask layer 130 ; and the polysilicon material on the hard mask layer 130 is removed by grinding.
[0049] like Figure 3As shown, the polysilicon material at the opening of the second trench 102 is dry-etched to reduce the height of the polysilicon material in the second trench 102 and form a polysilicon gate 230, the upper surface of which is flush with the surface of the oxide layer 110; finally, the hard mask layer 130 and the stop layer 120 are wet-etched.
[0050] The preparation of the above-mentioned MOS transistor is highly compatible with the CMOS process technology, and does not require additional masks and does not increase costs.
[0051] In summary, the utility model provides a MOS transistor, including a substrate, a first groove located in the substrate, a gate structure is arranged in the first groove, a source region and a drain region are arranged in the substrate on both sides of the gate structure, the gate structure includes a work function composite layer covering the sidewall of the first groove and a polysilicon gate filling the first groove inside the work function composite layer, and the work function composite layer is composed of at least two different metal compound film layers; the utility model has the following unexpected technical effect through the work function composite layer being composed of at least two different metal compound film layers: at least two lateral adjustment material layers can be formed on the outside of the polysilicon gate to adjust the gate work function, reduce GIDL current, and thus improve the GIDL effect.
[0052] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0053] It is understandable that, although the utility model has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the utility model. For any technician familiar with the art, without departing from the scope of the technical solution of the utility model, the above disclosed technical content can be used to make many possible changes and modifications to the technical solution of the utility model, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the utility model without departing from the content of the technical solution of the utility model still falls within the scope of protection of the technical solution of the utility model.
Claims
1. A MOS transistor, characterized in that: It includes a substrate, a first trench in the substrate, a gate structure is arranged in the first trench, a source region and a drain region are arranged in the substrate on both sides of the gate structure, the gate structure includes a work function composite layer covering the sidewall of the first trench and a polysilicon gate filling the first trench inside the work function composite layer, and the work function composite layer is composed of at least two different metal compound film layers.
2. The MOS transistor according to claim 1, wherein: The work function composite layer includes a first work function layer and a second work function layer, wherein the first work function layer covers the sidewalls of the first groove, and the second work function layer covers the sidewalls of the first work function layer with uniform thickness, wherein the first work function layer is provided with a film layer of a metal compound material different from that of the second work function layer.
3. The MOS transistor according to claim 2, wherein: The material of the second work function layer is TiN.
4. The MOS transistor according to claim 2, wherein: The first work function layer includes at least one sub-work function layer, and all of the sub-work function layers directly or indirectly cover the sidewalls and bottom wall of the first trench with uniform thickness.
5. The MOS transistor according to claim 4, characterized in that The material of at least one sub-work function in all the sub-work function layers is TiAl or TaN, and the material of the remaining sub-work functions is any one of TiN, TiAl and TaN.
6. The MOS transistor according to claim 4, wherein: The gate structure further includes a gate oxide layer, which covers the first trench. All the sub-work function layers directly or indirectly cover the gate oxide layer with uniform thickness. The polysilicon gate fills the first trench inside the second work function layer.
7. The MOS transistor according to claim 1, wherein: An oxide layer is disposed on the surface of the substrate, and the surface of the oxide layer is flush with the surface of the gate structure.