Lead frame and Cascode packaging structure

Abstract

The utility model discloses a lead frame and a Cascode packaging structure, and the packaging structure comprises a frame body, an insulating layer located on the frame body, a conductive layer located on the insulating layer, a pin layer located on the conductive layer, and an MOSFET chip and an HEMT chip which are packaged on the conductive layer. The conducting layer comprises a first conducting layer and a second conducting layer which are distributed at an interval, and a third conducting layer and a fourth conducting layer which are positioned on two sides of the first conducting layer and the second conducting layer, the MOSFET chip is packaged on the first conducting layer, the HEMT chip and the first pin layer are packaged on the second conducting layer, the second pin layer is packaged on the third conducting layer, and the fourth conducting layer is packaged on the third conducting layer. And the third pin layer is packaged on the fourth conductive layer. According to the invention, the Cascode packaging of the HEMT chip and the MOSFET chip can be realized in one lead frame, the length of the bonding wire and the current path are shortened to the greatest extent in the Cascode packaging structure, and the loss is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and particularly relates to a lead frame and a Cascode packaging structure. Background Art

[0002] With the continuous development of power electronics technology and communication electronics technology, the disadvantages of traditional silicon-based semiconductor material devices in application fields such as high voltage, high frequency, and high power have become increasingly obvious. In recent years, the third-generation semiconductor materials have been widely studied and applied. As a third-generation semiconductor material, gallium nitride is also known as a wide-bandgap semiconductor material because its bandgap width is greater than 2.2 eV. In addition to a larger bandgap width, it also has advantages such as a high breakdown electric field (more resistant to high voltage), a high electron saturation drift rate (higher power output), and good temperature resistance characteristics. Therefore, gallium nitride materials are also widely used in power semiconductor devices.

[0003] See Figure 1 The circuit schematic diagram of the Cascode structure (common-source common-gate cascade structure) in the prior art is shown. The Cascode structure has the characteristic of a large output impedance. It cascades a GaN HEMT (gallium nitride high electron mobility transistor) chip and a Si MOSFET (silicon metal-oxide-semiconductor field-effect transistor) chip. The source of the GaN HEMT chip is connected to the drain of the Si MOSFET chip. Among them, a depletion-mode GaN HEMT chip is used for the high-voltage part, and a Si MOSFET chip is used for the low-voltage part.

[0004] The specific working principle of the Cascode structure is as follows: 1. When the whole device is in the off state (Vg < Vth), when a small working voltage is applied across the source and drain (Vds is less than the threshold voltage of the GaN HEMT), the Si MOSFET is turned off and the GaN HEMT is turned on; when a working voltage greater than the HEMT threshold voltage is applied across the source and drain, the Si MOSFET is turned off and the GaN HEMT is turned off, thereby taking advantage of the high blocking voltage characteristic of gallium nitride to ensure that the Si MOSFET will not be broken down by a large voltage. 2. When the device is in the on state, the Si MOSFET is turned on, so that Figure 1 the voltage at point A is equal to the voltage at the S terminal (that is, the gate voltage of the GaN HEMT), and the gate voltage drop is zero, thereby turning on the GaN HEMT.

[0005] The Cascode structure works stably at high temperatures in applications. The GaN device has a good quality factor (RON*QG) and excellent performance. Cascode uses Si devices as gates, has high threshold voltages, a large adjustable range, safe applications, and is not susceptible to interference. The Cascode gate has a large withstand voltage range, large gate drive margin, good reliability, no gate clamping circuit, and no negative voltage shutdown. It is compatible with traditional Si MOSFET gate drivers, with low R&D investment costs, short cycles, and quick results. Due to the good gate reliability, the TO series package with better heat dissipation can be used, which has great advantages in high-power applications.

[0006] The TO series package is a common plug-in package widely used in systems such as high-power transistors, small and medium-scale integrated circuits, etc. It is usually a single-row plug-in, and can generally lead out 3, 5, or 7 pins. Among them, 3-pin devices are the most common, and specific models include TO-252, TO-247, TO-220, etc. However, the existing lead frame is composed of a layer of metal, and the back of the GaN HEMT chip and the Si MOSFET chip in the Cascode structure cannot be connected, so the two chips cannot be directly packaged in an ordinary lead frame. Moreover, the existing lead frame can only package chips of specific models or sizes, and cannot be compatible with multiple different models and sizes of chips.

[0007] Therefore, in view of the above technical problems, it is necessary to provide a lead frame and cascode packaging structure. Summary of the invention

[0008] In view of this, an object of the present invention is to provide a lead frame and a cascode packaging structure.

[0009] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0010] A lead frame, comprising a frame body, an insulating layer located on the frame body, a conductive layer located on the insulating layer, and a pin layer located on the conductive layer, wherein the conductive layer comprises a first conductive layer and a second conductive layer distributed at intervals, and a third conductive layer and a fourth conductive layer located on both sides of the first conductive layer and the second conductive layer, wherein the first conductive layer is used to encapsulate a MOSFET chip, the second conductive layer is used to encapsulate a HEMT chip and a first pin layer, the third conductive layer is used to encapsulate a second pin layer, and the fourth conductive layer is used to encapsulate the third pin layer.

[0011] In one embodiment, the surface of the first conductive layer includes a first packaging area for packaging MOSFET chips and a first bonding area for bonding, the surface of the second conductive layer includes a second packaging area for packaging HEMT chips, a second bonding area for bonding, and a first pin area for packaging a first pin layer, the third conductive layer includes a third bonding area for bonding, a second pin area for packaging a second pin layer, and a first transmission area between the third bonding area and the second pin area, and the fourth conductive layer includes a fourth bonding area for bonding, a third pin area for packaging a third pin layer, and a second transmission area between the fourth bonding area and the third pin area.

[0012] In one embodiment, the first packaging area is adjacent to the second packaging area, the third bonding area and the fourth bonding area are respectively located on both sides of the first conductive layer, the second bonding area and the first pin area are located between the second pin area and the third pin area, and the first transmission area and the second transmission area are respectively located on both sides of the second packaging area.

[0013] In one embodiment, the first packaging area has a length of 2.5 mm to 4.5 mm and a width of 0.5 mm to 1.5 mm, and the second packaging area has a length of 4 mm to 6 mm and a width of 3 mm to 4 mm.

[0014] Another embodiment of the present invention provides a technical solution as follows:

[0015] A cascode packaging structure, comprising a frame body, an insulating layer located on the frame body, a conductive layer located on the insulating layer, a pin layer located on the conductive layer, and a MOSFET chip and a HEMT chip packaged on the conductive layer, wherein the conductive layer comprises a first conductive layer and a second conductive layer distributed at intervals, and a third conductive layer and a fourth conductive layer located on both sides of the first conductive layer and the second conductive layer, the MOSFET chip is packaged on the first conductive layer, the HEMT chip and the first pin layer are packaged on the second conductive layer, the second pin layer is packaged on the third conductive layer, and the third pin layer is packaged on the fourth conductive layer.

[0016] In one embodiment, the surface of the first conductive layer includes a first packaging area for packaging MOSFET chips and a first bonding area for bonding, the surface of the second conductive layer includes a second packaging area for packaging HEMT chips, a second bonding area for bonding, and a first pin area for packaging a first pin layer, the third conductive layer includes a third bonding area for bonding, a second pin area for packaging a second pin layer, and a first transmission area between the third bonding area and the second pin area, and the fourth conductive layer includes a fourth bonding area for bonding, a third pin area for packaging a third pin layer, and a second transmission area between the fourth bonding area and the third pin area.

[0017] In one embodiment, the first packaging area is adjacent to the second packaging area, the third bonding area and the fourth bonding area are respectively located on both sides of the first conductive layer, the second bonding area and the first pin area are located between the second pin area and the third pin area, and the first transmission area and the second transmission area are respectively located on both sides of the second packaging area.

[0018] In one embodiment, the gate and source of the MOSFET chip are located on the upper surface of the MOSFET chip, the drain is located on the lower surface of the MOSFET chip, and the gate, source and drain of the HEMT chip are all located on the upper surface of the HEMT chip;

[0019] The gate of the MOSFET chip is electrically connected to the third bonding area through the first bonding wire, the source of the MOSFET chip is electrically connected to the fourth bonding area through the second bonding wire, and the source of the MOSFET chip is electrically connected to the gate of the HEMT chip through the third bonding wire, the source of the HEMT chip is electrically connected to the first bonding area through the fourth bonding wire, and the drain of the HEMT chip is electrically connected to the second bonding area through the fifth bonding wire.

[0020] In one embodiment, the length of the first packaging area is 2.5 mm to 4.5 mm, and the width is 0.5 mm to 1.5 mm; the length of the second packaging area is 4 mm to 6 mm, and the width is 3 mm to 4 mm; the length of the MOSFET chip is 1 mm to 2 mm, and the width is 0.4 mm to 1.4 mm; the length of the HEMT chip is 2 mm to 5 mm, and the width is 1 mm to 3 mm.

[0021] In one embodiment, the MOSFET chip is a Si MOSFET chip, and the HEMT chip is a GaN HEMT chip; and / or,

[0022] The MOSFET chip is packaged on the first conductive layer by conductive adhesive, and the HEMT chip is packaged on the second conductive layer by conductive adhesive.

[0023] The present invention has the following beneficial effects:

[0024] The lead frame of the present invention can realize Cascode packaging of HEMT chips and MOSFET chips in one lead frame through the design of the insulating layer and the conductive layer, and is suitable for chips of different models and sizes; the Cascode packaging structure shortens the bonding wire length and the current path to the greatest extent, thereby reducing the loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 It is a circuit schematic diagram of a Cascode structure (common source and common gate cascade structure) in the prior art;

[0027] Figure 2 is a schematic diagram of the planar structure of the lead frame in Embodiment 1 of the present invention;

[0028] Figure 3 is a schematic side view of the lead frame in Embodiment 1 of the present invention;

[0029] Figure 4 Schematic diagram of the planar structure of the conductive layer in Example 1 of the present invention;

[0030] Figure 5 This is a schematic diagram of the Cascode packaging structure in Example 2 of the present invention. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0032] The present invention discloses a lead frame, comprising a frame body, an insulating layer located on the frame body, a conductive layer located on the insulating layer and a pin layer located on the conductive layer, wherein the conductive layer comprises a first conductive layer and a second conductive layer which are spaced apart, and a third conductive layer and a fourth conductive layer which are located on both sides of the first conductive layer and the second conductive layer, wherein the first conductive layer is used for encapsulating a MOSFET chip, the second conductive layer is used for encapsulating a HEMT chip and a first pin layer, the third conductive layer is used for encapsulating a second pin layer, and the fourth conductive layer is used for encapsulating the third pin layer.

[0033] The present invention also discloses a Cascode packaging structure, comprising a frame body, an insulating layer located on the frame body, a conductive layer located on the insulating layer, a pin layer located on the conductive layer, and a MOSFET chip and a HEMT chip packaged on the conductive layer, wherein the conductive layer comprises a first conductive layer and a second conductive layer distributed at intervals, and a third conductive layer and a fourth conductive layer located on both sides of the first conductive layer and the second conductive layer, the MOSFET chip is packaged on the first conductive layer, the HEMT chip and the first pin layer are packaged on the second conductive layer, the second pin layer is packaged on the third conductive layer, and the third pin layer is packaged on the fourth conductive layer.

[0034] The present invention is further described below in conjunction with specific embodiments.

[0035] Embodiment 1:

[0036] Ginseng Figures 2 to 4 As shown, the lead frame in this embodiment includes a frame body 10, an insulating layer 20 located on the frame body, a conductive layer 30 located on the insulating layer, and a pin layer 40 located on the conductive layer. The frame body 10 is a metal layer, which is the base of the entire structure, and its main function is to dissipate heat and subsequently connect to the PCB board. The conductive layer 30 is formed on the upper surface of the insulating layer 20, and is generally a silver-plated layer. The chip is mounted on the conductive layer 30 through a conductive adhesive (such as conductive silver adhesive, etc.), and the pin layer 40 is mounted on the conductive layer 30 through a conductive adhesive.

[0037] Specifically, refer to Figure 3 As shown, the conductive layer 30 in this embodiment includes a first conductive layer 31 and a second conductive layer 32 that are spaced apart, and a third conductive layer 33 and a fourth conductive layer 34 located on both sides of the first conductive layer and the second conductive layer. The first conductive layer 31 is used to encapsulate the MOSFET chip, the second conductive layer 32 is used to encapsulate the HEMT chip and the first pin layer 41, the third conductive layer 33 is used to encapsulate the second pin layer 42, and the fourth conductive layer 34 is used to encapsulate the third pin layer 43.

[0038] The surface of the first conductive layer 31 includes a first packaging area 311 for packaging MOSFET chips and a first bonding area 312 for bonding. The surface of the second conductive layer 32 includes a second packaging area 321 for packaging HEMT chips, a second bonding area 322 for bonding, and a first pin area 323 for packaging the first pin layer. The third conductive layer 33 includes a third bonding area 331 for bonding, a second pin area 332 for packaging the second pin layer, and a first transmission area 333 located between the third bonding area and the second pin area. The fourth conductive layer 34 includes a fourth bonding area 341 for bonding, a third pin area 342 for packaging the third pin layer, and a second transmission area 343 located between the fourth bonding area and the third pin area.

[0039] In this embodiment, the first packaging area 311 is adjacent to the second packaging area 321, the third bonding area 331 and the fourth bonding area 341 are respectively located on both sides of the first conductive layer 31, the second bonding area 322 and the first pin area 323 are located between the second pin area 332 and the third pin area 342, and the first transmission area 333 and the second transmission area 342 are respectively located on both sides of the second packaging area 321.

[0040] In the present invention, the length of the first packaging area 311 is 2.5 mm to 4.5 mm, and the width is 0.5 mm to 1.5 mm. The length of the second packaging area 321 is 4 mm to 6 mm, and the width is 3 mm to 4 mm.

[0041] Exemplarily, in this embodiment, the size of the first conductive layer is 3.5mm*1mm, the size of the first packaging area is 1.8mm*1mm, the size of the second packaging area is 5mm*3.4mm, the length of the second wiring area is 2.8mm, the length of the third conductive layer and the fourth conductive layer is 4.8mm, the size of the first pin area, the second pin area, and the third pin area is 0.9mm*1.1mm, and the size of the entire insulating layer is 7.5mm*6mm.

[0042] Embodiment 2:

[0043] Ginseng Figure 5 Combined with Figure 2 to Figure 4 As shown, the Cascode packaging structure in this embodiment includes a frame body 10, an insulating layer 20 located on the frame body, a conductive layer 30 located on the insulating layer, a pin layer 40 located on the conductive layer, and a MOSFET chip and a HEMT chip packaged on the conductive layer. Among them, the design of the frame body 10, the insulating layer 20, the conductive layer 30 and the pin layer 40 is exactly the same as that in Example 1, and will not be repeated here.

[0044] The MOSFET chip in this embodiment is packaged on the first packaging area 311 in the first conductive layer 31, the HEMT chip is packaged on the second packaging area 312 in the second conductive layer 32, the first pin layer 41 is packaged on the first pin area 323 in the second conductive layer, the second pin layer 42 is packaged on the second pin area 332 in the third conductive layer 33, and the third pin layer 43 is packaged on the third pin area 342 in the fourth conductive layer 34.

[0045] Furthermore, the MOSFET chip is packaged on the first packaging area 311 by means of conductive adhesive, and the HEMT chip is packaged on the second packaging area 312 by means of conductive adhesive.

[0046] Exemplarily, the MOSFET chip in this embodiment is a Si MOSFET chip, and the HEMT chip is a GaN HEMT chip.

[0047] In this embodiment, the gate (G_Si) and source (S_Si) of the Si MOSFET chip are located on the upper surface of the Si MOSFET chip, the drain (D_Si) is located on the lower surface of the Si MOSFET chip, and the gate (G_GaN), source (S_GaN) and drain (D_GaN) of the GaN HEMT chip are all located on the upper surface of the GaN HEMT chip.

[0048] Specifically, in this embodiment, the gate (G_Si) of the Si MOSFET chip is electrically connected to the third bonding area 331 through the first bonding wire 51, the source (S_Si) of the Si MOSFET chip is electrically connected to the fourth bonding area 341 through the second bonding wire 52, and the source (S_Si) of the Si MOSFET chip is electrically connected to the gate (G_GaN) of the GaN HEMT chip through the third bonding wire 53, the source (S_GaN) of the GaN HEMT chip is electrically connected to the first bonding area 312 through the fourth bonding wire 54 (the first bonding area 312 is connected to the drain (D_Si) on the back of the Si MOSFET chip), and the drain (D_GaN) of the GaN HEMT chip is electrically connected to the second bonding area 322 through the fifth bonding wire 55.

[0049] In the present invention, the length of the Si MOSFET chip is 1 mm to 2 mm, the width is 0.4 mm to 1.4 mm, and the length of the GaN HEMT chip is 2 mm to 5 mm, the width is 1 mm to 3 mm. For example, the size of the Si MOSFET chip in this embodiment is 1.5 mm*1 mm, and the size of the GaN HEMT chip is 5 mm*2 mm.

[0050] Based on the characteristics of the cascode structure, the drain of the GaN HEMT chip and the drain of the Si MOSFET chip cannot be short-circuited, so the conductive layer on the surface of the insulating layer is designed as follows: Figure 4 The irregular pattern shown. The conductive path between the source of the GaN HEMT chip and the drain of the SiMOSFET chip needs to be connected to form a SW node, but the drain of the Si MOSFET chip is located on the back of the chip, so the source of the GaN HEMT chip and the back of the Si MOSFET chip are connected by bonding wires, and this design minimizes the bonding wires, which greatly reduces SW oscillation.

[0051] In addition, the HEMT chip placement area is large, and chips of different models and sizes can be placed to achieve the purpose of compatible design; the MOSFET chip placement area is similar, and it is agreed to be compatible with different models of MOSFET.

[0052] In addition, the three external pins of the lead frame are G, D, and S. The gate and source of the MOSFET chip are connected to the pins of the frame. Due to the placement of the chip, the bonding wire cannot be directly bonded to the pins, so two extension areas are added to the conductive layer to complete the wire bonding function. Through the design of the present invention, it is possible to achieve compatibility with multiple chips in a limited area, and to minimize the length of the bonding wire and the current path ( Figure 1 The dotted line path in the middle reduces the loss.

[0053] It can be seen from the above technical solutions that the present invention has the following advantages:

[0054] The lead frame of the present invention can realize Cascode packaging of HEMT chips and MOSFET chips in one lead frame through the design of the insulating layer and the conductive layer, and is suitable for chips of different models and sizes; the Cascode packaging structure shortens the bonding wire length and the current path to the greatest extent, thereby reducing the loss.

[0055] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0056] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A lead frame, characterized in that: The lead frame includes a frame body, an insulating layer located on the frame body, a conductive layer located on the insulating layer, and a pin layer located on the conductive layer. The conductive layer includes a first conductive layer and a second conductive layer that are spaced apart, and a third conductive layer and a fourth conductive layer that are located on both sides of the first conductive layer and the second conductive layer. The first conductive layer is used to encapsulate a MOSFET chip, the second conductive layer is used to encapsulate a HEMT chip and a first pin layer, the third conductive layer is used to encapsulate a second pin layer, and the fourth conductive layer is used to encapsulate the third pin layer.

2. The lead frame according to claim 1, characterized in that: The surface of the first conductive layer includes a first packaging area for packaging MOSFET chips and a first bonding area for bonding, the surface of the second conductive layer includes a second packaging area for packaging HEMT chips, a second bonding area for bonding, and a first pin area for packaging the first pin layer, the third conductive layer includes a third bonding area for bonding, a second pin area for packaging the second pin layer, and a first transmission area between the third bonding area and the second pin area, and the fourth conductive layer includes a fourth bonding area for bonding, a third pin area for packaging the third pin layer, and a second transmission area between the fourth bonding area and the third pin area.

3. The lead frame according to claim 2, characterized in that: The first packaging area is adjacent to the second packaging area, the third bonding area and the fourth bonding area are respectively located on both sides of the first conductive layer, the second bonding area and the first pin area are located between the second pin area and the third pin area, and the first transmission area and the second transmission area are respectively located on both sides of the second packaging area.

4. The lead frame according to claim 2, characterized in that: The first packaging area has a length of 2.5 mm to 4.5 mm and a width of 0.5 mm to 1.5 mm, and the second packaging area has a length of 4 mm to 6 mm and a width of 3 mm to 4 mm.

5. A Cascode packaging structure, characterized in that: The packaging structure includes a frame body, an insulating layer located on the frame body, a conductive layer located on the insulating layer, a pin layer located on the conductive layer, and a MOSFET chip and a HEMT chip packaged on the conductive layer. The conductive layer includes a first conductive layer and a second conductive layer distributed at intervals, and a third conductive layer and a fourth conductive layer located on both sides of the first conductive layer and the second conductive layer. The pin layer includes a first pin layer, a second pin layer, and a third pin layer. The MOSFET chip is packaged on the first conductive layer, the HEMT chip and the first pin layer are packaged on the second conductive layer, the second pin layer is packaged on the third conductive layer, and the third pin layer is packaged on the fourth conductive layer.

6. The Cascode packaging structure according to claim 5, characterized in that: The surface of the first conductive layer includes a first packaging area for packaging MOSFET chips and a first bonding area for bonding, the surface of the second conductive layer includes a second packaging area for packaging HEMT chips, a second bonding area for bonding, and a first pin area for packaging the first pin layer, the third conductive layer includes a third bonding area for bonding, a second pin area for packaging the second pin layer, and a first transmission area between the third bonding area and the second pin area, and the fourth conductive layer includes a fourth bonding area for bonding, a third pin area for packaging the third pin layer, and a second transmission area between the fourth bonding area and the third pin area.

7. The Cascode packaging structure according to claim 6, characterized in that: The first packaging area is adjacent to the second packaging area, the third bonding area and the fourth bonding area are respectively located on both sides of the first conductive layer, the second bonding area and the first pin area are located between the second pin area and the third pin area, and the first transmission area and the second transmission area are respectively located on both sides of the second packaging area.

8. The Cascode packaging structure according to claim 6, characterized in that: The gate and source of the MOSFET chip are located on the upper surface of the MOSFET chip, the drain is located on the lower surface of the MOSFET chip, and the gate, source and drain of the HEMT chip are all located on the upper surface of the HEMT chip; The gate of the MOSFET chip is electrically connected to the third bonding area through the first bonding wire, the source of the MOSFET chip is electrically connected to the fourth bonding area through the second bonding wire, and the source of the MOSFET chip is electrically connected to the gate of the HEMT chip through the third bonding wire, the source of the HEMT chip is electrically connected to the first bonding area through the fourth bonding wire, and the drain of the HEMT chip is electrically connected to the second bonding area through the fifth bonding wire.

9. The Cascode packaging structure according to claim 6, characterized in that: The length of the first packaging area is 2.5 mm to 4.5 mm, and the width is 0.5 mm to 1.5 mm. The length of the second packaging area is 4 mm to 6 mm, and the width is 3 mm to 4 mm. The length of the MOSFET chip is 1 mm to 2 mm, and the width is 0.4 mm to 1.4 mm. The length of the HEMT chip is 2 mm to 5 mm, and the width is 1 mm to 3 mm.

10. The Cascode packaging structure according to claim 5, characterized in that: The MOSFET chip is a SiMOSFET chip, and the HEMT chip is a GaN HEMT chip; and / or, The MOSFET chip is packaged on the first conductive layer by conductive adhesive, and the HEMT chip is packaged on the second conductive layer by conductive adhesive.

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