SD NAND based on substrate type packaging structure
By setting the memory chip above the controller chip and setting the substrate fingers below it, the problem of large package area of the existing SD NAND is solved, and the effect of reducing the number of substrate fingers and reducing the package area is achieved.
Patent Information
- Application Number
- CN202323203781.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-27
- Publication Date
- 2025-03-04
- Estimated Expiration
- 2033-11-27
AI Technical Summary
The existing SD NAND needs to be equipped with at least two rows of pads on the periphery of the memory chip, resulting in a large package area.
By setting the memory chip above the controller chip and setting the substrate fingers below it, the number of substrate fingers on the periphery of the memory chip is reduced, thereby reducing the overall package area.
It effectively reduces the number of substrate fingers on the periphery of the memory chip and reduces the overall package area of SD NAND.
Smart Images
Figure CN222564251U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of SD NAND, and particularly relates to an SD NAND based on a substrate type packaging structure. Background Art
[0002] Existing SD NAND is usually packaged in a substrate-type packaging structure, that is, the existing SD NAND stacks the memory chip and the controller chip on the substrate. Specifically, since the coverage area of the controller chip is much smaller than the coverage area of the memory chip, the controller chip is placed on the memory chip, and the memory chip is placed on the substrate. The memory chip and the controller chip can be bonded to the substrate fingers respectively, and the interconnection between the controller chip and the memory chip, and the interconnection between the controller chip and the PIN external output signal are all achieved through the internal wiring of the substrate. The memory chip and the controller chip can also be interconnected by PAD (pad) to PAD bonding, and the interconnection between the controller chip and the PIN external output chip is brought out by PAD and substrate finger bonding.
[0003] According to the definition of 4 PIN external output signals on the left and right sides of SD NAND, the controller chip needs to be provided with a row of pads for connecting PIN external output signals on the left and right sides respectively and a row of pads for interconnecting with the memory chip on either side of the upper and lower sides, that is, the controller chip includes at least three rows of pads, and the NAND chip includes at least one row of pads. If the memory chip and the controller chip are directly interconnected, the number of substrate fingers on the substrate located outside the memory chip is two rows; if the memory chip and the controller chip are wired with the substrate fingers respectively, the number of substrate fingers on the substrate located outside the memory chip is four rows. It can be seen from this that the existing SD NAND needs to be provided with at least two rows of pads on the periphery of the memory chip. Since the pads provided on the periphery of the memory chip need to occupy additional packaging area, the existing SD NAND has the problem of a large additional packaging area due to the need to provide at least two rows of pads on the periphery of the memory chip, resulting in a large overall packaging area of the SD NAND.
[0004] Therefore, the existing technology needs to be improved and developed. Utility Model Content
[0005] The purpose of the present application is to provide an SD NAND based on a substrate-type packaging structure, which can effectively reduce the number of substrate fingers arranged around the periphery of a memory chip, thereby effectively reducing the overall packaging area of the SD NAND.
[0006] The present application provides an SD NAND based on a substrate packaging structure, which includes:
[0007] A substrate having a plurality of rows of substrate fingers on its surface, wherein one row of substrate fingers is arranged at an edge of the substrate;
[0008] A controller chip is disposed on the substrate, and its pads are electrically connected to other substrate fingers on the substrate through bonding wires;
[0009] A dummy chip, fixed on the substrate and located on one side of the controller chip;
[0010] The memory chip is fixed on the dummy chip and is located above the controller chip, and its pad is electrically connected to the substrate finger located at the edge of the substrate through a welding wire.
[0011] The present application provides an SD NAND based on a substrate packaging structure, including a controller chip arranged on a substrate and a memory chip arranged on the controller chip. Since the coverage area of the memory chip is much larger than the coverage area of the controller chip and the memory chip is arranged above the controller chip, the substrate fingers originally located outside the memory chip for connecting the controller chip can be arranged below the memory chip, that is, the memory chip of the SD NAND can cover other substrate fingers electrically connected to the pads of the controller chip, that is, the SD NAND only needs to arrange a row of substrate fingers electrically connected to the pads of the memory chip on the periphery of the memory chip. Therefore, the SD NAND can effectively reduce the number of substrate fingers arranged on the periphery of the memory chip, thereby effectively reducing the overall packaging area of the SD NAND.
[0012] Furthermore, the controller chip includes a horizontal row of pads, a first column of pads and a second column of pads, the surface of the substrate has a first substrate finger, a second substrate finger and a third substrate finger, the horizontal row of pads is electrically connected to the first substrate finger through a welding wire, the first column of pads is electrically connected to the second substrate finger through a welding wire, and the second column of pads is electrically connected to the third substrate finger through a welding wire.
[0013] Further, the first substrate finger is located at one side of the horizontal row of pads, the second substrate finger is located at one side of the first column of pads, and the third substrate finger is located at one side of the second column of pads.
[0014] This technical solution is equivalent to reducing the distance between the first substrate finger and the horizontal row of pads, the distance between the second substrate finger and the first column of pads, and the distance between the third substrate finger and the second column of pads. Therefore, this technical solution can effectively reduce the length of the bonding wire required to electrically connect the pads of the controller chip to the substrate fingers.
[0015] Furthermore, the dummy chip is in a rectangular parallelepiped structure, and the dummy chip has the first substrate finger and the edge of the memory chip as a boundary.
[0016] This technical solution sets the dummy film as a rectangular structure, and the dummy film uses the first substrate finger and the edge of the memory chip as the boundary. Therefore, this technical solution can effectively increase the overlap rate between the dummy film and the memory chip. Since the higher the overlap rate between the dummy film and the memory chip, the larger the support area of the dummy film, this technical solution can also effectively improve the support effect of the dummy film and the overall stability of the SD NAND.
[0017] Furthermore, the memory chip includes a third row of pads, the surface of the substrate also has a fourth substrate finger, the fourth substrate finger is arranged at the edge of the substrate, and the third row of pads is electrically connected to the fourth substrate finger through a bonding wire.
[0018] Furthermore, the fourth substrate finger is located at an edge of the substrate close to the third row of pads.
[0019] This technical solution sets the fourth substrate finger at the edge of the substrate close to the third row of pads, that is, this technical solution is equivalent to reducing the distance between the fourth substrate finger and the third row of pads. Therefore, this technical solution can effectively reduce the length of the bonding wire required to electrically connect the pad of the memory chip to the substrate finger.
[0020] Furthermore, the minimum distance between the controller chip and the edge of the substrate is 0.15-0.25 mm.
[0021] Furthermore, the minimum distance between the memory chip and the edge of the substrate is 0.05-0.15 mm.
[0022] Further, the dummy sheet includes an aluminum sheet.
[0023] Furthermore, the thickness of the dummy chip is greater than the sum of the thickness of the controller chip and the bonding height of the controller chip.
[0024] Since the thickness of the dummy film of this technical solution is greater than the sum of the thickness of the controller chip and the bonding height of the controller chip, and the height of the dummy film is equal to the distance between the memory chip and the substrate, this technical solution can effectively avoid the situation where the bonding of the controller chip is affected by the small distance between the memory chip and the substrate.
[0025] As can be seen from the above, the utility model provides an SD NAND based on a substrate-type packaging structure, including a controller chip arranged on a substrate and a memory chip arranged on the controller chip. Since the coverage area of the memory chip is much larger than the coverage area of the controller chip, and the memory chip is arranged above the controller chip, the substrate fingers originally located outside the memory chip for connecting the controller chip can be arranged below the memory chip, that is, the memory chip of the SD NAND can cover other substrate fingers electrically connected to the pads of the controller chip, that is, the SD NAND only needs to arrange a row of substrate fingers electrically connected to the pads of the memory chip on the periphery of the memory chip. Therefore, the SD NAND can effectively reduce the number of substrate fingers arranged on the periphery of the memory chip, thereby effectively reducing the overall packaging area of the SD NAND. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 This is a schematic diagram of a simplified structure of a SD NAND based on a substrate-type packaging structure provided in an embodiment of the present application.
[0027] Figure 2 A top view of a detailed structural diagram of an SD NAND based on a substrate-type packaging structure provided in an embodiment of the present application.
[0028] Explanation of reference numerals: 1. substrate; 11. first substrate finger; 12. second substrate finger; 13. third substrate finger; 14. fourth substrate finger; 2. controller chip; 21. horizontal row of pads; 22. first column of pads; 23. second column of pads; 3. memory chip; 31. third column of pads; 4. dummy chip. DETAILED DESCRIPTION
[0029] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0030] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.
[0031] like Figure 1 and Figure 2 As shown, Figure 2 This is a top view of a detailed structural diagram of an SD NAND based on a substrate-type packaging structure provided in an embodiment of the present application, in order to illustrate the connection relationship between the controller chip 2, the memory chip 3 and the dummy chip 4, Figure 2 The memory chip 3 is perspective, and the present application provides an SD NAND based on a substrate packaging structure, which includes:
[0032] A substrate 1, having a plurality of rows of substrate fingers on its surface, wherein one row of substrate fingers is arranged at an edge of the substrate 1;
[0033] The controller chip 2 is arranged on the substrate 1, and its pads are electrically connected to other substrate fingers on the substrate 1 through bonding wires;
[0034] A dummy chip 4, which is fixed on the substrate 1 and located on one side of the controller chip 2;
[0035] The memory chip 3 is fixed on the dummy chip 4 and is located above the controller chip 2 , and its pads are electrically connected to the substrate fingers located at the edge of the substrate 1 through bonding wires.
[0036] Among them, the substrate 1 of this embodiment is an existing device, and internal wiring is arranged inside the substrate 1. Multiple rows of substrate fingers are arranged on the surface of the substrate 1. The substrate fingers are the wiring positions of the substrate 1. The substrate fingers are used to connect the chip pads with the internal wiring of the substrate 1, and one row of substrate fingers is arranged at the edge of the substrate 1. The controller chip 2 of this embodiment is arranged on the substrate 1, and the pads of the controller chip 2 are electrically connected to other substrate fingers on the substrate 1 (substrate fingers other than the substrate fingers located at the edge of the substrate 1) through welding wires. The memory chip 3 of this embodiment is fixed on the dummy chip 4 and is located above the controller chip 2, that is, the memory chip 3 of this embodiment is not in contact with the controller chip 2, and the pads of the memory chip 3 are electrically connected to the substrate fingers located at the edge of the substrate 1 through welding wires. It should be understood that since the coverage area of the memory chip 3 is much larger than the coverage area of the controller chip 2, and the memory chip 3 of this embodiment is arranged above the controller chip 2, the memory chip 3 of this embodiment can cover other substrate fingers electrically connected to the pads of the controller chip 2. Since the memory chip 3 of this embodiment is arranged above the controller chip 2, and the memory chip 3 is not in contact with the controller chip 2, this embodiment needs to set a dummy sheet 4 between the memory chip 3 and the substrate 1 to support the memory chip 3. The dummy sheet 4 of this embodiment can be a gasket without circuit such as a metal sheet or an alloy sheet. The dummy sheet 4 of this embodiment is fixed on the substrate 1.
[0037] The working principle of this embodiment is as follows: an SD NAND based on a substrate packaging structure provided in the present application includes a controller chip 2 arranged on a substrate 1 and a memory chip 3 arranged on the controller chip 2. Since the coverage area of the memory chip 3 is much larger than the coverage area of the controller chip 2, and the memory chip 3 is arranged above the controller chip 2, the substrate fingers originally located outside the memory chip 3 for connecting to the controller chip 2 can be arranged below the memory chip 3, that is, the memory chip 3 of the SD NAND can cover other substrate fingers electrically connected to the pads of the controller chip 2, that is, the SD NAND only needs to arrange a row of substrate fingers electrically connected to the pads of the memory chip 3 on the periphery of the memory chip 3, so the SD NAND can effectively reduce the number of substrate fingers arranged on the periphery of the memory chip 3, thereby effectively reducing the overall packaging area of the SD NAND.
[0038] In some embodiments, the controller chip 2 includes a horizontal pad 21, a first row of pads 22, and a second row of pads 23. The surface of the substrate 1 has a first substrate finger 11, a second substrate finger 12, and a third substrate finger 13. The horizontal pad 21 is electrically connected to the first substrate finger 11 through a welding wire, the first row of pads 22 is electrically connected to the second substrate finger 12 through a welding wire, and the second row of pads 23 is electrically connected to the third substrate finger 13 through a welding wire. The horizontal pad 21, the first row of pads 22, the second row of pads 23, the first substrate finger 11, the second substrate finger 12, and the third substrate finger 13 of this embodiment are all located below the memory chip 3, that is, the memory chip 3 covers the horizontal pad 21, the first row of pads 22, the second row of pads 23, the first substrate finger 11, the second substrate finger 12, and the third substrate finger 13. It should be understood that since the memory chip 3 of this embodiment covers the first substrate finger 11, the second substrate finger 12 and the third substrate finger 13, and the substrate 1 is also provided with a row of substrate fingers located at the periphery of the memory chip 3, the surface of the substrate 1 of this embodiment has four rows of substrate fingers.
[0039] In some embodiments, the first substrate finger 11 is located on one side of the horizontal pad 21, the second substrate finger 12 is located on one side of the first column pad 22, and the third substrate finger 13 is located on one side of the second column pad 23. In this embodiment, the first substrate finger 11 is arranged on one side of the horizontal pad 21, the second substrate finger 12 is arranged on one side of the first column pad 22, and the third substrate finger 13 is arranged on one side of the second column pad 23, that is, this embodiment is equivalent to reducing the distance between the first substrate finger 11 and the horizontal pad 21, the distance between the second substrate finger 12 and the first column pad 22, and the distance between the third substrate finger 13 and the second column pad 23, so this embodiment can effectively reduce the length of the bonding wire required when electrically connecting the pad of the controller chip 2 to the substrate finger.
[0040] In some embodiments, the dummy chip 4 is in a rectangular parallelepiped structure, and the dummy chip 4 is bounded by the first substrate finger 11 and the edge of the memory chip 3. In this embodiment, the dummy chip 4 is set as a rectangular parallelepiped structure, and the dummy chip 4 is bounded by the first substrate finger 11 and the edge of the memory chip 3, so this embodiment can effectively increase the overlap rate between the dummy chip 4 and the memory chip 3. Since the higher the overlap rate between the dummy chip 4 and the memory chip 3, the larger the support area of the dummy chip 4, this embodiment can also effectively improve the support effect of the dummy chip 4 and the overall stability of the SD NAND.
[0041] In some embodiments, the memory chip 3 includes a third row of pads 31, and the surface of the substrate 1 further includes a fourth substrate finger 14, which is disposed at the edge of the substrate 1, and the third row of pads 31 is electrically connected to the fourth substrate finger 14 through a bonding wire. The fourth substrate finger 14 of this embodiment is disposed at the edge of the substrate 1 and is located at the periphery of the memory chip 3.
[0042] In some embodiments, the fourth substrate finger 14 is located at the edge of the substrate 1 close to the third row of pads 31. This embodiment arranges the fourth substrate finger 14 at the edge of the substrate 1 close to the third row of pads 31, that is, this embodiment is equivalent to reducing the distance between the fourth substrate finger 14 and the third row of pads 31, so this embodiment can effectively reduce the length of the bonding wire required to electrically connect the pads of the memory chip 3 to the substrate finger.
[0043] In some embodiments, the minimum distance between the controller chip 2 and the edge of the substrate 1 is 0.15-0.25 mm. The minimum distance between the controller chip 2 and the edge of the substrate 1 in this embodiment is preferably 0.2 mm.
[0044] In some embodiments, the minimum distance between the memory chip 3 and the edge of the substrate 1 is 0.05-0.15 mm. The minimum distance between the memory chip 3 and the edge of the substrate 1 in this embodiment is preferably 0.1 mm.
[0045] In some embodiments, the dummy sheet 4 comprises an aluminum sheet.
[0046] In some embodiments, the thickness of the dummy sheet 4 is greater than the sum of the thickness of the controller chip 2 and the bonding height of the controller chip 2. Since the thickness of the dummy sheet 4 of this embodiment is greater than the sum of the thickness of the controller chip 2 and the bonding height of the controller chip 2, and the height of the dummy sheet 4 is equal to the distance between the memory chip 3 and the substrate 1, this embodiment can effectively avoid the situation where the bonding of the controller chip 2 is affected due to the small distance between the memory chip 3 and the substrate 1.
[0047] As can be seen from the above, the utility model provides an SD NAND based on a substrate-type packaging structure, including a controller chip 2 arranged on a substrate 1 and a memory chip 3 arranged on the controller chip 2. Since the coverage area of the memory chip 3 is much larger than the coverage area of the controller chip 2, and the memory chip 3 is arranged above the controller chip 2, the substrate fingers originally located outside the memory chip 3 for connecting to the controller chip 2 can be arranged below the memory chip 3, that is, the memory chip 3 of the SD NAND can cover other substrate fingers electrically connected to the pads of the controller chip 2, that is, the SD NAND only needs to arrange a row of substrate fingers for electrically connecting to the pads of the memory chip 3 on the periphery of the memory chip 3, so the SD NAND can effectively reduce the number of substrate fingers arranged on the periphery of the memory chip 3, thereby effectively reducing the overall packaging area of the SD NAND.
[0048] In the description of this specification, the description with reference to the terms "one embodiment", "certain embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the utility model. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0049] The above are only some embodiments of the present invention. For those skilled in the art, several modifications and improvements can be made without departing from the inventive concept of the present invention, which all belong to the protection scope of the present invention.
Claims
1. An SD NAND based on a substrate packaging structure, characterized in that: The SDN ADN based on the substrate packaging structure includes: A substrate having a plurality of rows of substrate fingers on its surface, wherein one row of the substrate fingers is arranged at an edge of the substrate; A controller chip is arranged on the substrate, and a pad of the controller chip is electrically connected to other substrate fingers on the substrate through a bonding wire; A dummy chip, fixed on the substrate and located on one side of the controller chip; A memory chip is fixed on the dummy chip and is located above the controller chip, and a pad of the memory chip is electrically connected to a substrate finger located at the edge of the substrate through the bonding wire.
2. The SD NAND based on substrate packaging structure according to claim 1, characterized in that: The controller chip includes a horizontal row of pads, a first column of pads, and a second column of pads. The surface of the substrate has a first substrate finger, a second substrate finger, and a third substrate finger. The horizontal row of pads is electrically connected to the first substrate finger through the welding wire, the first column of pads is electrically connected to the second substrate finger through the welding wire, and the second column of pads is electrically connected to the third substrate finger through the welding wire.
3. The SD NAND based on substrate packaging structure according to claim 2, characterized in that: The first substrate finger is located at one side of the horizontal row of pads, the second substrate finger is located at one side of the first column of pads, and the third substrate finger is located at one side of the second column of pads.
4. The SD NAND based on substrate packaging structure according to claim 2, characterized in that: The dummy film is in a rectangular parallelepiped structure, and the dummy film is bounded by the first substrate finger and the edge of the memory chip.
5. The SD NAND based on substrate packaging structure according to claim 1, characterized in that: The memory chip includes a third row of pads, the surface of the substrate further includes a fourth substrate finger, the fourth substrate finger is arranged at the edge of the substrate, and the third row of pads is electrically connected to the fourth substrate finger through a welding wire.
6. The SD NAND based on substrate packaging structure according to claim 5, characterized in that: The fourth substrate finger is located at an edge of the substrate close to the third row of pads.
7. The SD NAND based on substrate packaging structure according to claim 1, characterized in that: The minimum distance between the controller chip and the edge of the substrate is 0.15-0.25 mm.
8. The SD NAND based on substrate packaging structure according to claim 1, characterized in that: The minimum distance between the memory chip and the edge of the substrate is 0.05-0.15 mm.
9. The SD NAND based on substrate packaging structure according to claim 1, characterized in that: The dummy sheet comprises an aluminum sheet.
10. The SD NAND based on substrate packaging structure according to claim 1, characterized in that: The thickness of the dummy chip is greater than the sum of the thickness of the controller chip and the bonding height of the controller chip.