Display panel, display module and display device

Abstract

The utility model provides a display panel, a display module and a display device. The display panel comprises a display area and a peripheral area, the peripheral area is provided with a plurality of binding areas used for binding a chip on film, and at least one binding area is provided with at least two binding test parts. The at least one binding test part comprises a first test pin and a second test pin which are arranged at an interval, and the first test pin is electrically connected with the second test pin. The display panel is provided with at least one crack test circuit located in the peripheral area. Each crack test circuit is provided with a first connecting end and a second connecting end, one of the first connecting end and the second connecting end is used as an input end, and the other one is used as an output end. The first connecting end and the second connecting end of the same crack test circuit are electrically connected with different binding test parts of the same binding area respectively.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology and relates to a display panel, a display module and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) has been widely promoted and applied in the display industry in recent years due to its advantages such as fast response time, high color gamut, and bendability. With the rapid development of the OLED display industry, medium and large-sized OLED display products have gradually entered the market, such as car displays, laptop displays, and TV displays.

[0003] As people's requirements for the functions and resolution of display products become higher and higher, the number of binding pins required for display panels is increasing. In addition, in the production process of display modules, various functional tests are performed to ensure the normal operation of each process stage, thereby introducing more additional binding pins. When the width of the Chip On Flex (COF) remains unchanged, the more binding pins there are and the smaller the spacing, the more difficult the binding process becomes. Utility Model Content

[0004] The display panel, display module and display device provided by the embodiments of the present disclosure can effectively reduce the number of binding pins of the display panel and increase the spacing between the binding pins, thereby helping to reduce the difficulty of the binding process.

[0005] In a first aspect of the present disclosure, a display panel is provided, comprising: a display area and a peripheral area, wherein the peripheral area is provided with a plurality of binding areas for binding a cover chip film, at least one of the binding areas is provided with at least two binding test parts, at least one of the binding test parts comprises a first test pin and a second test pin arranged at intervals, and the first test pin and the second test pin are electrically connected. The display panel is provided with at least one crack test circuit, wherein the crack test circuit is located in the peripheral area, each of the crack test circuits has a first connection end and a second connection end, wherein one of the first connection end and the second connection end serves as an input end, and the other serves as an output end, and the first connection end and the second connection end of the same crack test circuit are respectively electrically connected to different binding test parts of the same binding area.

[0006] In combination with the first aspect, in some embodiments, the crack test circuit includes: a first test trace and a second test trace arranged at intervals, the second test trace is located between the first test trace and the display area, the first end of the first test trace is the first connection end, the second end of the first test trace is electrically connected to the first end of the second test trace, the second end of the second test trace is the second connection end, and the first connection end and the second connection end are located on the same side of the display panel.

[0007] In combination with the first aspect, in some embodiments, the at least one crack test circuit includes a first crack test circuit and a second crack test circuit that are independently arranged, the multiple binding areas are arranged in sequence along a first direction of the display panel, the display panel has a first side and a second side that are opposite in the first direction, the first connection end and the second connection end of the first crack test circuit are located on the first side of the display panel, and the first connection end and the second connection end of the second crack test circuit are located on the second side of the display panel. The multiple binding areas include: a first binding area and a second binding area, the first connection end and the second connection end of the first crack test circuit are each electrically connected to a different binding test portion of the first binding area, and the first connection end and the second connection end of the second crack test circuit are each electrically connected to a different binding test portion of the second binding area.

[0008] In combination with the first aspect, in some embodiments, the first binding area is the binding area closest to the first side of the display panel among the multiple binding areas, and the second binding area is the binding area closest to the second side of the display panel among the multiple binding areas.

[0009] In combination with the first aspect, in some embodiments, the peripheral area includes: a first border area, a second border area, a third border area and a fourth border area, the first border area is arranged opposite to the third border area, the second border area is arranged opposite to the fourth border area, and the multiple binding areas are distributed in the first border area. The third border area is provided with a first jumper wire and a second jumper wire, the first test trace and the second test trace in the first crack test circuit are distributed in the second border area and the third border area, and are electrically connected in the third border area through the first jumper wire, the first test trace and the second test trace in the second crack test circuit are distributed in the third border area and the fourth border area, and are electrically connected in the third border area through the second jumper wire.

[0010] In combination with the first aspect, in some embodiments, the at least two binding test sections include a first binding test section and a second binding test section, the binding area includes a first edge region, a second edge region, and an intermediate region between the first edge region and the second edge region, the first binding test section is located in the first edge region, and the second binding test section is located in the second edge region. The first connection end is electrically connected to the first binding test section via a first connection line, the second connection end is electrically connected to the second binding test section via a second connection line, the distance between the second binding test section and the second connection end is greater than the distance between the first binding test section and the first connection end, and the routing length of the second connection line is greater than the routing length of the first connection line.

[0011] In combination with the first aspect, in some embodiments, the middle area is provided with a plurality of signal pins arranged in sequence along a first direction of the display panel, and the peripheral area is further provided with a plurality of signal leads extending in a second direction, each signal lead is electrically connected to one of the signal pins, and the second direction intersects with the first direction. The display panel includes: a base substrate and a plurality of conductive layers stacked in sequence on the base substrate, the second connecting line includes a connecting line segment extending in the first direction, the orthographic projection of the connecting line segment on the base substrate intersects with the orthographic projection of the plurality of signal leads on the base substrate, and the connecting line segment and the plurality of signal leads are located in two different conductive layers among the plurality of conductive layers.

[0012] In combination with the first aspect, in some embodiments, the multiple conductive layers include: a first gate metal layer, a second gate metal layer, and a source-drain metal layer, and the multiple signal leads and the connecting line segments are located in two different metal layers among the first gate metal layer, the second gate metal layer, and the source-drain metal layer.

[0013] In a second aspect of the present disclosure, a display module is provided, comprising: the display panel as described in the first aspect and a plurality of chip-on-films, each of the chip-on-films being bound to a binding area in the display panel.

[0014] In combination with the second aspect, in some embodiments, each of the flip chip films is provided with a first binding pad area, a second binding pad area, a first test signal line, and a second test signal line. The first binding pad area is bound to a binding area of ​​the display panel, and the first binding pad area is provided with a first auxiliary test section corresponding to each binding test section of the binding area, and the first auxiliary test section includes: a first test pad and a second test pad, the first test pad is bound and connected to the first test pin of the corresponding binding test section, and the second test pad is bound and connected to the second test pin of the corresponding binding test section. The second binding pad area is used to bind the circuit board, and the second binding pad area is provided with a second auxiliary test section corresponding to each of the first auxiliary test sections, and each of the second auxiliary test sections includes: a third test pad and a fourth test pad, the first test signal line electrically connects the first test pad and the third test pad, and the second test signal line electrically connects the second test pad and the fourth test pad.

[0015] In combination with the second aspect, in some embodiments, at least one of the multiple flip-chip films is also provided with a third signal transmission line and a fourth signal transmission line, and the second binding pad area of ​​the at least one flip-chip film is also provided with: a fifth test pad and a sixth test pad, the third signal transmission line electrically connects the fifth test pad with the source driver chip set on the flip-chip film, and the fourth signal transmission line electrically connects the sixth test pad with the source driver chip.

[0016] In combination with the second aspect, in some embodiments, the display module further includes a circuit board, and the circuit board is provided with: a first test terminal, a second test terminal, and a third auxiliary test section corresponding to each second auxiliary test section. Each of the third auxiliary test sections includes: a third test terminal and a fourth test terminal, the first test terminal is bound and connected to the fifth test pad, the second test terminal is bound and connected to the sixth test pad, the third test terminal is bound and connected to the third test pad, the fourth test terminal is bound and connected to the fourth test pad, and the first test terminal and the second test terminal are respectively electrically connected to the third test terminal or the fourth test terminal of different third auxiliary test sections.

[0017] In a third aspect of the present disclosure, a display device is provided, comprising: the display module described in the second aspect above.

[0018] In the display panel, display module and display device provided in some embodiments of the present disclosure, at least one binding area of ​​the display panel is provided with at least two binding test parts for testing the binding impedance to detect whether the binding is qualified. By electrically connecting the first connection end and the second connection end of the same crack test line to different binding test parts of the same binding area, the two binding test parts of the same binding area can be reused to perform impedance testing and crack testing, which can reduce the number of binding pins of the display panel without affecting the functional test, thereby facilitating increasing the spacing between the binding pins and reducing the difficulty of the binding process.

[0019] The above description is only an overview of the technical solutions provided by some embodiments of the present disclosure. In order to more clearly understand the technical means of the embodiments of the present disclosure, they can be implemented in accordance with the contents of the specification. In order to make the embodiments of the present disclosure more obvious and easy to understand, the specific implementation methods of the embodiments of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 A schematic plan view of a display panel according to some embodiments of the present disclosure is shown;

[0022] Figure 2 Shows Figure 1 An enlarged schematic diagram of the left half of the area;

[0023] Figure 3 Shows Figure 1 The circuit layout near the first binding area in;

[0024] Figure 4 A film layer structure diagram of a display panel according to some embodiments of the present disclosure is shown;

[0025] Figure 5A An exploded structural diagram of a display module according to some embodiments of the present disclosure is shown;

[0026] Figure 5B Shows Figure 5A An enlarged schematic diagram of the dotted box Q in the middle;

[0027] Figure 6 A schematic diagram showing the binding of display modules in some embodiments of the present disclosure is shown;

[0028] Figure 7 Shows Figure 5AThe structure diagram of the display module after binding is shown;

[0029] Figure 8 A schematic structural diagram of a display device according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0030] The OLED module manufacturing process includes a variety of process sections, and the normality of these process sections determines the quality of the product. Therefore, in the production process of OLED modules, in order to ensure the normal operation of each process section, various tests will be introduced, such as binding impedance testing and crack testing, etc., which will introduce more signals that need to be transmitted, that is, more binding pins. Based on this, some embodiments of the present disclosure can reuse two binding test sections of the same binding area for impedance testing and crack testing by electrically connecting the first connection end and the second connection end of the crack test line to different binding test sections of the same binding area, which can reduce the number of binding pins of the display panel without affecting the functional test, thereby facilitating increasing the spacing between the binding pins and reducing the difficulty of the binding process.

[0031] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0032] It should be noted that the term "at least one" in this document includes one or more than one, and "more than one" and "at least two" include two or more than two. "Include" or "comprising" and similar words mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, but do not exclude other elements or objects. It should be understood that unless otherwise clearly specified and limited, the term "electrically connected" in this document should be understood in a broad sense, for example, it can be directly connected or indirectly connected through an intermediate medium.

[0033] Figure 1 FIG. 2 shows a schematic plan view of a display panel of some embodiments of the present disclosure. Figure 1As shown, the display panel 100 includes a display area AA and a peripheral area ND. The display area AA is provided with a plurality of pixel units distributed in an array, and each pixel unit includes one or more sub-pixels to achieve color display. For example, each pixel unit may include three sub-pixels, such as a red sub-pixel, a green sub-pixel, and a blue sub-pixel. For another example, each pixel unit may also include four sub-pixels, such as a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. Each sub-pixel includes a light-emitting device and a pixel circuit that drives the light-emitting device to emit light. The light-emitting device may be, for example, an organic electroluminescent device such as an OLED or a quantum dot light emitting diode (Quantum dotLight Emitting Diodes, QLED).

[0034] The pixel circuit may include multiple electronic components such as transistors and capacitors. For example, the pixel circuit may include three transistors and one capacitor, forming a 3T1C (i.e., a driving transistor, two switching transistors and a capacitor). For another example, the pixel circuit may also include more than three transistors and at least one capacitor, such as a 4T1C (i.e., a driving transistor, three switching transistors and a capacitor), a 5T1C (i.e., a driving transistor, four switching transistors and a capacitor) or a 7T1C (i.e., a driving transistor, six switching transistors and a capacitor), etc. Among them, the transistor may be a thin film transistor (Thin Film Transistor, referred to as TFT), a field effect transistor (metal oxide semiconductor, referred to as MOS) or other switching devices with the same characteristics.

[0035] It can be understood that the transistor may include a control electrode, a first electrode, and a second electrode. The control electrode is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor may be symmetrical in structure, the source and drain may be structurally indistinguishable, so the source of the transistor may be referred to as the first electrode or the second electrode.

[0036] The peripheral area ND of the display panel 100 is provided with a plurality of binding areas for binding the COF, and at least one binding area is provided with at least two binding test parts. At least one binding test part includes a first test pin 121 and a second test pin 122 arranged at intervals, and the first test pin 121 and the second test pin 122 are electrically connected to perform a binding impedance test, so as to detect whether the binding between the display panel and the COF is qualified.

[0037] It should be noted that Figure 1The number of binding areas shown, the number of binding areas provided with at least two binding test parts, and the number of binding test parts provided in the same binding area are for illustration only and are not intended to be limiting. They can be determined according to the needs of the actual product. In some embodiments, at least two binding test parts can be provided in each binding area to ensure the reliability of the binding test results and facilitate processing. In some embodiments, the at least two binding test parts can be two, respectively provided at the two ends of the binding area, so as to save binding pins while ensuring the reliability of the binding test results. Of course, if the number of binding pins allows, each binding area can also be provided with three or more binding test parts, respectively provided at the two ends and the middle of the binding area, and the present disclosure does not impose any restrictions on this.

[0038] Of course, in other embodiments, at least two binding test sections may be provided in a specific binding area (such as one or two, etc.) among the multiple binding areas to detect whether the binding between the display panel and the chip-on-film is qualified by performing impedance detection on the specific binding area.

[0039] In some embodiments, each binding test section includes a first test pin 121 and a second test pin 122 that are spaced apart, and the first test pin 121 and the second test pin 122 are electrically connected, so that each binding test section can be used for impedance detection and crack testing.

[0040] The display panel 100 is provided with at least one crack test circuit, which is located in the peripheral area ND of the display panel 100. The above-mentioned at least one crack test circuit has a first connection terminal v1 and a second connection terminal v2. One of the first connection terminal v1 and the second connection terminal v2 serves as an input terminal to receive an excitation signal, and the other serves as an output terminal to output a crack test signal. The first connection terminal v1 and the second connection terminal v2 of the same crack test circuit are respectively electrically connected to different binding test parts of the same binding area. It should be noted that the electrical connection with the binding test part can be achieved in the following three ways: (1) electrically connected to the first test pin 121 included in the binding test part; (2) electrically connected to the second test pin 122 included in the binding test part; (3) electrically connected to the connection block that realizes the conduction between the first test pin 121 and the second test pin 122.

[0041] For example, Figure 1 FIG. 1 shows two binding areas and two crack test circuits. The two binding areas are the first binding area B1 and the second binding area B2. Each binding area is provided with two binding test parts, namely the first binding test part 120a and the second binding test part 120b. The two crack test circuits are the first crack test circuit PCD1 and the second crack test circuit PCD2. Figure 1Taking the first crack test circuit PCD1 in the display device as an example, its first connection terminal v1 is an output terminal, and the second connection terminal v2 is an input terminal. The output terminal is electrically connected to the first binding test section 120a in the first binding area B1, and the input terminal is electrically connected to the second binding test section 120b in the first binding area B1, so that the first binding test section 120a and the second binding test section 120b are multiplexed to realize signal transmission with the outside. The excitation signal can be transmitted to the second connection terminal v2 via the first test pin 121 or the second test pin 122 of the second binding test section 120b, transmitted in the first crack test circuit PCD1, and then output from the first connection terminal v1 a crack test signal carrying the crack test information of the display panel 100, and output to the outside through the first test pin 121 or the second test pin 122 included in the first binding test section 120a.

[0042] Compared with separately setting test pins on the display panel 100 to transmit signals involved in crack testing, each binding area can reduce at least two pins, which is beneficial to increase the pin spacing in the binding area and reduce the difficulty of the binding process.

[0043] In some embodiments, the crack test circuit may include: a first test line l1 and a second test line l2 arranged at intervals. The second test line l2 is located between the first test line l1 and the display area AA, the first end of the first test line l1 serves as the first connection end v1, the second end of the first test line l1 is electrically connected to the first end of the second test line l2, and the second end of the second test line l2 serves as the second connection end v2.

[0044] The first connection end v1 and the second connection end v2 of the same crack test circuit are located on the same side of the display panel 100. Figure 1 The left side or right side of the display panel 100 shown in FIG. In some embodiments, the display panel 100 includes a long side and a short side, and a plurality of binding areas are distributed on one of the long sides (also referred to as a "binding side"). The end of one of the short sides close to the binding side can be used as the starting end, and the wiring can be routed around the display area AA in the peripheral area ND, passing through the area where crack detection is required, and then returning to the starting end to form the above-mentioned crack test circuit, and the first connection end v1 and the second connection end v2 of the crack test circuit are located on the same side of the display panel 100. This is conducive to reducing the wiring difficulty of connecting the first connection end v1 and the second connection end v2 to the two binding test parts of the same binding area respectively.

[0045] In some embodiments, the plurality of binding areas may be arranged along a first direction (eg, Figure 1The first direction may be the pixel row direction of the display panel 100. The display panel 100 has a first side and a second side opposite to each other in the first direction. If the first connection end v1 and the second connection end v2 of the crack test circuit are located on the first side (such as Figure 1 If the first connection end v1 and the second connection end v2 of the crack test circuit are located on the second side (such as the left side of the display panel 100), the first connection end v1 and the second connection end v2 are respectively electrically connected to the two binding test parts in the binding area close to the first side edge to reduce the wiring distance. Figure 1 The first connection terminal v1 and the second connection terminal v2 are respectively electrically connected to two binding test parts in the binding area close to the second side edge to reduce the wiring distance.

[0046] In some embodiments, the at least one crack test circuit mentioned above may be two, namely, a first crack test circuit PCD1 and a second crack test circuit PCD2. The first crack test circuit PCD1 and the second crack test circuit PCD2 are independently arranged. The first connection end v1 and the second connection end v2 of the first crack test circuit PCD1 are located on the first side of the display panel 100, and the first connection end v1 and the second connection end v2 of the second crack test circuit PCD2 are located on the second side of the display panel 100. The above-mentioned multiple binding areas include: a first binding area B1 and a second binding area B2, the first connection end v1 and the second connection end v2 of the first crack test circuit PCD1 are respectively electrically connected to different binding test parts of the first binding area B1, and the first connection end v1 and the second connection end v2 of the second crack test circuit PCD2 are respectively electrically connected to different binding test parts of the second binding area B2.

[0047] In some embodiments, the first binding area B1 is the binding area closest to the first side of the display panel 100 among the above-mentioned multiple binding areas, and the second binding area B2 is the binding area closest to the second side of the display panel 100 among the multiple binding areas, so as to minimize the wiring length in the first direction and reduce the wiring difficulty.

[0048] For example, the peripheral area ND of the display panel 100 may be divided into a first area and a second area arranged along a first direction (eg, Figure 1 The left half area and the right half area in the figure), the first crack test circuit PCD1 is used to perform crack test on the first area, and the second crack test circuit PCD2 is used to perform crack test on the second area. In this way, crack test can be performed in different areas, which is conducive to more accurate positioning of the crack occurrence position.

[0049] like Figure 1As shown, in some embodiments, the peripheral area ND of the display panel 100 may include: a first frame area ND1, a second frame area ND2, a third frame area ND3, and a fourth frame area ND4 that are adjacent to each other in sequence. The first frame area ND1 is arranged opposite to the third frame area ND3, the second frame area ND2 is arranged opposite to the fourth frame area ND4, and the above-mentioned multiple binding areas are distributed in the first frame area ND1. In other words, the first frame area ND1 is located on the binding side of the display panel 100, and the third frame area ND3 is located on the opposite side of the binding side, which can also be called the "non-binding side".

[0050] The third border area ND3 is provided with a first jumper wire and a second jumper wire. The first test trace l1 and the second test trace l2 of the first crack test circuit PCD1 are distributed in the second border area ND2 and the third border area ND3, and are electrically connected in the third border area ND3 through the first jumper wire. The first test trace l1 and the second test trace l1 of the second crack test circuit PCD2 are distributed in the third border area ND3 and the fourth border area ND4, and are electrically connected in the third border area ND3 through the second jumper wire. In this way, the first crack test circuit PCD1 can be used to test whether a part of the third border area ND3 and the second border area ND2 have cracks, and the second crack test circuit PCD2 can be used to test whether the fourth border area ND4 and another part of the third border area ND3 have cracks.

[0051] To make it clearer, Figure 2 Shows Figure 1 An enlarged schematic diagram of the left half of the area. Figure 2 As shown, taking the first crack test circuit PCD1 as an example, the first test trace l1 may include: a first trace segment l11 located in the second frame area ND2 and a second trace segment l12 located in the third frame area ND3, the first trace segment l11 and the second trace segment l12 are electrically connected at the corner between the second frame area ND2 and the third frame area ND3; the second test trace l2 may include: a third trace segment l21 located in the second frame area ND2 and a fourth trace segment l22 located in the third frame area ND3, the third trace segment l21 and the fourth trace segment l22 are also electrically connected at the corner between the second frame area ND2 and the third frame area ND3. Among them, the second trace segment l12 and the fourth trace segment l22 are electrically connected through the first jumper wire l3. For example: the second trace segment l12 and the fourth trace segment l22 can be located in different conductive layers from the first jumper wire l3, and then electrically connected through vias. The first trace segment l11 and the third trace segment l21 are connected along the second direction (such as Figure 2 The second direction intersects the first direction, and can be, for example, the pixel column direction of the display panel 100. The second routing segment 112 and the fourth routing segment 122 extend along the first direction (eg, the Y-axis direction of the display panel 100). Figure 2 It should be noted that the implementation of the second crack test circuit PCD2 is basically similar to that of the first crack test circuit PCD1, and will not be repeated here.

[0052] In some embodiments, the at least two binding test sections may be two binding test sections, namely a first binding test section and a second binding test section. The binding area includes a first edge region, a second edge region, and an intermediate region between the first edge region and the second edge region, the first binding test section is located in the first edge region, and the second binding test section is located in the second edge region. For example, Figure 2 As shown, the first binding area of ​​the display panel 100 has a plurality of binding pins. Figure 2 They are arranged in sequence along the middle X-axis direction. From left to right, the first and second binding pins are respectively the first test pin 121 and the second test pin 122 of the first binding test part 120a, and the second to last and the last binding pins are respectively the first test pin 121 and the second test pin 122 of the second binding test part 120b.

[0053] In order to realize the corresponding connection between the first connection end v1 and the second connection end v2 of the crack test circuit and the first binding test part 120a and the second binding test part 120b of the same binding area, the peripheral area ND of the display panel 100 is further provided with a first connection line h1 and a second connection line h2. The first connection line h1 and the second connection line h2 are located on the binding side of the display panel 100, that is, located in the above-mentioned first frame area ND1. The first connection end v1 is electrically connected to the first binding test part 120a through the first connection line h1, and the second connection end v2 is electrically connected to the second binding test part 120b through the second connection line h2.

[0054] In some embodiments, since the first connection end v1 and the second connection end v2 of the crack test circuit are located on the same side of the display panel 100, that is, on the same side of the binding area of ​​the test pin to be reused, and the first binding test section 120a and the second binding test section 120b of the same binding area are separated by an intermediate area, that is, there is a certain spacing distance, so when the first binding test section is closer to the first connection end v1 and the second connection end v2 than the second binding test section, the distance between the second binding test section and the second connection end v2 is greater than the distance between the first binding test section and the first connection end v1. Then, the second connection line h2 needs to be routed along the first direction and bypass the intermediate area to be electrically connected to the second binding test section. At this time, the routing length of the second connection line h2 is greater than the routing length of the first connection line h1; for example: the routing length of the second connection line h2 in the first frame area ND1 is greater than the routing length of the first connection line h1 in the first frame area ND1.

[0055] Figure 3 Shows Figure 1 The circuit layout near the first bonding area in Figure 3 As shown, the middle area MB of the first binding area is provided with a plurality of signal pins 131 arranged in sequence along the first direction of the display panel 100. The plurality of signal pins 131 are used to transmit the signals required by the display panel 100, for example, they can be used to transmit data signals, GOA signals, touch signals, etc., and are set according to the needs of the actual product. Therefore, in order to facilitate the connection between these signal pins 131 and the various signal lines in the panel, the peripheral area ND of the display panel 100 is also provided with a plurality of signal leads 132 extending along the second direction, each signal lead 132 is electrically connected to a signal pin 131, and the second direction intersects with the first direction. Since the above-mentioned second connecting line h2 needs to bypass the middle area, it is necessary to avoid these signal leads.

[0056] In some embodiments, the display panel 100 may include: a base substrate and a plurality of conductive layers stacked sequentially on the base substrate, with an insulating layer disposed between adjacent conductive layers. The second connecting line h2 includes a connecting line segment h21 extending along a first direction, and the orthographic projection of the connecting line segment h21 on the base substrate intersects with the orthographic projection of the plurality of signal leads 132 on the base substrate. Therefore, in order to achieve insulation between the connecting line segment h21 and the plurality of signal leads 132, the connecting line segment h21 and the plurality of signal leads 132 are located in two different conductive layers among the plurality of conductive layers.

[0057] Optionally, the orthographic projection of the first connection line h1 on the substrate substrate does not overlap with the orthographic projection of the plurality of signal leads 132 on the substrate substrate, and the first connection line h1 and the connection line segment h21 may be located in the same conductive layer, and the first connection line h1 and the connection line segment h21 may be located in a different conductive layer from the first crack test circuit PCD1. It should be noted that the connection line segment h21 is not charged in the non-crack test state, and the signal transmitted in the crack test state is a constant voltage without voltage mutation, so it will basically not affect the signal transmitted by the signal lead 132.

[0058] Figure 4 FIG. 2 shows a film layer structure diagram of a display panel of some embodiments of the present disclosure. Figure 2 As shown, the display panel 100 may include: a base substrate 101 , and a driving circuit layer, a planar layer 109 , a first electrode layer 110 , and a pixel defining layer 111 sequentially stacked on the base substrate 101 .

[0059] For example, the substrate 101 may be a rigid substrate, which may include, for example, a glass substrate, a PMMA (Polymethyl methacrylate) substrate, a silicon substrate, etc. In this case, the display panel 100 may be a rigid display panel.

[0060] For another example, the substrate 101 may be a flexible substrate. The flexible substrate may include, for example, a PI (Polyimide) substrate, a PET (Polyethylene terephthalate) substrate, or a PEN (Polyethylene naphthalate two formic acid glycol ester) substrate. In this case, the display panel 100 may be a flexible display panel.

[0061] It should be noted that the base substrate 101 may be a one-layer structure or a multi-layer structure. For example, the base substrate 101 may include at least one flexible substrate and at least one buffer layer, and the flexible substrate and the buffer layer are alternately stacked.

[0062] The pixel defining layer 111 has a plurality of pixel openings. Each pixel opening is configured to define a light emitting region of a light emitting device. The first electrode layer 110 includes: a first electrode for each light emitting device.

[0063] In a direction away from the base substrate 101, the light-emitting device may include a first electrode, a light-emitting functional layer (not shown in the figure), and a second electrode (not shown in the figure) stacked in sequence. One of the first electrode and the second electrode serves as the anode of the light-emitting device 120, and the other serves as the cathode. The light-emitting functional layer may at least include: a light-emitting layer (EML), which emits display light under the drive of the first electrode and the second electrode. In some embodiments, the light-emitting functional layer may also include any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL), which may be arranged according to actual needs, and the present disclosure does not limit this.

[0064] Each pixel opening exposes at least a portion of the first electrode of the corresponding light-emitting device, and at least a portion of the light-emitting function layer is located in the corresponding pixel opening and is electrically connected to the corresponding first electrode.

[0065] Of course, in addition to the above structure, the display panel 100 may also include other film layer structures, such as an encapsulation layer, a touch layer, and a color film layer, etc., which are configured according to actual product needs and are not limited in the present disclosure.

[0066] The driving circuit layer is at least configured to form a pixel circuit for each of the above-mentioned sub-pixels. Of course, in addition to the pixel circuit, the driving circuit layer can also be configured to form other functional circuits according to the needs of the actual application scenario. For example, in the display panel 100 with a fingerprint recognition function, the driving circuit layer can also be configured to form a photosensitive sensor, which is not limited in the present disclosure.

[0067] In some embodiments, the driving circuit layer may include at least: an active layer 102, a first gate insulating layer 103 (also referred to as GI1), a first gate metal layer 104 (also referred to as Gate1), a second gate insulating layer 105 (also referred to as GI2), a second gate metal layer 106 (also referred to as Gate2), an interlayer insulating layer 107 (InterlayerDielectric, ILD) and a source-drain metal layer 108 (also referred to as SD) stacked in sequence.

[0068] For example, the active layer 102 may include active patterns (also referred to as channel regions) of each transistor in the pixel circuit. The first gate metal layer 104 may include the gates of each transistor in the pixel circuit. In addition, the first gate metal layer 104 may also include: a first capacitor plate of a capacitor in the pixel circuit. For example, the gate pattern of the transistor may be used as the first capacitor plate at the same time, or a first capacitor plate may be additionally provided in the first gate metal layer 104. The specific structure is provided according to actual needs, and the present disclosure does not limit this. The second gate metal layer 106 includes a second capacitor plate of a capacitor in the pixel circuit. The first capacitor plate and the second capacitor plate are arranged relative to each other to form a capacitor in the pixel circuit. The source-drain metal layer 108 includes: a first electrode and a second electrode, i.e., a source electrode and a drain electrode, of each transistor in the pixel circuit.

[0069] In some embodiments, the above-mentioned multiple conductive layers may include at least: a first gate metal layer 104, a second gate metal layer 106, and a source-drain metal layer 108. The above-mentioned multiple signal leads 132 and the above-mentioned connecting line segment h21 may be located in two different metal layers among the first gate metal layer 104, the second gate metal layer 106, and the source-drain metal layer 108, so that the above-mentioned multiple signal leads 132 intersect with the above-mentioned connecting line segment h21 but are not conductive. In some embodiments, the first test pin 121, the second test pin 122, and each signal pin 131 of the binding area may be located in the source-drain metal layer 108, or, it may also be a multi-film layer structure formed by stacking multiple metal layers such as the first gate metal layer 104, the second gate metal layer 106, and the source-drain metal layer 108, etc., which is set according to the needs of the actual product, and the present disclosure does not limit this.

[0070] like Figure 3As shown, each signal pin 131 in the middle area MB of the first binding area B1 is connected to a signal lead 132 extending along the second direction. The second connection line h2 includes a connection line segment h21 extending along the first direction and a connection line segment h22 extending along the second direction. One end of the connection line segment h21 is electrically connected to the second connection end v2 of the first crack test circuit PCD1, and the other end is electrically connected to the connection line segment h22. The connection line segment h22 is electrically connected to the second binding test part 120b. In some embodiments, the first test line l1 and the second test line l2 of the first crack test circuit PCD1 can be located in the first gate metal layer 104, the signal lead 132 of each signal pin 131 and the connection line segment h22 can be located in the second gate metal layer 106, and the connection line segment h21 can be located in the source-drain metal layer 108. The connection line segment h21 can be connected to the second test line l2 and the connection line segment h22 via holes, respectively.

[0071] Of course, in other embodiments, the signal lead 132 may also be located at the source-drain metal layer 108, and the connecting line segment h21 is located at the second gate metal layer 106; or, the signal lead 132 is located at the second gate metal layer 106, and the connecting line segment h21 is located at the first gate metal layer 104; or, the signal lead 132 is located at the first gate metal layer 104, and the connecting line segment h21 is located at the source-drain metal layer 108; or, the signal lead 132 is located at the source-drain metal layer 108, and the connecting line segment h21 is located at the first gate metal layer 104; or, the signal lead 132 is located at the first gate metal layer 104, and the connecting line segment h21 is located at the second gate metal layer 106. It can be set according to the actual needs of the product to ensure that the signal lead 132 and the connecting line segment h21 intersect but are not conductive, and the present disclosure does not impose any restrictions on this.

[0072] Figure 5A shows an exploded structural diagram of a display module of some embodiments of the present disclosure, Figure 5B Shows Figure 5A Enlarged schematic diagram of the dotted box Q in the middle. Figure 6 A schematic diagram of binding display modules according to some embodiments of the present disclosure is shown. Figure 7 Shows Figure 5A The structure diagram of the display module after binding is shown.

[0073] refer to FIG. 5A to FIG. 7 The display module 10 provided by some embodiments of the present disclosure includes: a display panel 100 and a plurality of chip-on-films 200 , each of which is bound to a binding area in the display panel 100 .

[0074] like Figure 5A and 5BAs shown, each flip chip 200 is provided with a first binding pad area 211, a second binding pad area 212, a first test signal line 231 and a second test signal line 232. The first binding pad area 211 and the second binding pad area 212 are arranged opposite to each other, the first binding pad area 211 is bound to a binding area of ​​the display panel 100, and the second binding pad area 212 is used to bind the circuit board 300.

[0075] The first binding pad area 211 is provided with a first auxiliary test section 220 corresponding to each binding test section of the binding area. The first auxiliary test section 220 includes: a first test pad 221 and a second test pad 222. The first test pad 221 is bound and connected to the first test pin 121 of the corresponding binding test section, and the second test pad 222 is bound and connected to the second test pin 122 of the corresponding binding test section.

[0076] The second bonding pad area 212 is provided with a second auxiliary test section 240 corresponding to each first auxiliary test section 220. Each second auxiliary test section 240 includes: a third test pad 241 and a fourth test pad 242. Figure 4 As shown, the first test signal line 231 electrically connects the first test pad 221 and the third test pad 241 , and the second test signal line 232 electrically connects the second test pad 222 and the fourth test pad 242 .

[0077] In some embodiments, at least one of the plurality of chip-on-films 200 (eg, Figure 5A and Figure 5B The chip-on-film 200a in the embodiment of the present invention is provided with a third signal transmission line 233 and a fourth signal transmission line 234. The second binding pad area 212 of the chip-on-film 200a is also provided with a fifth test pad 251 and a sixth test pad 252. Figure 4 As shown, the third signal transmission line 233 electrically connects the fifth test pad 251 and the source driver chip 201a disposed on the flip chip 200a, and the fourth signal transmission line 234 electrically connects the sixth test pad 252 and the source driver chip 201a.

[0078] In some embodiments, the display module 10 may further include a circuit board 300, and the circuit board 300 is bonded to the second bonding pad area 212 of each COF 200. Figure 6 In some embodiments, the circuit board 300 may be a display driver board, also known as a TCON (Timing Controller) board, and the circuit board 300 may be provided with chips such as a timing controller, a power management chip, and a voltage converter. Of course, in other embodiments, the circuit board 300 may also be a transfer circuit board connected between the chip-on-film and the display driver board, which may be specifically provided according to the needs of the actual product, and the present disclosure does not limit this.

[0079] The circuit board 300 is provided with: a first test terminal 311, a second test terminal 312, and a third auxiliary test section 320 corresponding to each second auxiliary test section 240. Each third auxiliary test section 320 includes: a third test terminal 321 and a fourth test terminal 322. Figure 5B and Figure 7 As shown, the first test terminal 311 is bound and connected to the fifth test pad 251, the second test terminal 322 is bound and connected to the sixth test pad 252, the third test terminal 321 is bound and connected to the third test pad 241, and the fourth test terminal 322 is bound and connected to the fourth test pad 242. The first test terminal 311 and the second test terminal 312 are electrically connected to the third test terminal 321 or the fourth test terminal 322 of two different third auxiliary test parts 320, respectively.

[0080] For example, Figure 5A and Figure 7 As shown, a plurality of binding terminal areas are provided on the circuit board 300, and each binding terminal area is bound to a COF 200. The binding terminal area located at the edge includes: a plurality of binding terminals arranged in sequence along the first direction, some of which are signal terminals (not shown in the figure) for transmitting the signals required by the source driver chip 201 and the display panel 100, and the other part are test terminals for testing. Figure 5B As shown, two third auxiliary test sections 320 are respectively located at the two ends of the binding terminal area 301. In some embodiments, the first test terminal 311 is electrically connected to the fourth test terminal 322 of the third auxiliary test section 320 on the left side through the first signal wiring 331, so as to multiplex a group of second test pins 122 and second test pads 222, second test signal lines 232, and fourth test pads 242 and fourth test terminals 322 that are bound and connected to transmit crack test signals to the source driver chip 201a. The second test terminal 312 is electrically connected to the fourth test terminal 322 of the third auxiliary test section 320 on the right side through the second signal wiring 332, so as to multiplex another group of second test pins 122 and second test pads 222, second test signal lines 232, and fourth test pads 242 and fourth test terminals 322 that are bound and connected to transmit the excitation signal output from the source driver chip 201a.

[0081] In some embodiments, each second auxiliary test section 240 on the chip-on-film 200 further includes: a seventh test pad 243, which is electrically connected to the third test pad 241. Correspondingly, each third auxiliary test section 320 on the circuit board 300 further includes: a fifth test terminal 323, which is bound and connected to the seventh test pad 243, so as to detect the binding impedance between the chip-on-film 200 and the circuit board 300, thereby determining whether the binding between the chip-on-film 200 and the circuit board 300 is qualified.

[0082] In some embodiments, the circuit board 300 is also provided with test leads and test pads so as to perform a bonding impedance test on the circuit board 300. Figure 7 As shown, two groups of test pads are provided for each flip chip film 200 on the circuit board 300, and each group of test pads includes: pad A, pad B and pad C. For each group of test pads, pad A is electrically connected to the fifth test terminal through test lead a, pad B is electrically connected to the third test terminal through test lead b, and pad C is electrically connected to the fourth test terminal through test lead c. By inserting the probe of the impedance detection device into pad A and pad B, the binding impedance of the flip chip film and the circuit board can be detected, thereby detecting whether the binding of the flip chip film and the circuit board is qualified. By inserting the probe of the impedance detection device into pad B and pad C, the binding impedance of the display panel 100 and the flip chip film and the flip chip film and the circuit board can be detected, thereby detecting whether the binding of the display panel 100 and the flip chip film is qualified.

[0083] like Figure 5B As shown, the first test terminal 311 can be electrically connected to the test lead c located on the left side of the first test terminal 311 through the first signal trace 331, thereby achieving electrical connection with the fourth test terminal 322 of the third auxiliary test section 320 on the left side. The second test terminal 312 can be electrically connected to the test lead c located on the right side of the second test terminal 312 through the second signal trace 332, thereby achieving electrical connection with the fourth test terminal 322 of the third auxiliary test section 320 on the right side.

[0084] like Figure 7As shown, the display module 10 includes four COFs 200 arranged in sequence along the first direction of the display panel 100. Accordingly, the display panel 100 has four binding areas, each COF 200 is bound to one binding area, and each binding area is provided with two binding test parts 120. For the convenience of distinction, the binding area arranged at the left edge is recorded as the first binding area B1, the binding area arranged at the right edge is recorded as the second binding area B2, the binding test part arranged in the left edge area of ​​the binding area is recorded as the first binding test part 120a, the binding test part arranged in the right edge area of ​​the binding area is recorded as the second binding test part 120b, the COF bound to the first binding area B1 is recorded as the first COF 200a, and the COF bound to the second binding area B2 is recorded as the second COF 200b. A first crack test circuit PCD1 is provided on the left side of the display panel 100, and a second crack test circuit PCD2 is provided on the right side.

[0085] The first connection end v1 of the first crack test circuit PCD1 is an output end, electrically connected to the first binding test section 120a in the first binding area B1, and the second connection end v2 is an input end, electrically connected to the second binding test section 120b in the first binding area B1. The first connection end v1 of the second crack test circuit PCD2 is an input end, electrically connected to the first binding test section 120a in the second binding area B2, and the second connection end v2 is an output end, electrically connected to the second binding test section 120b in the second binding area.

[0086] The signal transmission circuits of the first crack test circuit PCD1 and the second crack test circuit PCD2 are similar. The signal transmission circuits of the excitation signal and the crack test signal of the first crack test circuit PCD1 are described below by taking the first crack test circuit PCD1 as an example.

[0087] The excitation signal output from the source driver chip 201a of the first flip chip film 200a is transmitted in sequence through the fourth signal transmission line 234, the sixth test pad 252, the second test terminal 312, the second signal trace 332, the fourth test terminal 322 of the third auxiliary test unit 320 on the right side and its bound fourth test pad 242, the second test signal line 232 connected to the fourth test pad 242 and the second test pad 222, and the second bound test unit 120b to the second connection end v2 of the first crack test circuit PCD1.

[0088] The crack test signal output from the first connection end v1 of the first crack test circuit PCD1 is transmitted to the source driver chip 201a in sequence through the first binding test part 120a, the second test pad 222 corresponding to the first binding test part 120a, the second test signal line 232 connected to the second test pad 222 and the fourth test pad 242, the fourth test terminal 322 bound to the fourth test pad 242, the first signal trace 331, the first test terminal 311, the fifth test pad 251, and the third signal transmission line 233.

[0089] By measuring the resistance between the first connection terminal v1 and the second connection terminal v2 of the first crack test circuit PCD1 through the source driver chip 201 a , it is possible to detect whether there is a crack in the left peripheral area of ​​the display panel 100 .

[0090] It should be noted that the “pins”, “pads” and “terminals” mentioned above are all gold finger pins used for binding connections. The reason why the gold finger pins set on the display panel 100 are called “pins”, the gold finger pins set on the chip-on-cover film 200 are called “pads”, and the gold finger pins set on the circuit board 300 are called “terminals” is only for the convenience of distinction and is not a limitation.

[0091] Compared with setting test pins, test pads and test terminals separately for the crack test circuit, the test pins, test pads and test terminals involved in the binding impedance test circuit in the multiplexing display module 10 can effectively reduce the number of binding gold finger pins of the circuit board, reduce the number of binding gold finger pins of ILB (Inner Lead Bonding) and OLB (Outer Lead Bonding) of COF, and reduce the number of binding gold finger pins of the display panel 100. The pin pitch can also be widened, which is beneficial to improve the binding yield of the product and improve the reliability quality of the module.

[0092] It is understandable that if test pins, test pads and test terminals are set separately for the crack test circuit, design reservations need to be made on the COF to ensure the universality of the COF. Then, on the COF located in the middle, the gold finger pins and signal lines originally reserved for crack testing are not used, and are used as Dummy pins and Dummy lines. After multiplexing the test pins, test pads and test terminals involved in the binding impedance test circuit, 4 gold finger pins can be saved on a single COF, and the test can be completed without reserving extra Dummy lines on the COF, which is conducive to saving the wiring space of the COF. In some application scenarios, by saving the gold finger pins and wiring space required for the COF, the originally required double-layer COF can be replaced with a single-layer COF to reduce technical requirements and production equipment costs.

[0093] Figure 8 Schematic diagram of the structure of the display device of some embodiments of the present disclosure is shown. Figure 8 As shown, some embodiments of the present disclosure provide a display device 1, including the display module 10 provided in the above embodiments. The display device 1 can be, for example, a display screen, a vehicle-mounted central control display screen, a dashboard display screen, a television, a tablet computer, a laptop computer, a digital photo frame, a navigator, and other display products or components. Of course, the display device 1 provided in the embodiments of the present disclosure is not limited to the types listed above.

[0094] It should be noted that the drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0095] Although some embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiment and all changes and modifications falling within the scope of the present disclosure.

Claims

1. A display panel, characterized in that: include: A display area and a peripheral area, wherein the peripheral area is provided with a plurality of binding areas for binding the COF, at least one of the binding areas is provided with at least two binding test parts, at least one of the binding test parts comprises a first test pin and a second test pin arranged at intervals, and the first test pin and the second test pin are electrically connected; The display panel is provided with at least one crack test circuit, and the crack test circuit is located in the peripheral area. Each of the crack test circuits has a first connection end and a second connection end, one of the first connection end and the second connection end serves as an input end, and the other serves as an output end. The first connection end and the second connection end of the same crack test circuit are respectively electrically connected to different binding test parts of the same binding area.

2. The display panel according to claim 1, characterized in that: The crack test circuit includes: a first test trace and a second test trace arranged at intervals, the second test trace is located between the first test trace and the display area, the first end of the first test trace is the first connection end, the second end of the first test trace is electrically connected to the first end of the second test trace, the second end of the second test trace is the second connection end, and the first connection end and the second connection end are located on the same side of the display panel.

3. The display panel according to claim 2, characterized in that: The at least one crack test circuit comprises a first crack test circuit and a second crack test circuit that are independently arranged, the plurality of binding areas are sequentially arranged along a first direction of the display panel, the display panel has a first side and a second side that are opposite in the first direction, a first connection end and a second connection end of the first crack test circuit are located on the first side of the display panel, and a first connection end and a second connection end of the second crack test circuit are located on the second side of the display panel; The multiple binding areas include: a first binding area and a second binding area, the first connection end and the second connection end of the first crack test circuit are respectively electrically connected to different binding test parts of the first binding area, and the first connection end and the second connection end of the second crack test circuit are respectively electrically connected to different binding test parts of the second binding area.

4. The display panel according to claim 3, characterized in that: The first binding area is a binding area closest to the first side of the display panel among the plurality of binding areas, and the second binding area is a binding area closest to the second side of the display panel among the plurality of binding areas.

5. The display panel according to claim 3, characterized in that: The peripheral area includes: a first frame area, a second frame area, a third frame area and a fourth frame area, the first frame area is arranged opposite to the third frame area, the second frame area is arranged opposite to the fourth frame area, and the plurality of binding areas are distributed in the first frame area; The third border area is provided with a first jumper wire and a second jumper wire, the first test line and the second test line in the first crack test circuit are distributed in the second border area and the third border area, and are electrically connected in the third border area through the first jumper wire, the first test line and the second test line in the second crack test circuit are distributed in the third border area and the fourth border area, and are electrically connected in the third border area through the second jumper wire.

6. The display panel according to any one of claims 1 to 5, characterized in that: The at least two binding test sections include a first binding test section and a second binding test section, the binding area includes a first edge area, a second edge area, and an intermediate area located between the first edge area and the second edge area, the first binding test section is located in the first edge area, and the second binding test section is located in the second edge area; The first connection end is electrically connected to the first binding test part through a first connection line, and the second connection end is electrically connected to the second binding test part through a second connection line. The distance between the second binding test part and the second connection end is greater than the distance between the first binding test part and the first connection end, and the routing length of the second connection line is greater than the routing length of the first connection line.

7. The display panel according to claim 6, characterized in that: The middle area is provided with a plurality of signal pins sequentially arranged along a first direction of the display panel, and the peripheral area is further provided with a plurality of signal lead lines extending along a second direction, each signal lead line is electrically connected to one of the signal pins, and the second direction intersects with the first direction; The display panel includes: a base substrate and a plurality of conductive layers stacked in sequence on the base substrate, the second connecting line includes a connecting line segment extending along the first direction, the orthographic projection of the connecting line segment on the base substrate intersects with the orthographic projection of the plurality of signal leads on the base substrate, and the connecting line segment and the plurality of signal leads are located in two different conductive layers among the plurality of conductive layers.

8. The display panel according to claim 7, characterized in that: The multiple conductive layers include: a first gate metal layer, a second gate metal layer and a source-drain metal layer, and the multiple signal leads and the connecting line segments are located in two different metal layers among the first gate metal layer, the second gate metal layer and the source-drain metal layer.

9. A display module, characterized in that: include: The display panel and multiple chip-on-films according to any one of claims 1-8, each of the chip-on-films is bound to a binding area in the display panel.

10. The display module according to claim 9, characterized in that: Each of the flip chip films is provided with a first binding pad area, a second binding pad area, a first test signal line and a second test signal line; The first binding pad area is bound to a binding area of ​​the display panel, the first binding pad area is provided with a first auxiliary test section corresponding to each binding test section of the binding area, the first auxiliary test section comprises: a first test pad and a second test pad, the first test pad is bound and connected to a first test pin of the corresponding binding test section, and the second test pad is bound and connected to a second test pin of the corresponding binding test section; The second binding pad area is used to bind the circuit board, and the second binding pad area is provided with a second auxiliary test part corresponding to each of the first auxiliary test parts, and each of the second auxiliary test parts includes: a third test pad and a fourth test pad, the first test signal line electrically connects the first test pad and the third test pad, and the second test signal line electrically connects the second test pad and the fourth test pad.

11. The display module according to claim 10, characterized in that: At least one of the multiple flip-chip films is also provided with a third signal transmission line and a fourth signal transmission line, and the second binding pad area of ​​the at least one flip-chip film is also provided with: a fifth test pad and a sixth test pad, the third signal transmission line electrically connects the fifth test pad with the source driver chip set on the flip-chip film, and the fourth signal transmission line electrically connects the sixth test pad with the source driver chip.

12. The display module according to claim 11, characterized in that: The display module further includes a circuit board, and the circuit board is provided with: a first test terminal, a second test terminal, and a third auxiliary test portion corresponding to each second auxiliary test portion, Each of the third auxiliary test parts includes: a third test terminal and a fourth test terminal, the first test terminal is bound and connected to the fifth test pad, the second test terminal is bound and connected to the sixth test pad, the third test terminal is bound and connected to the third test pad, and the fourth test terminal is bound and connected to the fourth test pad, and the first test terminal and the second test terminal are respectively electrically connected to the third test terminals or fourth test terminals of different third auxiliary test parts.

13. A display device, characterized in that: include: The display module according to any one of claims 9 to 12.

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