TDC time interval measuring unit based on FPGA carry chain

Abstract

The utility model discloses a TDC time interval measuring unit based on an FPGA carry chain, which belongs to the technical field of TDC measuring circuits and comprises a TDC unit group, a TDC sampling calibration signal generating unit and an FPGA, and the TDC unit group and the TDC sampling calibration signal generating unit are both arranged in the FPGA. Aiming at the problems, the utility model provides the TDC time interval measuring unit based on the FPGA carry chain, which is higher in resolution, higher in data processing speed and easy to transplant.

Description

Technical Field

[0001] The utility model belongs to the technical field of TDC measurement circuits, in particular to a TDC time interval measurement unit based on an FPGA carry chain. Background Art

[0002] DTOF (Direct Time-of-Flight) LiDAR is a sensor that senses the surrounding environment by sending laser pulses and measuring their return time. With the gradual improvement of industrial automation, DTOF LiDAR has been widely used in autonomous driving, mapping, construction and urban planning, drone navigation, transportation and logistics. In the DTOF LiDAR system, the time measurement unit is an indispensable component. Its measurement accuracy, pulse receiving bandwidth, parallel processing capability and power consumption will directly determine the design architecture and parameter upper limit of the entire DTOF LiDAR system.

[0003] There are two main technical routes for the time measurement units installed on the DTOF laser radars currently on the market: 1. Use a high-speed ADC to perform high-frequency sampling on the emission and reflected echoes and calculate their time intervals; 2. Pass the emission and reflected echoes through a threshold comparator and input them into a high-precision time-to-digital converter (TDC) to directly calculate the time difference between the two; There are also two branches of laser radars using the TDC solution, namely: 1. Use a dedicated TDC chip to measure time intervals; 2. Use FPGA to implement the TDC function.

[0004] The following is a brief introduction to the high-speed ADC solution mentioned above and the time interval measurement solution using a dedicated TDC chip:

[0005] 1. High-speed ADC solution: Using high-speed ADC for waveform sampling places very high requirements on the performance of ADC devices. Usually, in order to make the DTOF lidar have millimeter-level data accuracy, a high-speed ADC with a sampling rate greater than 3 GHz and a resolution greater than 8 bits is required. The device is also required to have a high signal-to-noise ratio and effective number of bits (ENOB).

[0006] 2. Use a dedicated TDC chip to measure time intervals. Using a dedicated TDC chip to implement the TDC function can achieve a measurement resolution of tens of picoseconds, but this solution still has the following pain points: 1. The data exchange rate is limited; 2. The capture pulse interval is long; 3. Multiple channels cannot be integrated.

[0007] To implement the on-chip TDC function using FPGA, the delay unit of the delay chain inside the FPGA needs to be calibrated. In order to achieve higher measurement accuracy, the delay chain needs to be calibrated bin-by-bin. The currently known calibration method is to use a gated digital oscillator circuit (such as the attachedFigure 3 ) or use a lookup table to form a ring oscillator (see attached Figure 4 ) generates a high-frequency oscillation signal and injects it into the delay chain. By recording the number of edges captured by each delay unit, a code density table can be generated, and the final calibration table can be obtained after accumulation and unit conversion.

[0008] The above two calibration signal generation methods will cause large inconsistencies in the signal flip frequency due to layout and wiring, device differences, temperature and other reasons. In order to achieve higher time resolution, some more advanced FPGA devices are required. The oscillation signal frequency achieved on such devices will far exceed the pulse capture bandwidth required by the lidar system, resulting in a serious waste of FPGA on-chip resources. In addition, the inability to capture all trigger edges will lead to inconsistent trigger probabilities for each delay unit, affecting the final calibration results and, in turn, the final measurement accuracy. Utility Model Content

[0009] In view of the above problems, the utility model provides a TDC time interval measurement unit based on FPGA carry chain which has higher resolution, higher data processing speed and is easy to transplant.

[0010] To achieve the above object, the technical solution adopted by the utility model is: a TDC time interval measurement unit based on FPGA carry chain, including a TDC unit group, a TDC sampling calibration signal generation unit and an FPGA, wherein the TDC unit group and the TDC sampling calibration signal generation unit are both arranged in the FPGA;

[0011] The TDC unit group is composed of a TDC coarse counting unit, a single TDC unit, and a TDC unit conversion unit, and the single TDC unit is configured as TDC_FIRE_UNIT and TDC_REF_UNIT;

[0012] The single TDC unit is composed of a carry chain input selector, a TDC calibration control module, a calibration result lookup table, a delayed carry chain, a carry chain output result encoder, and a measurement data screening module, and the calibration result lookup table is a pingpong structure;

[0013] The TDC sampling calibration signal generating unit is connected to the TDC unit group, the TDC coarse counting unit is connected to TDC_FIRE_UNIT and TDC_REF_UNIT respectively, and the TDC unit conversion unit is connected to TDC_FIRE_UNIT and TDC_REF_UNIT respectively;

[0014] The carry chain input selector is respectively connected to the TDC sampling calibration signal generating unit, the TDC calibration control module and the delayed carry chain, the delayed carry chain is connected to the carry chain output result encoder, the carry chain output result encoder is respectively connected to the TDC calibration control module and the measurement data screening module, the TDC calibration control module is connected to the calibration result lookup table, and the measurement data screening module is connected to the calibration result lookup table.

[0015] As a further improvement of the solution: a plurality of TDC_FIRE_UNITs and TDC_REF_UNITs are provided in the TDC unit group to process a plurality of groups of FIRE and REF signals;

[0016] The single TDC unit calculates the relative signal arrival time based on the coarse count value of the TDC coarse count unit and the fine count value generated by the carry chain inside the single TDC unit and sends it to the TDC unit conversion unit. The TDC unit conversion unit subtracts the signal arrival time measured by TDC_REF_UNIT and TDC_FIRE_UNIT and converts the unit to obtain the final absolute time interval and output it to the outside.

[0017] As a further improvement of the scheme: the TDC sampling calibration signal generating unit is composed of one or more PLLs in the FPGA chip, which respectively generate a phase-stable clock signal TDC_CLK for coarse counting and fine counting sampling, a dynamic phase modulation signal SPL_CLK with the same frequency as TDC_CLK for calibrating the total delay length of the carry chain, and a CAL_SIG obtained after fractional division for calibrating the relative delay length of each bit delay unit.

[0018] As a further improvement of the scheme: the TDC calibration control module determines the signal source of the delayed carry chain according to the current system working state, and generates a new calibration table according to the result of the carry chain output result encoder input, and sends it to the calibration result lookup table for updating; the measurement data screening module uses the encoding value of the carry chain output result encoder input as the address, obtains the calibration value from the calibration result lookup table, and calculates the signal arrival time according to the count value of the TDC coarse counting unit.

[0019] Compared with the prior art, the beneficial effects of the utility model are:

[0020] 1. Comparison of high-speed ADC solutions

[0021] Low cost: Compared with the price of several hundred yuan for a single high-speed ADC, the BOM price of the FPGA plus the entire set of peripheral circuits used in the utility model is less than one hundred yuan;

[0022] Save board area and easy to miniaturize: The high-speed ADC chip package itself is relatively large, and an FPGA with more differential IOs is also required to read the measurement data. The utility model requires much less FPGA differential IO quantity and PCB area than the high-speed ADC solution;

[0023] Low power consumption: As mentioned above, the ADC system that meets the millimeter-level data output accuracy is generally composed of ADC, external PLL and FPGA, and its overall power consumption is greater than 4W. The TDC system used in the utility model only includes a high-power digital chip FPGA, and the operating power consumption is no more than 2W, which also has a great advantage in power consumption;

[0024] Stronger parallel processing capability: High-speed ADC solutions can generally process no more than 4 data streams at the same time. The utility model can process more signals at the same time by adding fine counting units when the data processing speed is equivalent.

[0025] 2. Comparison with dedicated TDC chips

[0026] Faster data processing speed: The utility model integrates the scanning control unit, TDC unit, and data processing unit on a single-chip FPGA, eliminating the communication time between chips and improving the processing speed of the system to support a higher laser emission frequency;

[0027] Stronger continuous pulse capture capability: As mentioned above, compared with the minimum pulse interval of 5-20ns of the dedicated TDC chip, the utility model supports a minimum continuous pulse capture interval of 1.25ns, which can well meet the application requirements of laser radar;

[0028] Stronger parallel processing capability: As described above, the present invention can integrate multiple fine counting units on a single FPGA chip, and can process more receiving signals simultaneously compared to a dedicated TDC chip.

[0029] 3. Compare the existing FPGA solutions for implementing TDC

[0030] The calibration signal is more stable: the delay unit bit width calibration signal generated by the on-chip PLL through fractional frequency division and dynamic phase modulation is more stable than the existing solution;

[0031] The probability distribution of the code density table is more uniform: the calibration signal generated by the utility model has a smaller phase shift step (more than ten picoseconds), which can scan each delay unit more evenly and better calibrate the bit width of each unit in the delay chain;

[0032] Easier to port to other platforms: Compared with the oscillation loop circuit described above, the calibration signal frequency generated by the PLL is fixed and will not change due to changes in chip models, making it easier to port to other FPGA platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a functional schematic diagram of the top-level architecture of the unit module in the present utility model.

[0034] Figure 2 It is a functional schematic diagram of the fine counting unit architecture in the utility model.

[0035] Figure 3 The schematic diagram is a circuit structure diagram of a delay unit calibration using a gated digital oscillator circuit in the prior art.

[0036] Figure 4 The schematic diagram of the circuit structure of the prior art is a circuit structure of using a lookup table to form a ring oscillator to calibrate the delay unit.

[0037] Figure 5 It is a schematic diagram comparing the calibration data and linear fitting effect of TDC_FIRE_UNIT of the on-chip TDC unit of the FPGA of the utility model in the measurement experiment.

[0038] Figure 6 It is a schematic diagram comparing the calibration data of TDC_REF_UNIT and the linear fitting effect of the on-chip TDC unit of the FPGA of the utility model in the measurement experiment.

[0039] Figure 7 This is a data relationship diagram of the echo front distance value and the distance value measured by TDC in the measurement experiment of the FPGA off-chip TDC chip MS1005 used for comparison.

[0040] Figure 8 Schematic diagram of the relationship between the difference between the MS1005 output distance value and the on-chip TDC output distance value in the comparison measurement experiment and the echo front distance value measured by MS1005. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the technical solution, the utility model is described in detail below in conjunction with embodiments. The description in this section is only exemplary and explanatory and should not have any limiting effect on the protection scope of the utility model.

[0042] Embodiment 1:

[0043] like Figure 1-2 As shown, the specific scheme of this embodiment is: a TDC time interval measurement unit based on FPGA carry chain, including a TDC unit group 1, a TDC sampling calibration signal generation unit 2 and an FPGA, wherein the TDC unit group 1 and the TDC sampling calibration signal generation unit 2 are both arranged in the FPGA;

[0044] The TDC unit group 1 is composed of a TDC coarse counting unit 3, a single TDC unit 4, and a TDC unit conversion unit 5, wherein the single TDC unit 4 is configured as TDC_FIRE_UNIT and TDC_REF_UNIT;

[0045] The single TDC unit 4 is composed of a carry chain input selector 41, a TDC calibration control module 42, a calibration result lookup table 43, a delayed carry chain 44, a carry chain output result encoder 45, and a measurement data screening module 46, and the calibration result lookup table is a pingpong structure;

[0046] The TDC sampling calibration signal generating unit 2 is connected to the TDC unit group 1, the TDC coarse counting unit 3 is connected to TDC_FIRE_UNIT and TDC_REF_UNIT respectively, and the TDC unit conversion unit 5 is connected to TDC_FIRE_UNIT and TDC_REF_UNIT respectively;

[0047] The carry chain input selector 41 is respectively connected to the TDC sampling calibration signal generating unit 2, the TDC calibration control module 42 and the delayed carry chain 44, the delayed carry chain 44 is connected to the carry chain output result encoder 45, the carry chain output result encoder 45 is respectively connected to the TDC calibration control module 42 and the measurement data screening module 46, the TDC calibration control module 42 is connected to the calibration result lookup table 43, and the measurement data screening module 46 is connected to the calibration result lookup table 43.

[0048] Embodiment 2:

[0049] like Figure 1-2 As shown, as a further optimization of the above embodiment: a TDC time interval measurement unit based on FPGA carry chain, comprising a TDC unit group 1, a TDC sampling calibration signal generation unit 2 and an FPGA, wherein the TDC unit group 1 and the TDC sampling calibration signal generation unit 2 are both arranged in the FPGA;

[0050] The TDC unit group 1 is composed of a TDC coarse counting unit 3, a single TDC unit 4, and a TDC unit conversion unit 5, wherein the single TDC unit 4 is configured as TDC_FIRE_UNIT and TDC_REF_UNIT;

[0051] The single TDC unit 4 is composed of a carry chain input selector 41, a TDC calibration control module 42, a calibration result lookup table 43, a delayed carry chain 44, a carry chain output result encoder 45, and a measurement data screening module 46, and the calibration result lookup table is a pingpong structure;

[0052] The TDC sampling calibration signal generating unit 2 is connected to the TDC unit group 1, the TDC coarse counting unit 3 is connected to TDC_FIRE_UNIT and TDC_REF_UNIT respectively, and the TDC unit conversion unit 5 is connected to TDC_FIRE_UNIT and TDC_REF_UNIT respectively;

[0053] The carry chain input selector 41 is respectively connected to the TDC sampling calibration signal generating unit 2, the TDC calibration control module 42 and the delayed carry chain 44, the delayed carry chain 44 is connected to the carry chain output result encoder 45, the carry chain output result encoder 45 is respectively connected to the TDC calibration control module 42 and the measurement data screening module 46, the TDC calibration control module 42 is connected to the calibration result lookup table 43, and the measurement data screening module 46 is connected to the calibration result lookup table 43.

[0054] The TDC unit group is provided with a plurality of TDC_FIRE_UNITs and TDC_REF_UNITs to process a plurality of groups of FIRE and REF signals;

[0055] The single TDC unit 4 calculates the relative signal arrival time based on the coarse count value of the TDC coarse count unit 3 and the fine count value generated by the internal carry chain of the single TDC unit 4 and sends it to the TDC unit conversion unit 5. The TDC unit conversion unit 5 subtracts the signal arrival time measured by TDC_REF_UNIT and TDC_FIRE_UNIT and converts the unit to obtain the final absolute time interval and output it to the outside.

[0056] Embodiment 3:

[0057] like Figure 1-2 As shown, as a further optimization of the above embodiment: a TDC time interval measurement unit based on FPGA carry chain, comprising a TDC unit group 1, a TDC sampling calibration signal generation unit 2 and an FPGA, wherein the TDC unit group 1 and the TDC sampling calibration signal generation unit 2 are both arranged in the FPGA;

[0058] The TDC unit group 1 is composed of a TDC coarse counting unit 3, a single TDC unit 4, and a TDC unit conversion unit 5, wherein the single TDC unit 4 is configured as TDC_FIRE_UNIT and TDC_REF_UNIT;

[0059] The single TDC unit 4 is composed of a carry chain input selector 41, a TDC calibration control module 42, a calibration result lookup table 43, a delayed carry chain 44, a carry chain output result encoder 45, and a measurement data screening module 46, and the calibration result lookup table is a pingpong structure;

[0060] The TDC sampling calibration signal generating unit 2 is connected to the TDC unit group 1, the TDC coarse counting unit 3 is connected to TDC_FIRE_UNIT and TDC_REF_UNIT respectively, and the TDC unit conversion unit 5 is connected to TDC_FIRE_UNIT and TDC_REF_UNIT respectively;

[0061] The carry chain input selector 41 is respectively connected to the TDC sampling calibration signal generating unit 2, the TDC calibration control module 42 and the delayed carry chain 44, the delayed carry chain 44 is connected to the carry chain output result encoder 45, the carry chain output result encoder 45 is respectively connected to the TDC calibration control module 42 and the measurement data screening module 46, the TDC calibration control module 42 is connected to the calibration result lookup table 43, and the measurement data screening module 46 is connected to the calibration result lookup table 43.

[0062] The TDC sampling calibration signal generating unit 2 is composed of one or more PLLs in the FPGA chip, which respectively generate a phase-stable clock signal TDC_CLK for coarse counting and fine counting sampling, a dynamic phase modulation signal SPL_CLK with the same frequency as TDC_CLK for calibrating the total delay length of the carry chain, and a CAL_SIG obtained after fractional division for calibrating the relative delay length of each bit delay unit.

[0063] Embodiment 4:

[0064] like Figure 1-2 As shown, as a further optimization of the above embodiment: a TDC time interval measurement unit based on FPGA carry chain, comprising a TDC unit group 1, a TDC sampling calibration signal generation unit 2 and an FPGA, wherein the TDC unit group 1 and the TDC sampling calibration signal generation unit 2 are both arranged in the FPGA;

[0065] The TDC unit group 1 is composed of a TDC coarse counting unit 3, a single TDC unit 4, and a TDC unit conversion unit 5, wherein the single TDC unit 4 is configured as TDC_FIRE_UNIT and TDC_REF_UNIT;

[0066] The single TDC unit 4 is composed of a carry chain input selector 41, a TDC calibration control module 42, a calibration result lookup table 43, a delayed carry chain 44, a carry chain output result encoder 45, and a measurement data screening module 46, and the calibration result lookup table is a pingpong structure;

[0067] The TDC sampling calibration signal generating unit 2 is connected to the TDC unit group 1, the TDC coarse counting unit 3 is connected to TDC_FIRE_UNIT and TDC_REF_UNIT respectively, and the TDC unit conversion unit 5 is connected to TDC_FIRE_UNIT and TDC_REF_UNIT respectively;

[0068] The carry chain input selector 41 is respectively connected to the TDC sampling calibration signal generating unit 2, the TDC calibration control module 42 and the delayed carry chain 44, the delayed carry chain 44 is connected to the carry chain output result encoder 45, the carry chain output result encoder 45 is respectively connected to the TDC calibration control module 42 and the measurement data screening module 46, the TDC calibration control module 42 is connected to the calibration result lookup table 43, and the measurement data screening module 46 is connected to the calibration result lookup table 43.

[0069] The TDC calibration control module 42 determines the signal source of the delayed carry chain 44 according to the current system working state, and generates a new calibration table according to the result input by the carry chain output result encoder 45, and sends it to the calibration result lookup table 43 for updating; the measurement data screening module 46 uses the encoding value input by the carry chain output result encoder 45 as the address, obtains the calibration value from the calibration result lookup table 43, and calculates the signal arrival time according to the count value of the TDC coarse counting unit 3.

[0070] like Figure 1-2 As shown, the working principle of this scheme is:

[0071] Top-level architecture, specific functions are:

[0072] FIRE_PULSE_IN: start pulse input

[0073] REF_PULSE_IN: Termination pulse input

[0074] TDC_CLK_UNIT: TDC module clock generation unit, responsible for generating the three clock signals required by the TDC module.

[0075] TDC_CLK: TDC module sampling clock. Registers within the module are synchronized under the TDC_CLK clock tree.

[0076] SPL_CLK: A dynamically phase-modulated clock with the same frequency and source as TDC_CLK. It is responsible for calibrating the coefficients and correcting the temperature and voltage during BIN_BY_BIN calibration.

[0077] CAL_SIG: BIN-wide calibration signal, obtained by dynamic phase adjustment after fractional frequency division by the on-chip PLL of the FPGA. It can be regarded as a random signal for TDC_CLK.

[0078] TDC_CC_CNTR: TDC coarse counting unit, responsible for synchronizing the coarse counting code values ​​(CC_CNT) of all fine counting units.

[0079] TDC_FIRE_UNIT: Start pulse fine counting unit, responsible for capturing the start pulse and calculating its arrival time (F_MDATA).

[0080] TDC_REF_UNIT: Termination pulse counting unit, responsible for capturing the termination pulse and calculating its arrival time (REF_MDATA).

[0081] TDC_UNIT_CONV: Data processing unit, responsible for subtracting the end signal from the start signal, converting it into a unified distance unit and then outputting it.

[0082] The detailed counting unit architecture has the following specific functions:

[0083] TDC_CLK: TDC module sampling clock, frequency 200 MHz. Registers in the module are synchronized under the TDC_CLK clock tree.

[0084] SIG_MUX: Carry chain input signal selector, controls the signal source input according to the current TDC module calibration and measurement status.

[0085] SPL_CLK: A dynamically phase-modulated clock with the same frequency and source as TDC_CLK. It is responsible for calibrating the coefficients and correcting the temperature and voltage during BIN_BY_BIN calibration.

[0086] PULSE_IN: external pulse input, measured signal.

[0087] CAL_SIG: BIN-wide calibration signal, obtained by on-chip PLL after fractional frequency division and dynamic phase modulation, which can be regarded as a random signal for TDC_CLK.

[0088] SIG_IN_SEL: Input data selection signal, given by the CAL_CTRLER module, responsible for selecting one of the three signals to the carry chain unit.

[0089] SIG_IN: Carry chain unit input signal.

[0090] CARRY_CHAIN: Carry chain delay unit, composed of multiple levels of fast carry logic, each level of carry output C_OUT is stored in a register and output to the encoder unit for data format conversion.

[0091] ENCODER: Encoder unit, responsible for converting the one-hot code output by the carry chain into binary code and passing the data to the calibration unit and the data screening unit.

[0092] CAL_CTRLER: Calibration control unit, controls the TDC module to perform BIN_BY_BIN dynamic calibration, and writes the newly generated calibration netlist into pingpong_lut for the data screening unit to correct the measurement data.

[0093] CAL_PINGPONG_LUT: Ping-Pong calibration data lookup table. When a new calibration netlist is generated, the RAM port of the newly generated netlist is output and the data of the old netlist is copied.

[0094] DATA_SEL: measurement data screening unit, which caches the original measurement data output by the encoder, performs unit conversion and outputs it after legality check.

[0095] The designed FPGA on-chip TDC unit is deployed on a 2D rotating mirror DTOF lidar, which can achieve a 25hz frame rate and 72Khz laser emission frequency.

[0096] In order to detect the data quality of the TDC unit on the FPGA chip, the prototype is equipped with an off-chip TDC chip MS1005. The main parameters of the chip are as follows:

[0097] Dual-channel single-precision mode 60ps;

[0098] Single channel double precision mode 30ps;

[0099] Non-calibrated measurement range 3.5ns (0ns) to 25μs;

[0100] Single precision calibration measurement range 3.5ns (0ns) to 16μs;

[0101] Double precision calibration measurement range 3.5ns (0ns) to 4μs;

[0102] 20ns minimum pulse interval.

[0103] By making the FPGA's on-chip TDC unit and the MS1005 chip measure the same transmit and receive signal and comparing the difference between the two, the measurement performance of the FPGA's on-chip TDC unit can be intuitively evaluated.

[0104] The test data is as follows:

[0105] CAL_PINGPONG_LUT data quality:

[0106] like Figure 5-6 As shown, Figure 5 Calibration data for TDC_FIRE_UNIT, Figure 6 is the calibration data of TDC_REF_UNIT. In the figure, the horizontal axis is the serial number of the delay unit in the entire delay chain, and the vertical axis is the calibration value.

[0107] It can be seen that the overall linearity is good and there is no large dead zone; the delay times of the two delay chains are similar, and the slope error after fitting is about one thousandth.

[0108] After converting the units of the two calibration tables into picoseconds, we get the following table:

[0109] Mean Standard Deviation sum Minimum median Maximum FIRE 16.62564 4.39651 6434.1227 5.42535 16.61513 39.33377 REF 16.63703 4.05718 6438.5308 6.4426 16.61513 36.96018

[0110] The average delay of the delay units in the two delay chains is about 16.6ps, which is equivalent to a distance of about 2.5mm, which is better than the single-channel 60ps of MS1005.

[0111] The two delay chains were calibrated repeatedly to verify the stability of the calibration data. The results are shown in the following table:

[0112] Mean Standard Deviation sum Minimum median Maximum FIRE 18913.733 14.84386 567412 18889 18911 18944 REF 19067.7 14.15712 572031 19035 19063 19098

[0113] Analyzing the data, it can be found that the total length fluctuation error of the two delay chains is less than 5ps, which is equivalent to a distance of 0.76mm, which can meet the data stability requirements of the lidar.

[0114] The following is a display of the measurement data quality

[0115] Systematic error:

[0116] like Figure 7 As shown in the figure, the horizontal axis is the echo front distance value (unit CM) measured by MS1005, and the vertical axis is the distance value (unit CM) measured by the on-chip TDC. After fitting, it can be found that the two are highly linearly related, and the slope is approximately equal to 1.

[0117] like Figure 8 As shown in the figure, the relationship between the difference between the two and the distance changes is observed. The horizontal axis is the echo front distance value (unit CM) measured by MS1005, and the vertical axis is the difference between the distance value output by MS1005 and the distance value output by on-chip TDC. After fitting, it can be seen that the difference between the distance values ​​output by the two has basically nothing to do with the distance. It is a fixed offset error of the system, which can be simply eliminated during distance measurement. There is no systematic error on the on-chip TDC that changes with distance.

[0118] Fluctuation error:

[0119] Comparing the fluctuation error of the output data of MS1005 and on-chip TDC, the following table is obtained:

[0120]

[0121]

[0122] It can be seen that the fluctuation errors of the two are in the same order of magnitude.

[0123] Data processing speed:

[0124] When the on-chip TDC has a ranging window of 1us and a dynamic calibration window of 500ns, the single measurement time is 2.028us (O-T0); the single measurement time of MS1005 for processing the same data is 7.528us. The maximum measurement frequency supported by the on-chip TDC can exceed 400Khz, while that of MS1005 is about 125Khz.

[0125] In contrast, the on-chip TDC solution will be significantly ahead of the solution using an off-chip TDC chip in terms of maximum measurement frequency.

[0126] It should be noted that, in this article, the terms include, contain or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. Specific examples are used in this article to illustrate the principle and implementation of the technical solution of the utility model. The above examples are only used to help understand the method and core idea of ​​the utility model. The above are only preferred implementations of the utility model. It should be pointed out that due to the limitations of textual expression and the objective existence of infinite specific structures, for ordinary technicians in this technical field, without departing from the principle of the utility model, several improvements, modifications or changes can be made, and the above technical features can also be combined in an appropriate manner; these improvements, modifications, changes or combinations, or the direct application of the concept and technical solution of the utility model to other occasions without improvement, should be regarded as the protection scope of the utility model.

Claims

1. A TDC time interval measurement unit based on FPGA carry chain, characterized in that: It comprises a TDC unit group (1), a TDC sampling calibration signal generating unit (2) and an FPGA, wherein the TDC unit group (1) and the TDC sampling calibration signal generating unit (2) are both arranged in the FPGA; The TDC unit group (1) is composed of a TDC coarse counting unit (3), a single TDC unit (4), and a TDC unit conversion unit (5), wherein the single TDC unit (4) is configured as TDC_FIRE_UNIT and TDC_REF_UNIT; The single TDC unit (4) is composed of a carry chain input selector (41), a TDC calibration control module (42), a calibration result lookup table (43), a delayed carry chain (44), a carry chain output result encoder (45), and a measurement data screening module (46), wherein the calibration result lookup table is a pingpong structure; The TDC sampling calibration signal generating unit (2) is connected to the TDC unit group (1), the TDC coarse counting unit (3) is respectively connected to TDC_FIRE_UNIT and TDC_REF_UNIT, and the TDC unit conversion unit (5) is respectively connected to TDC_FIRE_UNIT and TDC_REF_UNIT; The carry chain input selector (41) is respectively connected to the TDC sampling calibration signal generating unit (2), the TDC calibration control module (42) and the delayed carry chain (44); the delayed carry chain (44) is connected to the carry chain output result encoder (45); the carry chain output result encoder (45) is respectively connected to the TDC calibration control module (42) and the measurement data screening module (46); the TDC calibration control module (42) is connected to the calibration result lookup table (43); and the measurement data screening module (46) is connected to the calibration result lookup table (43).

2. The TDC time interval measurement unit based on FPGA carry chain according to claim 1, characterized in that: The TDC unit group is provided with a plurality of TDC_FIRE_UNITs and TDC_REF_UNITs to process a plurality of groups of FIRE and REF signals; The single TDC unit (4) calculates the relative signal arrival time according to the coarse count value of the TDC coarse count unit (3) and the fine count value generated by the internal carry chain of the single TDC unit (4), and sends it to the TDC unit conversion unit (5). The TDC unit conversion unit (5) subtracts the signal arrival time measured by TDC_REF_UNIT from that measured by TDC_FIRE_UNIT and converts the unit to obtain the final absolute time interval and outputs it externally.

3. The TDC time interval measurement unit based on FPGA carry chain according to claim 1, characterized in that: The TDC sampling calibration signal generating unit (2) is composed of one or more PLLs in the FPGA chip, which respectively generate: A phase-stable clock signal TDC_CLK for coarse and fine count sampling, A dynamic phase modulation signal SPL_CLK with the same frequency as TDC_CLK for calibration of the total delay length of the carry chain, A CAL_SIG obtained by dividing the fractional frequency used to calibrate the relative delay length of each delay unit.

4. The TDC time interval measurement unit based on FPGA carry chain according to claim 1, characterized in that: The TDC calibration control module (42) determines the signal source of the delay carry chain (44) according to the current system working state, generates a new calibration table according to the result input by the carry chain output result encoder (45), and sends it to the calibration result lookup table (43) for updating; The measurement data screening module (46) uses the code value input by the carry chain output result encoder (45) as an address, obtains the calibration value from the calibration result lookup table (43), and calculates the signal arrival time according to the count value of the TDC coarse counting unit (3).

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