High-level synthesis method and system

A high-level synthesis, compatible graph technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as the inability to meet area design requirements, and achieve the effect of reducing interconnection overhead and rapid generation

Inactive Publication Date: 2012-04-18
SUN YAT SEN UNIV
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Problems solved by technology

However, in the process of executing the scheduling, its design constraints are usually determined based on manual experience, which generally only includes information on the number of hardware resources, but not hardware interconnection information. Therefore, the circuit structure generated by this system , which often cannot meet the design requirements of optimal area

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  • High-level synthesis method and system
  • High-level synthesis method and system

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Embodiment Construction

[0048] Depend on figure 1 and figure 2 As can be seen, a high-level synthesis method, the method steps include:

[0049] A. Obtain a description of the behavior of the digital circuit, and then generate a data flow diagram;

[0050] B. Pre-allocate hardware resources according to the data flow diagram, and then generate a resource constraint list;

[0051] C. Scheduling according to the resource constraint list and data flow graph;

[0052] D. Resource allocation is performed according to the scheduling results;

[0053] E. Generate a hardware circuit structure according to the resource allocation result and the scheduling result.

[0054] The above data flow diagram is as follows image 3 As shown, the nodes in the figure represent different types of operations, and the arrows represent the direction of data flow, that is, the data dependencies between operations; the scheduling is the process of allocating operations to each control step, and the resource allocation is...

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Abstract

The invention discloses a high-level synthesis method and a high-level synthesis system. The system comprises a data flow chart generation unit, a pre-allocation unit, a scheduling unit, a resource allocation unit and a circuit generation unit. The method comprises the following steps of: firstly, acquiring behavior description of a digital circuit; secondly, generating a data flow chart; thirdly, pre-allocating hardware resources; fourthly, generating a resource constraint list; sixthly, performing scheduling and resource allocation; and finally, generating a hardware circuit structure. By adoption of the method and the system, during the scheduling, number information of the hardware resources is scheduled, information of hardware interconnection is also scheduled, and manual determination of schedule restraints can be avoided, therefore, the hardware circuit structure can be generated more quickly, and the interconnection overhead in the hardware circuit structure is effectively reduced. The high-level synthesis method and the high-level synthesis system are widely applied in the field of designing the hardware circuit structure.

Description

technical field [0001] The invention relates to a method and a system for designing a hardware circuit structure, in particular to a high-level synthesis method and system combining scheduling and resource allocation based on a compatibility graph. Background technique [0002] Scheduling and resource allocation algorithm flow is a research hotspot in the field of high-level synthesis. [0003] Scheduling algorithms are classified according to their implementation methods, which can be mainly divided into construction method, transformation method and integer linear programming method. The construction method is to select an operation each time, then select an appropriate control step, and then schedule the operation to the selected control step until all operations are scheduled to complete. However, the key to the construction method is how to Select the next scheduling operation, and how to select the appropriate control step to place the selected operation; the transfor...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 陈弟虎郑洪滨王自鑫
Owner SUN YAT SEN UNIV
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