Method and system for controlling high-speed interface in multi-processor system-on-chip
A multi-core system, high-speed interface technology, applied in transmission systems, digital transmission systems, instruments, etc., can solve the problems of slow processing units, indeterminate states, etc.
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[0054] The present invention is shown by way of examples, but is not limited to the drawings, in which the same reference numbers represent similar structures.
[0055] The following describes the present invention in further detail with reference to specific embodiments:
[0056] reference figure 2 , Is the control system of the present invention, including data packet processing unit 202, data packet information register 204, receiving buffer 206, sending buffer 208, receiving controller 210, sending controller 212, valid flag 214, thread mailbox 216 and Large-capacity dynamic random access memory DRAM218, of which:
[0057] The data packet processing unit 202, as a core component of the network processor packet processing, frequently exchanges data with other units. In this embodiment, the data packet processing unit includes four data packet receiving processing units and two data packet sending processing units. The six data packet processing units serve as the master and are ...
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