Method and system for controlling high-speed interface in multi-processor system-on-chip

A multi-core system, high-speed interface technology, applied in transmission systems, digital transmission systems, instruments, etc., can solve the problems of slow processing units, indeterminate states, etc.

CN102662908AInactive Publication Date: 2012-09-12XIDIAN UNIV
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
Publication Date
2012-09-12
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention discloses a method and a system for controlling a high-speed interface in a multi-processor system-on-chip, which are mainly used for solving the problems of low efficiency of receiving and sending data of the existing system. The system comprises data packet processing units, a data packet information register, a mailbox and an effective marker bit, wherein each data packet processing unit comprises multiple threads; at the data receiving end, the threads are used for directly sending out receiving requests at the speed which is close to the line speed, receiving data packets according to the receiving requests and generating data packet information; the data packet information is placed into the data packet information register, and the threads are used for keeping the sequence of the received data packets according to the data packet information in the data packet information register and working state information in the thread mailbox; and at the data sending end, the threads are used for accurately sending the data packets to corresponding ports of external equipment at high speed according to the position situation of the effective marker bit and information of a control domain. The system disclosed by the invention has the advantages of receiving and sending the data with high efficiency and reliability, and can be used for processing the network data.
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Description

technical field

[0001] The invention belongs to the technical field of communication equipment, and particularly relates to a control method and system of a high-speed interface, which can be used for receiving and sending data in an on-chip multi-core system. Background technique

[0002] System-on-a-chip can generally be divided into three parts according to functions, which are data processing part, data storage part and data exchange interface part. Whether data can enter the system-on-chip system quickly and reliably and be processed in a timely manner is directly related to the overall performance of the system, such as In a common network processor, multiple multi-threaded packet processing units, usually called PE, general-purpose main processor ARM, high-speed small-capacity static random access memory SRAM, large-capacity dynamic random access memory DRAM, data exchange interface unit constitute. Usually, the performance parameters for assessing network processors...

Examples

Embodiment Construction

[0054] The present invention is shown by way of example, but not limitation, in the accompanying drawings, in which like reference numbers represent similar structures.

[0055] Below in conjunction with specific embodiment, the present invention is described in further detail:

[0056] refer to figure 2 , is the control system of the present invention, comprising packet processing unit 202, packet information register 204, receiving buffer 206, sending buffer 208, receiving controller 210, sending controller 212, valid flag 214, thread mailbox 216 and Large-capacity dynamic random access memory DRAM218, wherein:

[0057] The data packet processing unit 202, as the core element of network processor packet processing, frequently exchanges data with other units. In this embodiment, the data packet processing unit includes four data packet receiving processing units and two data packet sending processing units. The six data packet processing units, as the main control end, are...