Double-instruction multi-floating-point operand division operation controller

Abstract

The invention provides a double-instruction multi-floating-point operand division operation controller which comprises a dual-port read-only and write-only memory, an instruction and multi-operand writing time sequence control module, a floating-point operand reading time sequence control module, a memory data vacant marker controller and a configuration operation and output control module; the controller adopts an FPGA (Field Programmable Gate Array) design so as to be in hard link with a control circuit, two instructions can be stored and can be subjected to parallel processing; when one instruction is executed, the other instruction is to be executed; or when one instruction is executed, the other instruction is read in; or one instruction operand is subjected to writing-in and reading-out treatment at the same time; a writing time sequence pulse generated in the controller is used for controlling the continuous writing-in of multiple operands; a reading time sequence pulse synchronous with a system Clock automatically controls the division operation of multiple floating-point operands without occupying a system bus; execution of one instruction is equivalent to the execution of multiple division instruction based on a microprocessor, so that the operation times of performing instruction taking, coding, floating-point operand transmission and operation result write-back on the instructions by the system can be reduced.

Description

technical field [0001] The invention relates to a dual-instruction multi-floating-point operand division controller, in particular to a dual-instruction multi-floating-point operand division control circuit and a timing control method based on the hard connection of an FPGA parallel operation circuit. Background technique [0002] The floating-point number division operator realizes the division operation of two 32-bit floating-point numbers conforming to the IEEE754 standard; the division operation is several times longer than the addition / subtraction operation and multiplication operation, and the system needs to output 2 floating-point operands in time before each operation , or 1 floating-point operand, the 2 operand inputs of the arithmetic unit need 2 registers to ensure the stability of the dividend and divisor input during the division operation, and the microprocessor can transfer to Process other programs, and read the operation results in time-sharing after the op...

AI Technical Summary

Problems solved by technology

[0002] The floating-point number division operator realizes the division operation of two 32-bit floating-point numbers conforming to the IEEE754 standard; the division operation is several times longer than the addition / subtraction operation and multiplication operation, and the system needs to output 2 floating-point operands in time before each operation , or 1 floating-point operand, the 2 operand inputs of the arithmetic unit need 2 registers to ensure the stability of the dividend and divisor input during the division operation, and the microprocessor can transfer to Process other programs, and read the operation results in time-sharing after the operation is completed; for the continuous execution of the division operation of multiple operands, and the operation results are used as the dividend, the microprocessor needs to transmit the operand as the divisor and the operation as the dividend multiple times in time-sharing The operation of writing back the result; the design of the floating-point number division operator also adopts the method of pipeline execution, and the operation process is divided into several modules. The modules are executed sequentially, and the operation result of each instruction in the pipeline needs to be written back after the operation; but for the executed floating-point number division operation, the operation result of the previous operation instruction needs to be used as the dividend instruction, so the pipeline of the floating-point number division operation The operation loses its effect, which affects the execution speed of the floating-point number division operation instruction

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