RLE and LZW-based optimized bit file compression and decompression method

Abstract

The invention discloses an RLE and LZW-based optimized bit file compression and decompression method. By performing data format analysis on an FPGA configuration bit file, a head control word of the bit file is extracted; preliminary compression is performed by adopting an RLE code with the run length of 4 from real configuration data; and then LZW compression is performed, so that the compression rate is further increased. The decompression is an inverse process of compression; and LZW decompression is performed to recover intermediate data first, and then a data part which does not contain the head control word is subjected to RLE decompression to recover the original FPGA configuration bit file. The method comprehensively considers compression / decompression time and compression rate; compared with a compression tool of Xilinx, single use of an RLE algorithm and single use of an LZW algorithm, the method has the advantages that the win-win purpose of the compression rate and the compression speed is achieved; and the problem of an excessively large FPGA configuration bit file of advanced type of Xilinx is solved, the overhead of a storage chip is reduced, and a key technical support is provided for an FPGA in-orbit reconstruction technology.

Description

technical field [0001] The invention relates to an optimized bit file compression and decompression method based on RLE and LZW, and belongs to the technical field of bit file compression and decompression in communication. Background technique [0002] With the increase in the complexity of on-board applications, the requirements for on-board data processing capabilities are getting higher and higher, and the FPGA models used have to use higher-level devices with the increase in application complexity. Due to the more powerful functions of these advanced FPGA models, the corresponding bit files have also become larger. The bit files of an FPGA configured with a V5130T have increased by about 3 times compared with the V4SX55, which means that the application of a V5 FPGA requires the past 3 Times the storage resources to store the configuration bits, which is undoubtedly a problem for the limited resources on the star, and certain compression methods must be adopted to reduc...

AI Technical Summary

Problems solved by technology

It can be seen from the following experimental data that the bit file compression rate compressed by Xilinx is not high

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