Peripheral component interconnect (PCI) memory space optimization method and device

A technology of memory space and optimization method, which is applied in the computer field and can solve problems such as insufficient system memory space

Active Publication Date: 2017-05-10
HANGZHOU DPTECH TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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[0003] In view of this, the application provides a PCI memory space optimization meth...

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  • Peripheral component interconnect (PCI) memory space optimization method and device
  • Peripheral component interconnect (PCI) memory space optimization method and device

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Embodiment Construction

[0025] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this application. Rather, they are merely examples of devices and methods consistent with aspects of the present application as recited in the appended claims.

[0026] The terminology used in this application is for the purpose of describing particular embodiments only, and is not intended to limit the application. As used in this application and the appended claims, the singular forms "a", "the", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the term "an...

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Abstract

The present invention provides a peripheral component interconnect (PCI) memory space optimization method and device. The method comprises the steps that a processor determines, based on a scanned PCI configuration space of a PCI device, a theoretical memory space of the PCI device, allocates an actual memory space for the PCI device according to an actual memory space required by the PCI device actually and an address alignment rule, and determines the theoretical memory space of the PCI device according to a start address of the actual memory space, the actual memory space, the theoretical memory space, and a previous final address offset and an address alignment rule of the PCI device; and the processor sends the final address offset of the PCI device to a PCI bridge of the PCI device to store, and sends the theoretical memory space to the PCI device to store. Through adoption of the PCI memory space optimization method and device, the system memory space is saved, and limited system memory space is fully used.

Description

technical field [0001] The present application relates to the field of computer technology, in particular to a PCI memory space optimization method and device. Background technique [0002] In the network device, the processor can coordinate and control the PCI device through the PCI (Peripheral Component Interconnect, peripheral device interconnection) bus, so as to make the device run normally. When the network device is powered on or a new PCI device is connected to the network device, the processor can read the PCI configuration space of the PCI device, and determine the size of the PCI memory space required by the PCI device based on the PCI configuration space. Processor can allocate system memory space for this PCI device according to the PCI memory space size, and write the system memory space into the BAR (Base Address Register, base address register) of this PCI device as PCI memory space, subsequent processor and the The PCI device can perform data interaction th...

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Application Information

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IPC IPC(8): G06F12/02G06F9/50
CPCG06F9/5016G06F12/023
Inventor 邢彬朝秦德楼刘小兵
Owner HANGZHOU DPTECH TECH
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