Channel adaptive adc-based receiver

A receiver and adaptation technology, applied in transmitter/receiver shaping network, baseband system, baseband system components, etc., can solve problems such as high-speed communication links or different signal loss levels of channels

Active Publication Date: 2018-03-16
XILINX INC
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  • Claims
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Problems solved by technology

Based on these principles, high-speed communication li

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  • Channel adaptive adc-based receiver
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  • Channel adaptive adc-based receiver

Examples

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Embodiment Construction

[0039] In the following description, numerous specific details are set forth in order to provide a more thorough explanation of the specific examples described herein. It will be apparent, however, to one skilled in the art that one or more other examples and / or variations of these examples may be practiced without using all of the specific details presented below. In other instances, well-known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same numerical designations are used on different figures to refer to the same items; however, in alternative examples, these items may be different.

[0040] Before describing in detail several examples shown illustratively in the figures, a general introduction is provided to facilitate understanding.

[0041] Because the channel may have noise, such as inter-symbol interference ("ISI", inter-symbol interference), among other types of noise, the recei...

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Abstract

A receiver (100) relates generally to channel adaptation. In this receiver (100), a first signal processing block (101) is coupled to a communications channel (20). The first signal processing block (101) includes: an AGC block (102) and a CTLE block (103) for receiving a modulated signal (21) for providing an analog signal (104); an ADC (105) for converting the analog signal (104) to digital samples (106); and an FFE block (112) for equalizing the digital samples (106) to provide equalized samples (114). A second signal processing block (111) includes: a DFE block (113) for receiving the equalized samples (114) for providing re-equalized samples (116); and a slicer (123) coupled to the DFE block (113) for slicing the re-equalized samples (116). A receiver adaptation block (150) is coupledto the first signal processing block (101) and the second signal processing block (111). The receiver adaptation block (150) is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel (20).

Description

technical field [0001] This description refers to integrated circuits ("ICs"). More specifically, this description relates to channel-adapted analog-to-digital converter based receivers for ICs. Background technique [0002] High-speed serial communication circuits, such as, for example, the input side of 40 gigabits / second ("Gbits / s") or faster serializer-deserializers ("SerDes"), conventionally use signal processing circuitry to at least Achieving the target bit error rate. Based on these principles, high-speed communication links or channels may have different levels of signal loss. Therefore, adapting a channel-adapted analog-to-digital converter (“ADC-based”) receiver (such as, for example, a channel-adapted ADC-based SerDes receiver) to dynamically changing signal channel transmission conditions to at least achieve the target error Bit rate is useful. Contents of the invention [0003] A receiver is generally concerned with channel adaptation. In such a receiver...

Claims

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Application Information

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IPC IPC(8): H04L25/03
CPCH04L25/03057H04L25/03885H04L27/3809
Inventor 廖宇G·张张洪涛张琨永T·帕姆Z·D·吴
Owner XILINX INC
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