Method and device for detecting stability of phase-locked loop output clock signal

Abstract

The invention relates to a method and a device for detecting stability of a phase-locked loop output clock signal. The method comprises the steps of detecting a clock signal entering a first clock domain, if a rising edge occurs, obtaining a sampling signal, transmitting the sampling signal from the first clock domain to a second clock domain and enabling a counter to count pulses of the samplingsignal; feeding the pulses back to the first clock domain to generate a count stopping signal, sending the count stopping signal from the first clock domain to the second clock domain, controlling thecounter to stop counting, and storing an obtained counting value to the counter; and comparing the obtained adjacent two counting values via a value comparer till a difference between the two counting values is smaller than a preset fixed value. Through two times of synchronously counting, if the difference between the two times of counting is smaller than the preset value, an output frequency ofa phase-locked loop signal is indicated to be stable, so the frequent switching of a clock frequency is avoided; and thus the problem that a phase-locked loop clock signal is output unstably in an integrated circuit is solved.

Description

technical field [0001] The invention relates to the field, in particular to a method for detecting the stability of a phase-locked loop output clock signal, and also relates to a detection device for the stability of the phase-locked loop output clock signal. Background technique [0002] Usually, in the realization of large-scale digital circuits, the clock signal is the key signal to drive the operation of the circuit, and its signal quality is related to whether the circuit can operate correctly. [0003] In the prior art, taking a system on chip (SoC) as an example, different modules will work in different clock domains, so as to reduce the dynamic power consumption caused by signal inversion as much as possible under the premise of meeting the computing performance requirements. What's more, a module will switch clock frequency due to changes in computing load during operation. [0004] Due to the frequent switching of the clock frequency during the operation of the in...

AI Technical Summary

Problems solved by technology

[0004] Due to the frequent switching of the clock frequency during the operation of the integrated circuit, there is a problem of unstable clock signal output

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