A gate switch circuit and a memory including the circuit

Abstract

The present invention discloses a gating switch circuit and a memory including the circuit, wherein the gating switch circuit comprises: a storage unit connection terminal, a read switch tube, a programming switch tube, a read input terminal and a programming input terminal, wherein the number of the read switch tube is one, and the read input terminal is connected to the storage unit connection terminal through the read switch tube, and is used to conduct the storage unit connection terminal and the read input terminal when receiving a read control signal. The gating switch circuit provided by an embodiment of the present invention reduces the conduction resistance of the gating switch circuit, increases the conduction speed, and thus improves the reading speed when performing a read operation on the storage unit by controlling a read switch tube to conduct the path between the read input terminal and the storage unit connection terminal.

Description

Technical Field

[0001] The present invention relates to the technical field of memory, and in particular to a gating switch circuit and a memory comprising the circuit. Background Art

[0002] Flash memory is a non-volatile memory that uses a non-linear macrocell mode internally. It has the advantages of large capacity and fast rewrite speed, and is suitable for storing large amounts of data.

[0003] In flash memory, a storage cell can be regarded as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Figure 1 It is a common MOSFET structure diagram, including gate 20, source 21, drain 22, P-type silicon semiconductor substrate 23, and tunneling oxide layer 24. The connections between them are as follows: the P-type silicon semiconductor substrate 23 diffuses two N-type regions, a tunneling oxide layer 24 is covered on the P-type silicon semiconductor substrate 23, and finally two holes are made on the N-type region by etching, and three electrodes are made on the insulating layer and in the two holes by metallization: gate 20, source 21 and drain 22, the source 21 and drain 22 correspond to the two N-type regions respectively, and the gate 20 is the word line of the storage unit, and the drain 22 is the bit line of the storage unit. Further, the gate 20 includes a control gate 201, an inter-polysilicon dielectric 202 (Inter Poly Dielectric, IPD), and a floating gate 203, and the floating gate 203 stores charge. The flash memory stores data by changing the number of electrons in the floating gate 203.

[0004] When reading a memory cell in a flash memory, after applying a read voltage, the memory cell generates a current, and the current flowing through the memory cell is compared with the reference current through a current comparator. If the current comparator outputs a high level, it indicates that the current storage state of the memory cell is an erased state, that is, the read data is "1"; if the current comparator outputs a low level, it indicates that the current storage state of the memory cell is a programmed state, that is, the read data is "0". For details, please refer to Figure 2 As shown in the circuit structure diagram of the memory cell read operation, the drain 22 of the memory cell is connected to the input terminal SENBL of the current comparator 26 through the gate switch circuit 25, and the current flowing through the drain 22 is compared with the reference current IREF of the current comparator 26 to obtain the current storage state of the memory cell; further, see Figure 3The circuit structure diagram of the commonly used gating switch circuit 25 in the prior art shown in the figure includes a storage unit connection terminal connected to the drain 22 of the storage unit; and also includes a common switch tube hn2, a read switch tube hn3, a programming switch tube hn4 and a discharge switch tube hn1, as well as a read input terminal SENBL and a programming input terminal PGMBL. When the storage unit is read, the drain 22 of the storage unit is connected to the input terminal in the gating switch circuit 25, and the conduction of the common switch tube hn2 is controlled by the first read control signal YA_S, and the conduction of the read switch tube hn3 is controlled by the second read control signal YB_S, so that the path between the drain 22 of the storage unit and the input terminal SENBL of the current comparator 26 is connected. When the storage unit is programmed, it is necessary to control the conduction of the common switch tube hn2 by the first programming control signal YA_P, and control the conduction of the programming switch tube hn4 by the second programming control signal YB_P, so that the path between the drain 22 of the storage unit and the programming input terminal PGMBL is connected.

[0005] Obviously, in order to connect the path between the drain 22 of the storage unit and the read input terminal SENBL of the current comparator 26, it is necessary to turn on the common switch tube hn2 and the read switch tube hn3. The on-resistance is the sum of the resistances of the common switch tube hn2 and the read switch tube hn3. Therefore, the on-resistance is large. In order to obtain an ideal read voltage, a large on-resistance will make the charging time of the drain of the storage unit longer, thereby slowing down the reading speed and placing higher requirements on the design of the current comparator 26. At the same time, the first read control signal YA_S for controlling the conduction of the common switch tube hn2 and the second read control signal YB_S for controlling the conduction of the read switch tube hn3 need to be coordinated, which increases the complexity of the entire read operation. Summary of the invention

[0006] The embodiment of the present invention provides a gating switch circuit and a memory including the same, which reduces the on-resistance of the gating switch circuit and increases the on-speed when performing a read operation on a memory cell, thereby improving the reading speed.

[0007] In a first aspect, an embodiment of the present invention provides a gating switch circuit, the circuit comprising:

[0008] A storage unit connection end, a read switch tube, a programming switch tube, a read input end and a programming input end. The number of the read switch tube is one. The read input end is connected to the storage unit connection end through the read switch tube, and is used to conduct the storage unit connection end and the read input end when a read control signal is received.

[0009] Furthermore, the number of the programming switch tubes is two, and the programming input terminal is connected to the storage unit connection terminal through two programming switch tubes connected in series, so as to conduct the storage unit connection terminal and the programming input terminal when two programming control signals are received respectively.

[0010] Furthermore, the circuit further comprises: a discharge switch tube, through which the storage unit connection end is grounded and is used for discharging under the control of a discharge signal.

[0011] Exemplarily, the switch tube is a MOS tube.

[0012] In a second aspect, an embodiment of the present invention further provides a memory, comprising a storage unit, a gate switch circuit and a current comparator, wherein the gate switch circuit adopts the gate switch circuit described in the first aspect above.

[0013] A gating switch circuit provided by an embodiment of the present invention includes a storage unit connection terminal, a read switch tube, a programming switch tube, a read input terminal and a programming input terminal, wherein the number of the read switch tube is one, and the read input terminal is connected to the storage unit connection terminal through the read switch tube, and is used to conduct the storage unit connection terminal and the read input terminal when receiving a read control signal; the circuit controls a read switch tube to conduct the path between the read input terminal and the storage unit connection terminal, thereby achieving the purpose of reducing the on-resistance of the gating switch circuit, increasing the conduction speed, and thus improving the reading speed when performing a read operation on the storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a structural diagram of a metal oxide semiconductor field effect transistor used as a storage unit in a flash chip;

[0015] Figure 2 It is a schematic diagram of the circuit structure when performing a read operation on a storage unit in the prior art;

[0016] Figure 3 It is a circuit structure diagram of a gate switch circuit in the prior art;

[0017] Figure 4 is a structural schematic diagram of a gating switch circuit in Embodiment 1 of the present invention;

[0018] Figure 5 is a structural schematic diagram of another gating switch circuit in Embodiment 1 of the present invention;

[0019] Figure 6 is a structural schematic diagram of a gating switch circuit in Embodiment 2 of the present invention;

[0020] Figure 7 is a structural schematic diagram of another gating switch circuit in the second embodiment of the present invention;

[0021] Figure 8 It is a schematic diagram of the structure of a memory in the third embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0023] Embodiment 1

[0024] Figure 4 This is a schematic diagram of the structure of a gate switch circuit provided in the first embodiment of the present invention. This embodiment can be applied to conduct the path between the drain end of the storage unit and the input end of the current comparator through the gate switch circuit when performing a read operation on the flash memory. Figure 4 The gate switch circuit provided in this embodiment specifically includes the following:

[0025] Storage unit connection terminal COL <n:0>, a read switch tube 110, a programming switch tube 120, a read input terminal SENBL and a programming input terminal PGMBL, the number of the read switch tube 110 is one, and the read input terminal SENBL is connected to the storage unit connection terminal COL through the read switch tube 110 <n:0>Connection, used to receive the read control signal YA_S <n:0>When the storage unit connection terminal COL is turned on <n:0>and read input terminal SENBL;

[0026] Among them, the storage unit connection terminal COL <n:0>Its essence is the port led out from the drain end of the storage unit. For details, please refer to Figure 1 As shown; the essence of the read input terminal SENBL is connected to the input terminal of the current comparator; when the read operation of the storage unit begins, the read control signal YA_S <n:0>The read switch tube 110 is controlled to be turned on, the drain end of the storage cell is turned on with the input end of the current comparator, and then the current flowing through the storage cell is compared with the reference current in the current comparator, and finally the current storage state of the storage cell is obtained, that is, the programming state "0" or the erased state "1".

[0027] What needs to be explained is the read control signal YA_S <n:0>、Storage unit connection terminal COL <n:0>middle" <n:0>", because a flash memory has many storage units according to its own storage capacity, each storage unit is used to store data, so it is inevitable to perform a read operation on each storage unit. In order to improve the efficiency of the read operation, a read selection switch 110 is used between the drain of each storage unit and the input end of the current comparator, so" <n:0>" indicates the read control signal YA_S of the first storage unit <0> Read control signal YA_S to the n+1th storage unit <n>, the first storage unit is connected to the terminal COL <0> To the n+1th storage unit connection terminal COL <n>; Specifically, taking n equal to 1 as an example, see Figure 5 Another structural diagram of a gate switch circuit is shown. Of course, n can also be as small as 0, which means that only one storage unit needs to be read.

[0028] A gating switch circuit provided in this embodiment includes a storage unit connection terminal, a read switch tube, a programming switch tube, a read input terminal and a programming input terminal. The number of the read switch tube is one. The read input terminal is connected to the storage unit connection terminal through the read switch tube, and is used to conduct the storage unit connection terminal and the read input terminal when receiving a read control signal. The circuit controls a read switch tube to conduct the path between the read input terminal and the storage unit connection terminal, thereby reducing the on-resistance of the gating switch circuit when performing a read operation on the storage unit. The reduction in on-resistance shortens the charging time of the drain of the storage unit, thereby increasing the conduction speed, improving the reading speed, and correspondingly reducing the design requirements for the current comparator.

[0029] Embodiment 2

[0030] Figure 6 FIG. 1 is a schematic diagram of a gate switch circuit structure provided in Embodiment 2 of the present invention. This embodiment is further optimized on the basis of Embodiment 1. Figure 6 As shown, the gating switch circuit specifically includes:

[0031] Storage cell connection terminal COL<3:0>, read switch tube 110, programming switch tube 120, read input terminal SENBL and programming input terminal PGMBL, the number of read switch tube 110 is one, the read input terminal SENBL is connected to the storage cell connection terminal COL<3:0> through the read switch tube 110, and is used to conduct the storage cell connection terminal COL<3:0> and the read input terminal SENBL when receiving the read control signal YA_S<3:0>;

[0032] Furthermore, the gate switch circuit further includes a discharge switch tube hn1<3:0>, and the storage unit connection terminal COL<3:0> is grounded through the discharge switch tube hn1<3:0> for discharging under the control of a discharge signal.

[0033] Exemplarily, the switch tube is a MOS tube, and the number of the programming switch tubes 120 is two, such as Figure 6 The read switch tube hn2<3:0>, the programming switch tube hn3<3:0> and hn4<3:0>; the programming input terminal PGMBL is connected to the storage unit connection terminal COL<3:0> through two programming switch tubes connected in series, namely hn3<3:0> and hn4<3:0>, and is used to turn on the storage unit connection terminal COL<3:0> and the programming input terminal PGMBL when receiving two programming control signals YA_P<3:0> and YB_P<3:0> respectively.

[0034] See also Figure 6 As shown, when a memory cell is read, the memory cell connection terminal COL<3:0> and the read input terminal SENBL can be turned on by controlling the read switch tube hn2<3:0> to be turned on by the read control signal YA_S<3:0>. Compared with the prior art, the on-resistance is reduced, and the charging time of the memory cell connection terminal COL<3:0> is correspondingly shortened, thereby increasing the on-speed and thus improving the reading speed.

[0035] It should be noted that the same as in Example 1 regarding " <n:0>" is similar to the explanation of ", in this embodiment, n is equal to 3, and the discharge switch tube hn1 <0> ,hn1 <1> ,hn1 <2> ,hn1 <3> The read switch hn2<3:0>, the programming switch hn3<3:0> and hn4<3:0> also follow the same principle. For details, see Figure 7 Another schematic diagram of the structure of a gate switch circuit is shown in FIG. Figure 7 Take n equals 1 as an example.

[0036] The present embodiment provides a gating switch circuit, which is based on the first embodiment and optimizes the switch tube to a MOS tube, thereby facilitating flexible and accurate control of each switch tube, and better realizing the reduction of the on-resistance of the gating switch circuit when performing a read operation on a storage unit. The reduction of the on-resistance shortens the charging time of the drain of the storage unit, thereby increasing the conduction speed, improving the reading speed, and at the same time, the design requirements for the current comparator are also reduced accordingly.

[0037] Embodiment 3

[0038] Figure 8 A structural schematic diagram of a memory provided for implementation three of the present invention specifically includes: a storage unit 300, a gating switch circuit 310 and a current comparator 320, wherein the gating switch circuit 310 adopts the gating switch circuit provided by any of the above embodiments, and the gating switch circuit provided by any of the above embodiments enables the memory to have a faster reading speed.

[0039] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims. < / n> < / n>

Claims

1. A gate switch circuit, comprising a storage unit connection terminal, a read switch tube, a programming switch tube, a read input terminal and a programming input terminal, characterized in that: The number of the read switch tube is one, and the read input end is connected to the storage unit connection end through the read switch tube, and is used to conduct the storage unit connection end and the read input end when receiving a read control signal; The number of the programming switch tubes is two, and the programming input terminal is connected to the storage unit connection terminal through two programming switch tubes connected in series, so as to conduct the storage unit connection terminal and the programming input terminal when two programming control signals are received respectively.

2. The circuit according to claim 1, characterized in that Also includes: A discharge switch tube, through which the storage unit connection end is grounded, is used for discharging under the control of a discharge signal.

3. The circuit according to any one of claims 1-2, characterized in that: The switch tube is a MOS tube.

4. A memory comprising a storage unit, a gate switch circuit and a current comparator, characterized in that: The gating switch circuit adopts the gating switch circuit described in any one of claims 1-3.

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