Multichannel ADC system synchronous sampling device and method

A synchronous sampling and multi-channel technology, which is applied in the field of multi-channel ADC, can solve the problem that single chips cannot be aligned with each other, and achieve the effect of data synchronization

Active Publication Date: 2019-10-18
成都铭科思微电子技术有限责任公司
View PDF8 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] None of the existing multi-channel alignment schemes can automatically align each channel in a single chip

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Multichannel ADC system synchronous sampling device and method
  • Multichannel ADC system synchronous sampling device and method
  • Multichannel ADC system synchronous sampling device and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0046] The present invention designs a device for synchronous sampling of a multi-channel ADC system, which can realize data alignment of multi-channels in the chip, such as figure 1 As shown, the following configuration structure is particularly adopted: a TOKEN generation unit, a TOKEN distribution unit, an ADC unit, an ADC back-end logic unit and RCOUT are provided,

[0047] The TOKEN generation unit generates a cycle factor (TOKEN) based on the sampling clock (CLK);

[0048] The TOKEN allocation unit is used to allocate the cycle factor (TOKEN) to the ADC unit and the ADC back-end logic unit;

[0049] The ADC unit is used to sample the analog input of the corresponding channel and quantize it into a multi-bit digital signal;

[0050] The ADC back-end logic unit is used to generate aligned data clocks and realize the data interleaving output function of the small channels inside the large channel;

[0051] RCOUT is used to transmit the cycle factor to the downstream ADC c...

Embodiment 2

[0056] This embodiment is further optimized on the basis of the above-mentioned embodiments, and the similarities with the technical solutions of the foregoing embodiments will not be repeated here, such as figure 1 As shown, further in order to better realize the synchronous sampling device of the multi-channel ADC system of the present invention, the following setting method is adopted in particular: the TOKEN generation unit works in Master mode or Slave mode.

Embodiment 3

[0058] This embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the similarities with the technical solutions of the foregoing embodiments will not be repeated here, such as figure 1 As shown, further in order to better realize the device for synchronous sampling of the multi-channel ADC system described in the present invention, the following setting method is adopted in particular: In the Master mode, the TOKEN generation unit performs a cycle based on the sampling clock (CLK) Counting, the cycle period is the number N of sub-channels (ADC sub-channels) in the large channel (large-channel ADC), and the counting method uses Gray code; it is used to generate a series of cyclic pulses, and its duty ratio is 1 / N.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a multichannel ADC system synchronous sampling device and method, and the device is provided with a TOKEN generation unit, a TOKEN distribution unit, an ADC unit, an ADC rear-end logic unit, an RCOUT, and a TOKEN generation unit, and a circulation factor TOKEN is generated based on a sampling clock CLK. The TOKEN distribution unit is used for distributing the circulation factor TOKEN to the ADC unit and the ADC rear-end logic unit; the ADC unit is used for sampling analog input of a corresponding channel and quantizing the analog input into a multi-bit digital signal, wherein the ADC back-end logic unit is used for generating aligned data clocks and realizing a data interleaving output function of a small channel in a large channel, the RCOUT is used for transmitting a cycle factor to a downstream ADC chip, the period of the RCOUT is equal to the period of the cycle factor, and the duty ratio of the RCOUT is 50%; the device can realize on-chip multi-channel dataalignment, and the method can also realize automatic alignment of data output DOUT0 and DOUT1 and clock output DCLK0 and DCLK1 after the device (chip) is powered on without software re-interference.

Description

technical field [0001] The invention relates to the technical field of multi-channel ADC, in particular to a device and method for synchronous sampling of a multi-channel ADC system. Background technique [0002] For the parallel LVDS output and multi-channel ADC system, if the phases of the data clock DCLK and data output DOUT of each channel are aligned, the design of peripheral and downstream data collection circuits will be simplified. [0003] None of the existing multi-channel alignment schemes can automatically align each channel in a single chip. The alignment of each channel between multiple chips either requires high requirements for the routing and matching of synchronous signals outside the chip, or requires separate corrections for the data output DOUT and the data clock DCLK. Contents of the invention [0004] The purpose of the present invention is to provide a device and method for synchronous sampling of a multi-channel ADC system. The device can realize ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): H03M1/12
CPCH03M1/1255H03M1/1245
Inventor 王现喜王建东徐振涛
Owner 成都铭科思微电子技术有限责任公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap