A Cell Matrix Merging Method in Physical Verification of Flat Panel Display Layout

A cell matrix, physical verification technology, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as non-coverage, low inspection efficiency, and great impact, and achieve improved execution efficiency and result level optimization. , reduce the effect of overlapping areas
CN111008513BActive Publication Date: 2022-07-15北京华大九天科技股份有限公司
8 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
北京华大九天科技股份有限公司
Publication Date
2022-07-15

Smart Images

  • Figure 1
    Figure 1
  • Figure 2
    Figure 2
  • Figure 3
    Figure 3
Patent Text Reader

Abstract

A cell matrix merging method in physical verification of flat panel display layout, comprising the following steps: 1) performing topological sorting of cells, sorting all cells from top to bottom according to a hierarchical reference relationship, and forming a linked list; 2) specifying a current cell, and performing element sorting Recognition of the matrix; 3) The calculation unit refers to the overlapping area, and divides the current unit into multiple blocks according to the overlapping area; 4) In each overlapping area block, merge the overlapping matrices in sequence to form a new unit , form a matrix of new units; 5) Insert a new unit linked list after the current unit, maintaining the topological order of the entire linked list. The unit matrix merging method in the physical verification of the layout of the flat panel display of the present invention reduces the overlapping area between the unit references to the greatest extent, avoids the occurrence of the worst situation of the layout layout, significantly improves the execution efficiency, and significantly optimizes the result level. And the follow-up operations are very positive.
Need to check novelty before this filing date? Find Prior Art

Description

technical field

[0001] The invention relates to the technical field of semiconductor integrated circuit design, in particular to a physical layout verification tool for flat panel display circuits in semiconductor integrated circuit design, and in particular to a cell matrix merging method in physical verification of flat panel display layout. Background technique

[0002] Flat Panel Display (FPD) devices, including mobile phone screens, computer monitors, TV screens, etc., whose main area is a display pixel array (Pixel Array) in the center of the device superimposed on a touch matrix (TouchArray), which consists of a large number of repetitive circuits The cells are arranged in rows and columns, and the control circuit is usually around the main area.

[0003] To ensure the successful manufacture of flat panel display devices, the flat panel display circuits are also physically verified. Similar to the physical verification of the integrated circuit layout, the physical v...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More