Fourier transform system and method based on neural network hardware system

Abstract

The present invention discloses a Fourier transform system based on a neural network hardware system, and belongs to the field of neural network chip technology. It includes: arranging input data points into a set two-dimensional length. According to the input data points and the real part equation of the rotation factor, respectively obtain the corresponding first real matrix and second real matrix. Arrange the input data matrix into a two-dimensional first matrix corresponding to the number of rows and columns of the computing unit array. Obtain a fourth matrix according to the two-dimensional third matrix, the second real matrix and the second imaginary matrix. The fourth matrix is ​​obtained by operating the first fully connected layer computing unit with the first real matrix and the first imaginary matrix to obtain a fifth matrix. According to the fifth matrix, obtain output Fourier real data and output Fourier imaginary data. The present invention solves the problem that the prior art artificial intelligence chip has low performance and large area when calculating Fourier transform in application scenarios such as speech recognition and speech synthesis.

Description

Technical Field

[0001] The present invention belongs to the technical field of neural network chips, and in particular to a Fourier transform system and method implemented by a neural network hardware system. Background Art

[0002] Fourier transform is an algorithm commonly used in speech and DSP (digital signal processing). At present, most artificial intelligence chips use integrated ASIC (application-specific integrated circuit) in hardware, and most use FFT (fast Fourier transform) to calculate Fourier transform in algorithm. Taking the calculation point number of 1024 points as an example, if the above method is used, it takes about 20,000 clock cycles to calculate 1024 points. The performance is difficult to meet the requirements, and the area and power consumption are also unacceptable. How to calculate the Fourier transform in artificial intelligence chips in application scenarios such as speech recognition and speech synthesis so that its performance is high and the area is small has become a technical difficulty. Summary of the invention

[0003] The purpose of the present invention is to provide a Fourier transform system and method based on a neural network hardware system to solve the problems of low performance and large area when artificial intelligence chips in the prior art calculate Fourier transform in application scenarios such as speech recognition and speech synthesis.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] A Fourier transform system based on a neural network hardware system, comprising:

[0006] The neural network hardware system includes a first fully connected layer computing unit and a second fully connected layer computing unit. The neural network hardware system has a plurality of computing unit arrays. The computing unit array is a two-dimensional array. The number of bits in the two-dimensional array is equal to the number of rows multiplied by the number of columns. The Fourier transform method implemented by the neural network hardware system includes:

[0007] Step S101, arranging multiple input data points into an input data matrix of a set two-dimensional length. The number of the multiple input data points is an integer multiple of the number of bits of the two-dimensional array. The two-dimensional length corresponds to the number of rows and columns of the calculation unit array.

[0008] Step S102: The real part equation and the imaginary part equation of the rotation factor are obtained by combining the rotation factor formula and the Euler formula.

[0009] Step S103, according to the plurality of input data points and the real part equation of the rotation factor, respectively obtain the first real part matrix and the second real part matrix corresponding thereto. According to the plurality of input data points and the imaginary part equation of the rotation factor, respectively obtain the first imaginary part matrix and the second imaginary part matrix corresponding thereto.

[0010] The first real matrix and the first imaginary matrix are arranged according to the first digit. The first digit is the number of rows or columns. The second real matrix and the second imaginary matrix are arranged according to the second digit. The second digit is the number of two-dimensional array digits.

[0011] Step S104, arranging the input data matrix into a two-dimensional first matrix corresponding to the number of rows and columns of the calculation unit array. Arranging the first real matrix and the first imaginary matrix into two-dimensional second matrices corresponding to the number of rows and columns of the calculation unit array.

[0012] Step S105, swapping the order of rows and columns of the two-dimensional first matrix and the two-dimensional second matrix.

[0013] Step S106, multiplying the two-dimensional first matrix by the two-dimensional second matrix through the first fully connected layer computing unit to obtain a two-dimensional third matrix.

[0014] Step S107, obtaining a fourth matrix according to the two-dimensional third matrix, the second real matrix and the second imaginary matrix.

[0015] Step S108, using the first fully connected layer computing unit to perform operations on the fourth matrix, the first real matrix, and the first imaginary matrix to obtain a fifth matrix.

[0016] Step S109, obtaining output Fourier real part data and output Fourier imaginary part data according to the fifth matrix.

[0017] On the basis of the above technical solution, the present invention can also be improved as follows:

[0018] Furthermore, the number of the plurality of input data points is 1024 input data points, the input data matrix is ​​a 1*1024 matrix, and the computing unit array is a 32*32 two-dimensional array.

[0019] Further, the first real matrix and the first imaginary matrix are 1*1024 matrices. The first number of bits is 32. The second real matrix and the second imaginary matrix are 1*1024 matrices. The second number of bits is 1024.

[0020] Furthermore, the two-dimensional first matrix is ​​a 32*32 matrix. The two-dimensional second matrix is ​​a 32*32 matrix.

[0021] Furthermore, the two-dimensional fourth matrix is ​​a 32*32 matrix. The two-dimensional fifth matrix is ​​a 32*32 matrix.

[0022] A neural network hardware system capable of implementing Fourier transform, the neural network hardware system comprising a first fully connected layer computing unit and a second fully connected layer computing unit. The neural network hardware system has a plurality of computing unit arrays. The computing unit array is a two-dimensional array. The number of bits in the two-dimensional array is equal to the number of rows multiplied by the number of columns. The neural network hardware system capable of implementing Fourier transform is configured as follows:

[0023] Arrange multiple input data points into an input data matrix of a set two-dimensional length. The number of multiple input data points is an integer multiple of the number of bits in the two-dimensional array. The two-dimensional length corresponds to the number of rows and columns of the calculation unit array.

[0024] The rotation factor formula and Euler formula are combined to obtain the real part equation and the imaginary part equation of the rotation factor.

[0025] According to the plurality of input data points and the real part equation of the rotation factor, the first real part matrix and the second real part matrix corresponding thereto are obtained respectively. According to the plurality of input data points and the imaginary part equation of the rotation factor, the first imaginary part matrix and the second imaginary part matrix corresponding thereto are obtained respectively.

[0026] The first real matrix and the first imaginary matrix are arranged according to the first digit. The first digit is the number of rows or columns. The second real matrix and the second imaginary matrix are arranged according to the second digit. The second digit is the number of two-dimensional array digits.

[0027] The input data matrix is ​​arranged into a two-dimensional first matrix corresponding to the number of rows and columns of the calculation unit array. The first real matrix and the first imaginary matrix are arranged into two-dimensional second matrices corresponding to the number of rows and columns of the calculation unit array.

[0028] The order of rows and columns of the two-dimensional first matrix and the two-dimensional second matrix is ​​swapped.

[0029] The two-dimensional first matrix is ​​multiplied by the two-dimensional second matrix through the first fully connected layer computing unit to obtain the two-dimensional third matrix.

[0030] A fourth matrix is ​​obtained according to the two-dimensional third matrix, the second real matrix, and the second imaginary matrix.

[0031] The fifth matrix is ​​obtained by performing operations on the fourth matrix, the first real matrix, and the first imaginary matrix through the first fully connected layer computing unit.

[0032] Output Fourier real part data and output Fourier imaginary part data are obtained according to the fifth matrix.

[0033] Furthermore, the number of the plurality of input data points is 1024 input data points, the input data matrix is ​​a 1*1024 matrix, and the computing unit array is a 32*32 two-dimensional array.

[0034] Further, the first real matrix and the first imaginary matrix are 1*1024 matrices. The first number of bits is 32. The second real matrix and the second imaginary matrix are 1*1024 matrices. The second number of bits is 1024.

[0035] Furthermore, the two-dimensional first matrix is ​​a 32*32 matrix. The two-dimensional second matrix is ​​a 32*32 matrix.

[0036] Furthermore, the two-dimensional fourth matrix is ​​a 32*32 matrix. The two-dimensional fifth matrix is ​​a 32*32 matrix.

[0037] The present invention has the following advantages:

[0038] 1. Low hardware consumption: Using neural networks for Fourier transform, the existing neural network hardware layer can be flexibly used in hardware implementation, without the need to integrate ASIC-FFT IP again, which can greatly reduce the chip area.

[0039] 2. Efficient calculation: Compared with the approximately 20,000 clock cycles required for ASIC calculation, the present invention only uses 192 32*32 fully connected layers and 8 32*32 Eltwise layers to roughly complete a 1024-point Fourier transform. In scenarios such as speech recognition, the efficiency of speech recognition can be greatly improved.

[0040] 3. Efficient storage: The present invention requires only 2*32*32 rotation factors, compared with 1024*1024 of DFT, and the storage space required by the present invention is only 1 / 512 of that of DFT.

[0041] 4. High quantization accuracy: The traditional radix 2 FFT extracted by time / frequency has 10 calculation layers, and the multiplication calculation of each layer will cause precision loss. The calculation layer of the present invention is only 3 layers (2 fully connected layers and 1 eltwise layer), which greatly reduces the precision loss.

[0042] 5. Hardware-friendly: From the perspective of hardware design, it is currently difficult to design a high-dimensional fully connected layer and Eltwise layer similar to 1024*1024 for Fourier transform in neural network chips, while the hardware design of low-dimensional fully connected layers and Eltwise layers is more popular. This solves the problem that it takes a long time to find an accurate phase spectrum in the existing technology, resulting in phase mismatch. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 It is a flow chart of the Fourier transform method of the present invention.

[0045] Figure 2 It is a schematic diagram of the W32 arrangement of the present invention.

[0046] Figure 3 It is a schematic diagram of the W1024 arrangement of the present invention.

[0047] Figure 4 This is a calculation flow chart of the Fourier transform system of the present invention. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] like Figure 1-4 As shown, an embodiment of the present invention provides a Fourier transform system implemented by a neural network hardware system.

[0050] Compared with the approximately 20,000 clock cycles required for ASIC calculation, the Fourier transform system of the present invention can roughly complete a 1024-point Fourier transform using only 192 32*32 fully connected layers and 8 32*32 Eltwise layers. In scenarios such as speech recognition, the efficiency of speech recognition can be greatly improved.

[0051] The neural network hardware system includes a first fully connected layer computing unit and a second fully connected layer computing unit. The neural network hardware system has a plurality of computing unit arrays. The computing unit array is a two-dimensional array. The number of bits in the two-dimensional array is equal to the number of rows multiplied by the number of columns.

[0052] The number of calculation layers of the traditional radix-2 FFT extracted by time / frequency is 10, and the multiplication calculation of each layer will cause precision loss. The number of calculation layers of the present invention is only 3 (2 fully connected layers and 1 eltwise layer), which greatly reduces the precision loss.

[0053] Fourier transform methods implemented by neural network hardware systems include:

[0054] Step S101, arranging a plurality of input data points into an input data matrix of a set two-dimensional length.

[0055] In this step, the plurality of input data points are arranged into an input data matrix of a set two-dimensional length. The number of the plurality of input data points is an integer multiple of the number of bits of the two-dimensional array. The two-dimensional length corresponds to the number of rows and columns of the calculation unit array.

[0056] The 1024 input points are recorded as {data_0, data_1, data_2, ..., data_1023}, which is actually a 1024×1 matrix.

[0057] Step S102: The real part equation and the imaginary part equation of the rotation factor are obtained by combining the rotation factor formula and the Euler formula.

[0058] In this step, the rotation factor formula and the Euler formula are combined to obtain the real part equation and the imaginary part equation of the rotation factor.

[0059] According to the definition of the rotation factor and Euler's formula:

[0060]

[0061] The real part of the rotation factor is W N_Real (i) = cos(2π×i / N), where i = 0, 1, 2, ..., N. The imaginary part of the rotation factor is W N_IM (i)=sin(2π×i / N), where i=0, 1, 2,...,N.

[0062] The Fourier transform system of the present invention requires only 2*32*32 rotation factors, compared with 1024*1024 of DFT, and the storage space required by the Fourier transform system of the present invention is only 1 / 512 of that of DFT.

[0063] Step S103, according to the multiple input data points and the real part equations of the rotation factors, respectively obtain the corresponding first real part matrix and second real part matrix.

[0064] In this step, according to the multiple input data points and the real part equation of the rotation factor, the corresponding first real part matrix and the second real part matrix are obtained respectively. According to the multiple input data points and the imaginary part equation of the rotation factor, the corresponding first imaginary part matrix and the second imaginary part matrix are obtained respectively.

[0065] The first real matrix and the first imaginary matrix are arranged according to the first digit. The first digit is the number of rows or columns. The second real matrix and the second imaginary matrix are arranged according to the second digit. The second digit is the number of two-dimensional array digits.

[0066] According to Formula 1, the real part matrix of the rotation factor matrix W32 is constructed as W32_R={W32_R_O, W32_R_1, ..., W32_R_1023}, where W32_R_i=cos(2*pi*i / 32), i=32*p+q, i=0, 1, 2, ..., 1023. p, q=0, 1, 2, ..., 31. W32_R is actually a 1*1024 matrix.

[0067] According to Formula 1, the imaginary matrix of the rotation factor matrix W1024 is constructed as W1024_I={W1024_I_0, W1024_I_1, ..., W1024_I_1023}, W1024_i=sin(2*pi*i / 1024), i=32*p+q, i=0, 1, 2, ..., 1023. W1024_I is actually a 1×1024 matrix.

[0068] Step S104, arranging the input data matrix into a two-dimensional first matrix corresponding to the number of rows and columns of the calculation unit array.

[0069] In this step, the input data matrix is ​​arranged into a two-dimensional first matrix corresponding to the number of rows and columns of the calculation unit array. The first real matrix and the first imaginary matrix are arranged into two-dimensional second matrices corresponding to the number of rows and columns of the calculation unit array.

[0070] ① Rearrange the input 1024-point data into a 32*32 matrix, recorded as data_in matrix.

[0071] ② Similarly, reorder W32_R, W32_I, W1024_R, and W1024_I into a 32*32 matrix.

[0072] Among them, p is regarded as the number of rows, q is regarded as the number of columns, and p,q=0,1,2,...,31.

[0073] Step S105, swapping the order of rows and columns of the two-dimensional first matrix and the two-dimensional second matrix.

[0074] In this step, the order of rows and columns of the two-dimensional first matrix and the two-dimensional second matrix is ​​swapped.

[0075] Reading elements of the data_in matrix column by column is actually a transposition operation, and the result is recorded as the data_in_t matrix.

[0076]

[0077] After transposition

[0078]

[0079] Step S106, multiplying the two-dimensional first matrix by the two-dimensional second matrix through the first fully connected layer computing unit to obtain a two-dimensional third matrix.

[0080] In this step, the two-dimensional first matrix is ​​multiplied by the two-dimensional second matrix through the first fully connected layer computing unit to obtain the two-dimensional third matrix.

[0081] The full connection operation is actually a vector-matrix multiplication. If the vector is upgraded to a matrix, the multiplication of two matrices can be regarded as multiple sets of full connection operations. Take the multiplication of a 32×32 matrix by a 32×32 matrix as an example.

[0082]

[0083] ① Perform a full connection operation on each row of data_in_t(32*32) and W32_R(32*32), and the result is recorded as data_out_1_R(32*32). There are 32 32*32 full connection operations in total.

[0084] ② Perform a full connection operation on each row of data_in_t(32*32) and W32_I(32*32), and the result is recorded as data_out_1_I(32*32). There are 32 32*32 full connection operations in total.

[0085] There are a total of 64 32*32 full-connection operations.

[0086] Step S107, obtaining a fourth matrix according to the two-dimensional third matrix, the second real matrix and the second imaginary matrix.

[0087] In this step, a fourth matrix is ​​obtained according to the two-dimensional third matrix, the second real matrix and the second imaginary matrix.

[0088] Step S108, obtaining a fifth matrix by performing an operation on the fourth matrix, the first real matrix, and the first imaginary matrix through the first fully connected layer computing unit.

[0089] In this step, the fifth matrix is ​​obtained by performing operations on the fourth matrix, the first real matrix, and the first imaginary matrix through the first fully connected layer computing unit.

[0090] Step S109, obtaining output Fourier real part data and output Fourier imaginary part data according to the fifth matrix.

[0091] In this step, output Fourier real part data and output Fourier imaginary part data are obtained according to the fifth matrix.

[0092] The number of the multiple input data points is 1024. The input data matrix is ​​a 1*1024 matrix. The calculation unit array is a 32*32 two-dimensional array.

[0093] Eltwise operation is actually an operation on the corresponding elements of two matrices. Take two 2×2 matrices as an example.

[0094] Eltwise multiplication:

[0095]

[0096] Eltwise addition:

[0097]

[0098] ① Multiply the corresponding elements of data_out_1_R(32*32) and W1024_R(32*32) in the Eltwise layer, and the result is recorded as data_out_2_R1(32*32).

[0099] ② Multiply the corresponding elements of data_out_1_I(32*32) and W1024_I(32*32) in the Eltwise layer, and the result is recorded as data_out_2_R2(32*32).

[0100] ③ Multiply the corresponding elements of data_out_1_R(32*32) and W1024_I(32*32) in the Eltwise layer, and the result is recorded as data_out_2_I1(32*32).

[0101] ④ Multiply the corresponding elements of data_out_1_I(32*32) and W1024_R(32*32) in the Eltwise layer, and the result is recorded as data_out_2_I2(32*32).

[0102] ⑤Add the corresponding elements of data_out_2_R1(32*32) and -data_out_2_R2(32*32) in the Eltwise layer, and the result is recorded as data_out_2_R(32*32).

[0103] ⑥Add the corresponding elements of data_out_2_I1(32*32) and data_out_2_I2(32*32) in the Eltwise layer, and the result is recorded as data_out_2_I(32*32).

[0104] There are a total of 4 32*32 Eltwise layer multiplication operations and 2 32*32 Eltwise layer addition operations.

[0105] 6.Fully-Connected

[0106] ① Perform a full connection operation on each row of data_out_2_R(32*32) and W32_R(32*32), and the result is recorded as data_out_3_R1(32*32). There are 32 32*32 full connection operations in total.

[0107] ② Perform a full connection operation on each row of data_out_2_I(32*32) and W32_I(32*32), and the result is recorded as data_out_3_R2(32*32). There are 32 32*32 full connection operations in total.

[0108] ③ Perform a full connection operation on each row of data_out_2_R(32*32) and W32_I(32*32), and the result is recorded as data_out_3_I1(32*32). There are 32 32*32 full connection operations in total.

[0109] ④ Perform a full connection operation on each row of data_out_2_I(32*32) and W32_R(32*32), and the result is recorded as data_out_3_I2(32*32). There are 32 32*32 full connection operations in total.

[0110] A total of 128 32*32 full-connection operations

[0111] Eltwise (corresponding element operation)

[0112] ① Add the corresponding elements of data_out_3_R1(32*32) and -data_out_3_R2(32*32) in the Eltwise layer, and the result is recorded as data_out_R(32*32).

[0113] ②Add the corresponding elements of data_out_3_I1(32*32) and data_out_3_I2(32*32) in the Eltwise layer, and the result is recorded as data_out_I(32*32).

[0114] There are a total of 2 32*32 Eltwise layer addition operations.

[0115] The first real matrix and the first imaginary matrix are 1*1024 matrices. The first bit is 32 bits. The second real matrix and the second imaginary matrix are 1*1024 matrices. The second bit is 1024 bits.

[0116] The two-dimensional first matrix is ​​a 32*32 matrix. The two-dimensional second matrix is ​​a 32*32 matrix.

[0117] The two-dimensional fourth matrix is ​​a 32*32 matrix. The two-dimensional fifth matrix is ​​a 32*32 matrix.

[0118] A neural network hardware system capable of implementing Fourier transform, the neural network hardware system comprising a first fully connected layer computing unit and a second fully connected layer computing unit. The neural network hardware system has a plurality of computing unit arrays. The computing unit array is a two-dimensional array. The number of bits in the two-dimensional array is equal to the number of rows multiplied by the number of columns. The neural network hardware system capable of implementing Fourier transform is configured as follows:

[0119] Arrange multiple input data points into an input data matrix of a set two-dimensional length. The number of multiple input data points is an integer multiple of the number of bits in the two-dimensional array. The two-dimensional length corresponds to the number of rows and columns of the calculation unit array.

[0120] The rotation factor formula and Euler formula are combined to obtain the real part equation and the imaginary part equation of the rotation factor.

[0121] According to the plurality of input data points and the real part equation of the rotation factor, the first real part matrix and the second real part matrix corresponding thereto are obtained respectively. According to the plurality of input data points and the imaginary part equation of the rotation factor, the first imaginary part matrix and the second imaginary part matrix corresponding thereto are obtained respectively.

[0122] The first real matrix and the first imaginary matrix are arranged according to the first digit. The first digit is the number of rows or columns. The second real matrix and the second imaginary matrix are arranged according to the second digit. The second digit is the number of two-dimensional array digits.

[0123] The input data matrix is ​​arranged into a two-dimensional first matrix corresponding to the number of rows and columns of the calculation unit array. The first real matrix and the first imaginary matrix are arranged into two-dimensional second matrices corresponding to the number of rows and columns of the calculation unit array.

[0124] The order of rows and columns of the two-dimensional first matrix and the two-dimensional second matrix is ​​swapped.

[0125] The two-dimensional first matrix is ​​multiplied by the two-dimensional second matrix through the first fully connected layer computing unit to obtain the two-dimensional third matrix.

[0126] A fourth matrix is ​​obtained according to the two-dimensional third matrix, the second real matrix, and the second imaginary matrix.

[0127] The fifth matrix is ​​obtained by performing operations on the fourth matrix, the first real matrix, and the first imaginary matrix through the first fully connected layer computing unit.

[0128] Output Fourier real part data and output Fourier imaginary part data are obtained according to the fifth matrix.

[0129] The number of the multiple input data points is 1024. The input data matrix is ​​a 1*1024 matrix. The calculation unit array is a 32*32 two-dimensional array.

[0130] The first real matrix and the first imaginary matrix are 1*1024 matrices. The first bit is 32 bits. The second real matrix and the second imaginary matrix are 1*1024 matrices. The second bit is 1024 bits.

[0131] The two-dimensional first matrix is ​​a 32*32 matrix. The two-dimensional second matrix is ​​a 32*32 matrix.

[0132] The two-dimensional fourth matrix is ​​a 32*32 matrix. The two-dimensional fifth matrix is ​​a 32*32 matrix.

[0133] From the perspective of hardware design, it is currently difficult to design high-dimensional fully connected layers and Eltwise layers similar to 1024*1024 for Fourier transform in neural network chips, while the hardware design of low-dimensional fully connected layers and Eltwise layers is more popular.

[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the above embodiments, a person skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A Fourier transform method implemented by a neural network hardware system, characterized in that: The neural network hardware system includes a first fully connected layer computing unit and a second fully connected layer computing unit; the neural network hardware system has a plurality of computing unit arrays; The computing unit array is a two-dimensional array; The number of bits in a two-dimensional array is equal to the number of rows multiplied by the number of columns; The Fourier transform method implemented by the neural network hardware system includes: Step S101, arranging a plurality of input data points into an input data matrix of a set two-dimensional length; the number of the plurality of input data points is an integer multiple of the number of bits of the two-dimensional array; the two-dimensional length corresponds to the number of rows and columns of the computing unit array; Step S102, combining the rotation factor formula and the Euler formula to obtain the real part equation and the imaginary part equation of the rotation factor; according to the definition of the rotation factor and the Euler formula: The real part of the rotation factor is W N_Real (i) = cos(2π×i / N), where i = 0, 1, 2, ..., N, and the imaginary part of the rotation factor is W N_IM (i)=sin(2π×i / N), where i=0, 1, 2,...,N; Step S103, according to multiple input data points and the real part equation of the rotation factor, respectively obtain the first real matrix and the second real matrix corresponding thereto; according to multiple input data points and the imaginary part equation of the rotation factor, respectively obtain the first imaginary matrix and the second imaginary matrix corresponding thereto; the first real matrix and the first imaginary matrix are arranged according to the first digit; the first digit is the number of rows or columns; the second real matrix and the second imaginary matrix are arranged according to the second digit; the second digit is the number of two-dimensional array digits; according to formula 1, the real matrix of the rotation factor matrix W32 is constructed as W32_R={W32_R_0, W32_R_1, ..., W32_R_1023}, wherein W32_R_i=cos(2*pi*i / 32), i=32*p+q, i=0, 1, 2, ..., 1023, p, q=0, 1, 2, ..., 31, W32_R is actually a 1*1024 matrix; According to formula 1, the imaginary matrix of the rotation factor matrix W1024 is constructed as W1024_I={W1024_I_0, W1024_I_1, ..., W1024_I_1023}, W1024_i=sin(2*pi*i / 1024), i=32*p+q, i=0, 1, 2, ...., 1023, W1024_I is actually a 1×1024 matrix; Step S104, arranging the input data matrix into a two-dimensional first matrix corresponding to the number of rows and columns of the computing unit array; arranging the first real matrix and the first imaginary matrix into two-dimensional second matrices corresponding to the number of rows and columns of the computing unit array; ① reordering the input 1024 point data into a 32*32 matrix, recorded as data_in matrix; ② Similarly, reorder W32_R, W32_I, W1024_R, and W1024_I into a 32*32 matrix; Among them, p is regarded as the number of rows, q is regarded as the number of columns, p,q=0,1,2,...,31; Step S105, swapping the order of rows and columns of the two-dimensional first matrix and the two-dimensional second matrix; reading elements of the data_in matrix by column, which is actually a transposition operation, and the result is recorded as the data_in_t matrix; After transposition Step S106, multiplying the two-dimensional first matrix by the two-dimensional second matrix through the first fully connected layer computing unit to obtain a two-dimensional third matrix; Step S107, obtaining a fourth matrix by performing corresponding element operations of an Eltwise module according to the two-dimensional third matrix, the second real matrix and the second imaginary matrix; Step S108, performing an operation on the fourth matrix, the first real matrix, and the first imaginary matrix through the second fully connected layer computing unit to obtain a fifth matrix; Step S109, obtaining output Fourier real part data and output Fourier imaginary part data through corresponding element operations of the Eltwise module according to the fifth matrix.

2. The Fourier transform method according to claim 1, characterized in that: The number of the multiple input data points is 1024 input data points; the input data matrix is ​​a 1*1024 matrix; and the computing unit array is a 32*32 two-dimensional array.

3. The Fourier transform method according to claim 1 or 2, characterized in that: The first real matrix and the first imaginary matrix are 1*1024 matrices; the first bit number is 32 bits; the second real matrix and the second imaginary matrix are 1*1024 matrices; the second bit number is 1024 bits.

4. The Fourier transform method according to claim 3, characterized in that: The two-dimensional first matrix is ​​a 32*32 matrix; the two-dimensional second matrix is ​​a 32*32 matrix.

5. The Fourier transform method according to claim 3, characterized in that: The two-dimensional fourth matrix is ​​a 32*32 matrix; the two-dimensional fifth matrix is ​​a 32*32 matrix.

6. A neural network hardware system capable of implementing Fourier transform, characterized in that: The neural network hardware system comprises a first fully connected layer computing unit and a second fully connected layer computing unit; the neural network hardware system has a plurality of computing unit arrays; the computing unit array is a two-dimensional array; the number of bits in the two-dimensional array is equal to the number of rows multiplied by the number of columns; the neural network hardware system capable of implementing Fourier transform is configured as follows: Arrange multiple input data points into an input data matrix of a set two-dimensional length; the number of the multiple input data points is an integer multiple of the number of bits of the two-dimensional array; the two-dimensional length corresponds to the number of rows and columns of the computing unit array; Combine the rotation factor formula and Euler formula to obtain the real part equation and imaginary part equation of the rotation factor; According to the definition of the rotation factor and Euler's formula: The real part of the rotation factor is W N_Real (i) = cos(2π×i / N), where i = 0, 1, 2, ..., N, and the imaginary part of the rotation factor is W N_IM (i)=sin(2π×i / N), where i=0, 1, 2,...,N; According to the plurality of input data points and the real part equation of the rotation factor, respectively obtain the first real part matrix and the second real part matrix corresponding thereto; according to the plurality of input data points and the imaginary part equation of the rotation factor, respectively obtain the first imaginary part matrix and the second imaginary part matrix corresponding thereto; The first real matrix and the first imaginary matrix are arranged according to a first digit; the first digit is the number of rows or columns; The second real matrix and the second imaginary matrix are arranged according to a second number of bits; the second number of bits is the number of bits of the two-dimensional array; According to formula 1, the real part matrix of the rotation factor matrix W32 is constructed as W32_R={W32_R_0, W32_R_1, ..., W32_R_1023}, where W32_R_i=cos(2*pi*i / 32), i=32*p+q, i=0,1,2,....,1023, p, q=0,1,2,...,31, and W32_R is actually a 1*1024 matrix; According to formula 1, the imaginary matrix of the rotation factor matrix W1024 is constructed as W1024_I={W1024_I_0, W1024_I_1, ..., W1024_I_1023}, W1024_i=sin(2*pi*i / 1024), i=32*p+q, i=0,1,2,....,1023, W1024_I is actually a 1×1024 matrix; Arrange the input data matrix into a two-dimensional first matrix corresponding to the number of rows and columns of the calculation unit array; arrange the first real matrix and the first imaginary matrix into two-dimensional second matrices corresponding to the number of rows and columns of the calculation unit array; ① reorder the input 1024 point data into a 32*32 matrix, recorded as data_in matrix; ② Similarly, reorder W32_R, W32_I, W1024_R, and W1024_I into a 32*32 matrix; Among them, p is regarded as the number of rows, q is regarded as the number of columns, p,q=0,1,2,...,31; The order of rows and columns of the two-dimensional first matrix and the two-dimensional second matrix is ​​swapped; the data_in matrix is ​​read by column, which is actually a transposition operation, and the result is recorded as the data_in_t matrix; After transposition Multiplying the two-dimensional first matrix by the two-dimensional second matrix through the first fully connected layer computing unit to obtain a two-dimensional third matrix; Obtain a fourth matrix according to the two-dimensional third matrix, the second real matrix and the second imaginary matrix through corresponding element operations of an Eltwise module; Implementing the operation of the fourth matrix with the first real matrix and the first imaginary matrix through the second fully connected layer computing unit to obtain a fifth matrix; The output Fourier real part data and the output Fourier imaginary part data are obtained by operating the corresponding elements of the Eltwise module according to the fifth matrix.

7. The neural network hardware system according to claim 6, characterized in that: The number of the multiple input data points is 1024 input data points; the input data matrix is ​​a 1*1024 matrix; and the computing unit array is a 32*32 two-dimensional array.

8. The neural network hardware system according to claim 6 or 7, characterized in that: The first real matrix and the first imaginary matrix are 1*1024 matrices; the first bit number is 32 bits; the second real matrix and the second imaginary matrix are 1*1024 matrices; the second bit number is 1024 bits.

9. The neural network hardware system according to claim 8, characterized in that: The two-dimensional first matrix is ​​a 32*32 matrix; the two-dimensional second matrix is ​​a 32*32 matrix.

10. The neural network hardware system according to claim 8, characterized in that: The two-dimensional fourth matrix is ​​a 32*32 matrix; the two-dimensional fifth matrix is ​​a 32*32 matrix.

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