Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a discrete core layer on the substrate, wherein the core layer to be removed serves as a pseudo core layer; forming a sacrificial sidewall on the sidewall of the core layer; forming a mask sidewall on the sidewall of the sacrificial sidewall; removing the sacrificial sidewall; after removing the sacrificial sidewall, removing the pseudo core layer; and patterning the substrate using the mask sidewall and the remaining core layer as masks. The embodiments of the present invention are conducive to reducing the process difficulty of removing the pseudo core layer and increasing the process window for removing the pseudo core layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also shortened accordingly. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, so the control ability of the gate structure over the channel becomes worse, and the difficulty of pinching off the channel by the gate voltage becomes increasingly greater, making subthreshold leakage, the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to reduce the impact of the short channel effect, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (FinFETs). In FinFETs, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFETs, the gate structure has a stronger control over the channel and can effectively suppress the short channel effect; and FinFETs have better compatibility with existing integrated circuit manufacturing than other devices.

[0004] In the semiconductor field, according to process requirements, it is usually necessary to form fins with different pitches. Currently, one approach is to form fins with different pitches through a fin cut process, wherein the fin cut process generally includes a fin cut first process and a fin cut last process. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to increase the process window for removing the dummy core layer.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a discrete core layer on the substrate, wherein the core layer to be removed serves as a pseudo core layer; forming a sacrificial sidewall on the sidewall of the core layer; forming a mask sidewall on the sidewall of the sacrificial sidewall; removing the sacrificial sidewall; after removing the sacrificial sidewall, removing the pseudo core layer; and graphing the substrate using the mask sidewall and the remaining core layer as masks.

[0007] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, comprising: a substrate; a plurality of groups of mask pattern layers separated and arranged at intervals on the substrate, used as masks for forming fins, the mask pattern layers comprising a core layer and mask side walls located on both sides of the core layer and arranged at intervals with the core layer, the core layers of some of the mask pattern layers serving as pseudo core layers corresponding to the positions of the fin cuts.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the embodiment of the present invention, a sacrificial sidewall is formed on the sidewall of the core layer; and a mask sidewall is formed on the sidewall of the sacrificial sidewall. Therefore, after removing the sacrificial sidewall, a plurality of discrete groups of mask pattern layers arranged at intervals are formed on the substrate, including a core layer and mask sidewalls located on both sides of the core layer and arranged at intervals from the core layer. Subsequent steps also include: removing the dummy core layer. In a semiconductor process, the step of removing the dummy core layer generally includes: forming a mask layer on a substrate; forming a mask opening in the mask layer to expose the dummy core layer. In the embodiment of the present invention, mask sidewalls arranged at intervals from the core layer are formed on both sides of the core layer. When forming the mask opening, even if there is an overlay shift that causes the mask opening to expose the mask sidewalls on both sides of the dummy core layer, since the mask sidewalls are made of different materials from the core layer, the probability of causing mis-etching of the mask sidewalls adjacent to the dummy core layer when removing the dummy core layer is also low, thereby helping to reduce the process difficulty of removing the dummy core layer and increase the process window for removing the dummy core layer.

[0010] In addition, the process window for removing the dummy core layer is increased in the embodiment of the present invention, so it is easy to completely remove the dummy core layer by increasing the opening size of the mask opening or over-etching the dummy core layer, which is beneficial to reduce the probability of residual dummy core layer. After the substrate is subsequently patterned using the mask side wall and the remaining core layer as a mask, it is beneficial to make the target pattern formed in the substrate meet the process requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 5 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Figures 6 to 20 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0013] The devices currently formed still have the problem of poor performance. The reasons for the poor performance of the devices are now analyzed in combination with a method for forming a semiconductor structure.

[0014] refer to Figures 1 to 5 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1 , providing a substrate 1; forming a plurality of discrete sidewalls on the substrate 1, wherein the sidewalls include a mask sidewall 2 and a dummy mask sidewall 3.

[0016] refer to Figure 2 A mask layer 4 is formed on the substrate 1 , wherein the mask layer 4 has an opening 5 , and the opening 5 exposes the top of the dummy mask sidewall 3 .

[0017] refer to Figure 3 , using the mask layer 4 as a mask, removing the dummy mask sidewall 3 .

[0018] refer to Figure 4 , remove the mask layer 4.

[0019] refer to Figure 5 , using the mask sidewall 2 as a mask, patterning the substrate 1.

[0020] In the formation method, the process of removing the pseudo mask sidewall 3 is difficult and the process window is small. Specifically, in the semiconductor field, the process of removing the opening 5 is usually an anisotropic etching process, and the anisotropic etching process has a slower etching rate for the pseudo mask sidewall 3 closer to the surface of the substrate 1, which easily produces the pseudo mask sidewall 3 residue (such as Figure 3 Alternatively, when there is an overlay shift in the photolithography process for forming the opening 5, it is also easy to make it difficult to completely remove the pseudo mask sidewall 3, and thus it is easy to generate residual pseudo mask sidewall 3. When patterning the substrate 1, the residual pseudo mask sidewall 3 is easy to form an unwanted target pattern (such as Figure 5 (shown in the dashed box).

[0021] In order to prevent the dummy mask sidewalls 3 from remaining, currently, the dummy mask sidewalls are usually overetched when removing the dummy mask sidewalls, or the opening size of the opening is increased when forming the opening.

[0022] However, the above two methods are likely to increase the risk of mis-etching the mask sidewalls adjacent to the pseudo-mask sidewalls, and thus easily affect the pattern of the mask sidewalls, and correspondingly easily reduce the subsequent process effect of patterning the substrate using the mask sidewalls as a mask, and the target pattern formed is difficult to meet the process requirements.

[0023] In order to solve the technical problem, an embodiment of the present invention forms a sacrificial side wall on the side wall of the core layer; and forms a mask side wall on the side wall of the sacrificial side wall. Therefore, after removing the sacrificial side wall, a plurality of discrete groups of mask graphic layers arranged at intervals are formed on the substrate, including the core layer and the mask side walls located on both sides of the core layer and arranged at intervals with the core layer. The subsequent steps also include: removing the dummy core layer. In the semiconductor process, the step of removing the dummy core layer generally includes: forming a mask layer on the substrate; forming a mask opening in the mask layer to expose the dummy core layer. In the embodiment of the present invention, mask side walls arranged at intervals with the core layer are formed on both sides of the core layer. When the mask opening is formed, even if there is an overlay offset that causes the mask opening to expose the mask side walls on both sides of the dummy core layer, since the mask side walls and the core layer are made of different materials, the probability of causing mis-etching of the mask side walls adjacent to the dummy core layer when removing the dummy core layer is also low, which is beneficial to reducing the process difficulty of removing the dummy core layer and increasing the process window for removing the dummy core layer.

[0024] In addition, the embodiment of the present invention increases the process window for removing the dummy core layer, so it is easy to completely remove the dummy core layer by increasing the opening size of the mask opening or over-etching the dummy core layer, which is beneficial to reduce the probability of residual dummy core layer. After the substrate is subsequently patterned using the mask side wall and the remaining core layer as a mask, it is beneficial to make the target pattern formed in the substrate meet the process requirements.

[0025] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] Figures 6 to 20 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0027] refer to Figure 6 , providing a substrate 100.

[0028] The substrate 100 provides a process platform for subsequent process steps, and is also used as a material layer to be etched in a patterning process. In this embodiment, the substrate 100 is used to form a substrate and a fin protruding from the substrate.

[0029] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. In some other embodiments, the substrate may also include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, the first semiconductor layer providing a process basis for the subsequent formation of a substrate, and the second semiconductor layer providing a process basis for the subsequent formation of a fin. In other embodiments, the substrate may also be other functional layers to be etched, such as a gate material layer.

[0030] It should be noted that, continue to refer to Figure 6 In this embodiment, the formation method further includes: forming a pad oxide layer 105 on the substrate 100 ; forming a grinding stop layer 110 on the pad oxide layer 105 ; and forming a hard mask material layer 120 on the grinding stop layer 110 .

[0031] The pad oxide layer 105 is used to provide a buffering effect when forming the grinding stop layer 110, so as to avoid the problem of dislocation when the grinding stop layer 110 is directly formed on the substrate 100. In this embodiment, the material of the pad oxide layer 105 is silicon oxide.

[0032] After the substrate 100 is subsequently patterned to form a substrate and a fin protruding from the substrate, a step of forming an isolation structure on the substrate where the fin is exposed is usually included, and the formation of the isolation structure usually includes a grinding process, and the grinding stop layer 110 is used to define the stop position of the grinding process.

[0033] In this embodiment, the material of the grinding stop layer 110 is silicon nitride.

[0034] The hard mask material layer 120 is used to form a hard mask layer after a subsequent etching process, thereby serving as a mask for etching the substrate 100, and subsequently the pattern in the mask pattern layer is first transferred to the hard mask material layer 120, so that the substrate 100 can be directly etched using the hard mask layer as a mask, which is beneficial to improving the process stability and process effect of the subsequent patterning of the substrate 100.

[0035] In addition, the core layer, sacrificial sidewalls and mask sidewalls subsequently formed on the substrate 100 are usually formed by a process combining deposition and etching. The top surface of the hard mask material layer 120 is also used to define the stop position of the etching process to avoid over-etching problems.

[0036] In this embodiment, the material of the hard mask material layer 120 is titanium nitride. In other embodiments, the material of the hard mask material layer can also be silicon oxide, silicon oxynitride, silicon oxycarbonitride or other suitable materials such as silicon, depending on the materials of the substrate and the subsequent core layer, sacrificial sidewalls and mask sidewalls.

[0037] Combination Figure 6 ,refer to Figure 7 , a separate core layer 130 is formed on the substrate 100, wherein the core layer 130 to be removed serves as a dummy core layer 130a.

[0038] The subsequent step also includes forming a sacrificial sidewall on the sidewall of the core layer 130 , and the core layer 130 is used to provide support for forming the sacrificial sidewall. Part of the core layer 130 is also used as an etching mask for the subsequent patterning of the substrate 100 .

[0039] The dummy core layer 130a is a core layer to be removed later. Specifically, in this embodiment, the position of the dummy core layer 130a corresponds to the position of the fin cut.

[0040] The material of the core layer 130 includes amorphous silicon, silicon nitride, silicon oxide, amorphous carbon, photoresist or metal oxide. Among them, the metal oxide can be titanium oxide. In this embodiment, the material of the core layer 130 is amorphous silicon. Amorphous silicon is a core layer material commonly used in the patterning process.

[0041] In this embodiment, the steps of forming the core layer 130 include:

[0042] like Figure 6 As shown, a core material layer 125 is formed on the substrate 100 .

[0043] Specifically, the core material layer 125 is formed on the hard mask material layer 120 .

[0044] The core material layer 125 is used to form a core layer after a subsequent patterning process.

[0045] Continue to refer Figure 6 , an organic coating layer 101 is formed on the core material layer 125 ; a first anti-reflection coating layer 102 is formed on the organic coating layer 101 ; and a patterned first photoresist layer 103 is formed on the first anti-reflection coating layer 102 .

[0046] The organic coating layer 101 is used to provide a good interface state for the formation of subsequent film layers to improve the surface flatness of the subsequent film layers, thereby improving the accuracy and process effect of the patterning process when forming the first photoresist layer. In this embodiment, the organic coating layer 101 is a spin-on carbon (SOC) layer.

[0047] The first anti-reflection coating 102 is used to reduce the reflection effect during exposure, thereby improving the transfer accuracy of the pattern. In this embodiment, the first anti-reflection coating 102 is a Si-ARC layer (Si-based anti-reflection coating), which is beneficial to improving exposure uniformity, thereby further improving the transfer accuracy of the pattern.

[0048] The first photoresist layer 103 is used as an etching mask for patterning the core material layer 125 .

[0049] like Figure 7 As shown, using the first photoresist layer 103 as a mask, the first anti-reflective coating layer 102 , the organic coating layer 101 and the core material layer 125 are sequentially etched to form a core layer 130 .

[0050] In this embodiment, the core material layer 125 is etched using a dry etching process.

[0051] In this embodiment, the material of the core layer 130 is amorphous silicon, and the main etching gas of the dry etching process includes C x F y , Cl2 and HBr. Wherein, x and y are positive integers greater than zero.

[0052] During the etching process, the first photoresist layer 103 and the first anti-reflective coating layer 102 are consumed in sequence. Therefore, after the core layer 130 is formed, only a partial thickness of the organic coating layer 101 remains on the top of the core layer 130 .

[0053] Accordingly, the formation method further includes: removing the organic coating layer 101. By removing the organic coating layer 101, the core layer 130 is exposed, providing a process basis for subsequently forming a sacrificial sidewall on the sidewall of the core layer 130. Specifically, the organic coating layer 101 can be removed by ashing.

[0054] refer to Figures 8 to 9 , forming a sacrificial spacer 140 (such as Fig. 9 shown).

[0055] The subsequent step also includes a step of forming a mask sidewall on the sidewall of the sacrificial sidewall 140 , and the sacrificial sidewall 140 provides support for forming the mask sidewall.

[0056] The material of the sacrificial sidewall 140 includes amorphous carbon, silicon oxide, silicon nitride, silicon or metal oxide. Among them, the metal oxide can be titanium oxide and other materials. In this embodiment, the material of the sacrificial sidewall 140 is silicon nitride. Silicon nitride material is a common material in semiconductor processes, which is conducive to improving process compatibility.

[0057] In this embodiment, the steps of forming the sacrificial spacer 140 include:

[0058] like Figure 8 As shown, a first spacer film 135 is formed to conformally cover the top and sidewalls of the core layer 130 and the hard mask material layer 120. The first spacer film 135 is used to form a sacrificial spacer through a subsequent etching process.

[0059] In this embodiment, an atomic layer deposition process is used to form the first sidewall film 135. The atomic layer deposition process forms a thin film by depositing a single atomic layer layer by layer. The atomic layer deposition process has a strong gap filling ability and step coverage ability, which is conducive to improving the formation quality and thickness uniformity of the first sidewall film 135 and reducing the difficulty of controlling the thickness of the first sidewall film 135.

[0060] like Fig. 9 As shown, the first spacer film 135 on the top of the core layer 130 and the top of the hard mask material layer 120 is removed, and the remaining first spacer film 135 is used as a sacrificial spacer 140 .

[0061] In this embodiment, in the step of removing the first spacer film 135 on the top of the core layer 130 and the top of the hard mask material layer 120, the etching selectivity ratio of the first spacer film 135 to the core layer 130, and the etching selectivity ratio of the first spacer film 135 to the hard mask material layer 120 are both greater than 3, thereby reducing the probability of damage to the core layer 130 and the hard mask material layer 120 in this step.

[0062] In this embodiment, the first spacer film 135 is etched by a dry etching process to remove the first spacer film 135 on the top of the core layer 130 and the top of the hard mask material layer 120. The dry etching process has the characteristic of anisotropic etching, and can etch the first spacer film 135 in a direction perpendicular to the surface of the substrate 100 in a maskless etching manner, thereby removing the first spacer film 135 on the top of the core layer 130 and the hard mask material layer 120 while retaining the first spacer film 135 on the side wall of the core layer 130. Moreover, the etching selectivity of the dry etching process is relatively high, which is conducive to ensuring that the etching selectivity ratio of the first spacer film 135 to the core layer 130 and the etching selectivity ratio of the first spacer film 135 to the hard mask material layer 120 meet the process requirements.

[0063] refer to Figure 10 to Figure 11 , a mask sidewall 150 (such as Fig.11 The mask sidewall 150 is used as a partial etching mask for the subsequent patterning of the substrate 100.

[0064] In this embodiment, the material of the mask sidewall 150 is silicon oxide. The mask sidewall 150 is usually formed by deposition and etching. Silicon oxide and silicon nitride, as well as silicon oxide and amorphous silicon, have a large etching selectivity, thereby preventing the etching process when forming the mask sidewall 150 from damaging the sacrificial sidewall 140 and the core layer 130, and facilitating the subsequent removal of the sacrificial sidewall 140 and the dummy core layer 130a. At the same time, the process of removing the sacrificial sidewall 140 and the dummy core layer 130a has little effect on the mask sidewall 150.

[0065] In other embodiments, according to the materials of the core layer and the sacrificial sidewall, the material of the mask sidewall may also be amorphous carbon, silicon nitride, silicon, or metal oxide, etc. The metal oxide may be titanium oxide, etc.

[0066] In this embodiment, the steps of forming the mask sidewall 150 include:

[0067] like Fig.10 As shown, a second spacer film 145 is formed to conformally cover the top and sidewall of the sacrificial spacer 140 , the top of the core layer 130 , and the top of the hard mask material layer 120 .

[0068] The second spacer film 145 is used to form a mask spacer after a subsequent etching process.

[0069] In this embodiment, the second spacer film 145 is formed by an atomic layer deposition process, which is beneficial to improving the conformal coverage and thickness uniformity of the second spacer film 145 .

[0070] like Fig.11 As shown, the second spacer film 145 located on the sacrificial spacer 140 , the top of the core layer 130 , and the top of the hard mask material layer 120 is removed, and the remaining second spacer film 145 is used as a mask spacer 150 .

[0071] In this embodiment, in the step of removing the sacrificial sidewall 140, the core layer 130 and the second sidewall film 145 on the top of the hard mask material layer 120, the etching selectivity ratio of the second sidewall film 145 and the core layer 130, and the etching selectivity ratio of the second sidewall film 145 and the sacrificial sidewall 140 are both greater than 3, thereby preventing the core layer 130 and the sacrificial sidewall 140 from being damaged in this step.

[0072] In this embodiment, a dry etching process is used to etch the second spacer film 145. The dry etching process has the characteristics of anisotropic etching, and can remove the sacrificial spacer 140, the core layer 130 and the second spacer film 145 on the top of the hard mask material layer 120 in a maskless etching manner, and the second spacer film 145 located on the side wall of the sacrificial spacer 140 can be retained; in addition, the dry etching process is easy to achieve a large etching selectivity, so that the etching selectivity of the second spacer film 145 and the core layer 130, and the etching selectivity of the second spacer film 145 and the sacrificial spacer 140 meet the process requirements.

[0073] It should be noted that, in the present embodiment, in the step of forming the mask sidewall 150 on the sidewall of the sacrificial sidewall 140 , the mask sidewall 150 to be removed serves as the dummy mask sidewall 150 a .

[0074] The dummy mask spacer 150a serves as the mask spacer 150 to be removed later, thereby preventing an unnecessary target pattern from being formed later in the substrate 100. Specifically, in this embodiment, the position of the dummy mask spacer 150a corresponds to the position of the fin cut.

[0075] refer to Fig.12 , remove the sacrificial sidewall 140 (such as Fig.11 shown).

[0076] After removing the sacrificial sidewalls 140, a plurality of discrete groups of spaced-apart mask pattern layers 200 are formed on the substrate 100, including a core layer 130 and mask sidewalls 150 located on both sides of the core layer 130 and spaced-apart from the core layer 150. In the subsequent step of removing the dummy core layer 130a, since mask sidewalls 150 spaced-apart from the dummy core layer 130a are formed on both sides of the dummy core layer 130a, and the mask sidewalls 150 are made of different materials from the core layer 130, the probability of mis-etching the mask sidewalls 150 when removing the dummy core layer 130a is low.

[0077] Moreover, the probability of mis-etching the mask sidewall 150 when the dummy core layer 130a is subsequently removed is low. Therefore, it is easy to completely remove the dummy core layer 130a by adjusting the process steps for removing the dummy core layer 130a, which is beneficial to reduce the probability of residual dummy core layer 130a.

[0078] Therefore, in the step of removing the sacrificial sidewall 140, the etching selectivity ratio of the sacrificial sidewall 140 to the core layer 130, and the etching selectivity ratio of the sacrificial sidewall 140 to the mask sidewall 150 should not be too small, so as to ensure that the probability of causing mis-etching to the core layer 130 and the mask sidewall 150 is low, and in order to completely remove the sacrificial sidewall 140, the sacrificial sidewall 140 is usually required to be over-etched. If the etching selectivity ratio is too small, it is easy to further increase the probability of damage to the core layer 130 and the mask sidewall 150. For this reason, in the present embodiment, in the step of removing the sacrificial sidewall 140, the etching selectivity ratio of the sacrificial sidewall 140 to the core layer 130, and the etching selectivity ratio of the sacrificial sidewall 140 to the mask sidewall 150 are both greater than 10.

[0079] In this embodiment, a wet etching process is used to remove the sacrificial sidewall 140. The wet etching process is easy to achieve a large etching selectivity ratio, and the process is simple. Specifically, in this embodiment, the material of the sacrificial sidewall 140 is silicon nitride, and the etching solution is a phosphoric acid solution. The phosphoric acid solution is an etching solution commonly used for etching silicon nitride materials in semiconductor processes, and the phosphoric acid solution has a low etching rate for amorphous silicon and silicon oxide.

[0080] The sacrificial sidewall 140 may also be removed by dry etching. The dry etching process may be a plasma etching process. The plasma etching process is easy to achieve a large etching selectivity ratio, and the plasma etching process has high etching precision and high etching efficiency. Specifically, the main etching gas of the plasma etching process includes C x F y , C x H y F z and C x H y The auxiliary etching gas includes one or more of H2, Cl2, HBr, Ar, O2 and SO2. The auxiliary etching gas is used to adjust the etching rate, etching uniformity and etching selectivity, and also adjusts the amount of etching byproducts in the etching chamber, which is beneficial to improve the removal effect of the sacrificial sidewall 140. In addition, x, y and z are all positive integers greater than zero.

[0081] In other embodiments, when the material of the sacrificial sidewall is other materials, a suitable etching process is used to remove the sacrificial sidewall. For example, when the material of the sacrificial sidewall is silicon oxide, a dry etching process is used to remove the sacrificial sidewall. The main etching gas used in the dry etching process includes C x F y , C x H y F z and C x H yOne or more of the auxiliary etching gases include one or more of H2, Cl2, HBr, Ar, O2 and SO2; when the material of the sacrificial sidewall is silicon or metal oxide, a dry etching process is used to remove the sacrificial sidewall, and the main etching gas used in the dry etching process includes C x F y , Cl2 and HBr, the auxiliary etching gas includes C x H y F z , C x H y , one or more of H2, Ar, O2 and SO2; when the material of the sacrificial side wall is amorphous carbon, the SPM solution is used to remove the sacrificial side wall, wherein the SPM solution refers to a mixed solution of H2SO4 and H2O2.

[0082] refer to Figures 13 to 15 After removing the sacrificial sidewall 140 , the dummy core layer 130 a is removed.

[0083] The dummy core layer 130a is removed to prevent the subsequent formation of unnecessary patterns in the substrate 100. In this embodiment, the substrate 100 is used to form a substrate and a fin protruding from the substrate. Therefore, after removing the dummy core layer 130a, no dummy fin will be formed in the substrate 100, and accordingly, there is no need to perform the step of removing the dummy fin, which is beneficial to improving the quality of subsequent fin formation.

[0084] The step of removing the dummy core layer 130a generally includes: forming a mask layer on the substrate 100; forming a mask opening in the mask layer to expose the dummy core layer 130a. In the present embodiment, mask sidewalls 150 are formed on both sides of the core layer 130 and are arranged at intervals from the core layer 130. When the mask opening is formed, even if there is an overlay offset that causes the mask opening to expose the mask sidewalls 150 on both sides of the dummy core layer 130a, since the mask sidewalls 150 and the core layer 130 are made of different materials, when removing the dummy core layer 130a, the probability of causing mis-etching of the mask sidewalls 150 adjacent to the dummy core layer 130a is also low, which is beneficial to reducing the process difficulty of removing the dummy core layer 130a and increasing the process window for removing the dummy core layer 130a.

[0085] In addition, the process window for removing the dummy core layer 130a in the present embodiment is relatively large, so it is easy to completely remove the dummy core layer 130a by increasing the opening size of the mask opening or over-etching the dummy core layer 130a, thereby helping to reduce the probability of residual dummy core layer 130a. After subsequently patterning the substrate 100 using the mask side wall 150 and the remaining core layer 130 as a mask, it is helpful to make the target pattern formed in the substrate 100 meet the process requirements.

[0086] In this embodiment, the step of removing the dummy core layer 130a includes:

[0087] like Fig.13 As shown, a first mask layer 151 covering the core layer 130 and the mask sidewalls 150 is formed on the substrate 100. The first mask layer 151 is used as an etching mask for subsequently removing the dummy core layer 130a after forming a first mask opening exposing the dummy core layer 130a through a subsequent patterning process.

[0088] The first mask layer 151 needs to be removed later. Therefore, in order to reduce the difficulty of the subsequent removal process of the first mask layer 151, the first mask layer 151 is made of a material that is easy to remove, and the process of removing the first mask layer 151 causes little damage to the mask side wall 150 and the core layer 130.

[0089] In this embodiment, the material of the first mask layer 151 is SOC. The SOC material has low cost, simple formation process and high process compatibility.

[0090] In other embodiments, the material of the first mask layer may also be BARC (bottom anti-reflective coating) material, photoresist, ODL (organic dielectric layer) material, DARC (dielectric anti-reflective coating) material or DUO (Deep UV Light Absorbing Oxide) material.

[0091] In this embodiment, the first mask layer 151 is formed by a spin coating process.

[0092] Combination Fig.13 ,like Fig.14 As shown, a first mask opening 155 exposing the dummy core layer 130a is formed in the first mask layer 151. The first mask opening 155 is prepared for the subsequent removal of the dummy core layer 130a.

[0093] In this embodiment, before forming the first mask opening 155, the process further includes: Fig.13 As shown, a second anti-reflective coating 152 is formed on the first mask layer 151 ; a second photoresist layer 153 is formed on the second anti-reflective coating 152 , and a first graphic opening (not shown) exposing a portion of the second anti-reflective coating 152 is formed in the second photoresist layer 153 .

[0094] The second anti-reflective coating 152 is used to reduce the reflection effect during exposure, thereby improving the transfer accuracy of the pattern. In this embodiment, the second anti-reflective coating 152 is a Si-ARC layer, which is beneficial to improving the uniformity of exposure, thereby further improving the transfer accuracy of the pattern.

[0095] The second photoresist layer 153 is used to etch the first mask layer 151 to form an etching mask for a first mask opening. The first pattern opening is formed by performing a photolithography process such as exposure and development on the second photoresist layer 153.

[0096] Therefore, the step of forming the first mask opening 155 includes: using the second photoresist layer 153 as a mask, sequentially etching the second anti-reflective coating 152 and the first mask layer 151 along the first pattern opening to form the first mask opening 155 in the first mask layer 151 .

[0097] In this embodiment, since mask sidewalls 150 are formed on both sides of the core layer 130 and are arranged at intervals from the core layer 130, when forming the first mask opening 155, even if there is an overlay offset that causes the first mask opening 155 to expose the mask sidewalls 150, the probability of damaging the mask sidewalls 150 is low. The first mask opening 155 is obtained by etching the first mask layer 151 along the first pattern opening using the second photoresist layer 153 as a mask, that is, when the second photoresist layer 153 is subjected to a photolithography process such as exposure and development to form the first pattern opening, the overlay offset requirement for the photolithography process is relatively low, thereby increasing the process window of the photolithography process, thereby significantly reducing the process difficulty of removing the dummy core layer 130a.

[0098] In this embodiment, a dry etching process is used to etch the second anti-reflective coating 152 and the first mask layer 151. Specifically, in this embodiment, the material of the first mask layer 151 is SOC, and the main etching gas of the dry etching process includes one or more of SO2, O2, Ar, N2, H2, and COS.

[0099] In this embodiment, during the etching process, the second photoresist layer 153 and the second anti-reflective coating layer 152 are consumed in sequence. Therefore, after the first mask opening 155 is formed, only a partial thickness of the first mask layer 151 remains.

[0100] like Fig.15 As shown, the first mask layer 151 is used as a mask to remove the dummy core layer 130 a exposed by the first mask opening 155 .

[0101] In the step of removing the dummy core layer 130a, the etching selectivity ratio of the dummy core layer 130a to the mask sidewall 150 should not be too small, otherwise there is a high risk of mis-etching the mask sidewall 150. In this embodiment, in the step of removing the dummy core layer 130a, the etching selectivity ratio of the dummy core layer 130a to the mask sidewall 150 is greater than 5.

[0102] In this embodiment, a dry etching process is used to remove the dummy core layer 130a. By using the dry etching process, it is easy to achieve a larger etching selectivity, thereby reducing the risk of causing mis-etching to the mask sidewall 150, and the dry etching process has good process controllability and high etching precision, which is also conducive to improving etching efficiency.

[0103] In this embodiment, the material of the dummy core layer 130a is amorphous silicon. Therefore, the main etching gas of the dry etching process includes C x F y , Cl2 and HBr, the auxiliary etching gas includes C x H y F z , C x H y , H2, Ar, O2 and SO2.

[0104] In other embodiments, when the core layer is made of other materials, a suitable etching process is used to remove the dummy core layer.

[0105] It should be noted that, in this embodiment, after removing the dummy core layer 130a, the forming method further includes: removing the first mask layer 151, so as to expose the remaining core layer 130 and the mask sidewall 150, in preparation for subsequent process steps.

[0106] In this embodiment, the material of the first mask layer 151 is SOC, so an ashing process is used to remove the first mask layer 151. The ashing process has simple process steps and low process cost, and the ashing process causes little damage to the core layer 130 and the mask sidewall 150.

[0107] It should also be noted that, combined with reference Figures 16 to 18 In this embodiment, after removing the sacrificial sidewall 140 , the forming method further includes: removing the dummy mask sidewall 150 a .

[0108] In this embodiment, after the dummy core layer 130 a is removed, the dummy mask sidewall 150 a is removed.

[0109] The dummy mask sidewall 150a is removed, thereby preventing the subsequent formation of an unnecessary target pattern in the substrate 100. Specifically, in this embodiment, the dummy mask sidewall 150a corresponds to the position of the fin cut, so that no dummy fin is formed in the subsequent substrate 100, and the step of removing the dummy fin is not required, thereby preventing the fin from being damaged and improving the formation quality of the fin.

[0110] In the present embodiment, when the pseudo-mask sidewall 150a is removed, since a core layer 130 is formed on one side of the mask sidewall 150 and is arranged at intervals with the mask sidewall 150, even if there is an overlay offset in the mask opening formed when the pseudo-mask sidewall 150a is removed, since the core layer 130 and the mask sidewall 150 are made of different materials, the probability of the core layer 130 being damaged when the pseudo-mask sidewall 150a is removed is also low, thereby increasing the process window for removing the pseudo-mask sidewall 150a.

[0111] In this embodiment, in the step of removing the dummy mask sidewalls 150a, at least two adjacent dummy mask sidewalls 150a are removed. Specifically, after removing the sacrificial sidewalls 140, a plurality of discrete groups of mask pattern layers 200 arranged at intervals are formed on the substrate 100, including the core layer 130 and the mask sidewalls 150 located on both sides of the core layer 130 and arranged at intervals with the core layer 130. Therefore, the core layer 130 is formed on both sides of each two adjacent dummy mask sidewalls 150a. By removing at least two adjacent dummy mask sidewalls 150a, it is beneficial to further increase the process window for removing the dummy mask sidewalls 150a.

[0112] In this embodiment, the step of removing the dummy mask sidewall 150a includes:

[0113] like Fig.16 As shown, a second mask layer 156 is formed on the substrate 100 .

[0114] The second mask layer 156 is used as an etching mask for removing the dummy mask sidewall 150 a after a second mask opening is formed to expose the dummy mask sidewall 150 a through a subsequent patterning process.

[0115] In this embodiment, the material of the second mask layer 156 is SOC.

[0116] In this embodiment, the second mask layer 156 is formed by a spin coating process.

[0117] Combination Fig.16 ,like Fig.17 As shown, a second mask opening 160 exposing the dummy mask sidewall 150a is formed in the second mask layer 156. The second mask opening 160 exposes the dummy mask sidewall 150a, preparing for the subsequent removal of the dummy mask sidewall 150a.

[0118] In this embodiment, before forming the second mask opening 160, Fig.16 As shown, it also includes: forming a third anti-reflective coating 157 on the second mask layer 156; forming a third photoresist layer 158 on the third anti-reflective coating 157, and forming a second graphic opening (not marked) in the third photoresist layer 158 to expose a portion of the third anti-reflective coating 157.

[0119] In this embodiment, the material of the third anti-reflection coating 157 is BARC. For a detailed description of the third anti-reflection coating 157 , reference may be made to the above description of the second anti-reflection coating 152 .

[0120] Therefore, in this embodiment, the step of forming the second mask opening 160 includes: using the third photoresist layer 158 as a mask, and sequentially etching the third anti-reflective coating 157 and the second mask layer 156 along the second pattern opening.

[0121] In the present embodiment, the process window for forming the second mask opening 160 is relatively large. The second mask opening 160 is obtained by etching the second mask layer 156 along the second graphic opening using the third photoresist layer 158 as a mask. That is to say, the process window for forming the second graphic opening in the present embodiment is relatively large. Therefore, the overlay offset accuracy requirement when forming the second graphic opening is relatively low. This is beneficial for significantly increasing the process window of the lithography process when forming the second graphic opening and reducing the process difficulty of the lithography process.

[0122] In this embodiment, a dry etching process is used to etch the third anti-reflection coating 157 and the second mask layer 156. The process of etching the third anti-reflection coating 157 and the second mask layer 156 is the same as the process of etching the second anti-reflection coating 152 and the first mask layer 151, which will not be repeated here.

[0123] like Fig.18 As shown, the dummy mask sidewalls 150 a exposed by the second mask opening 160 are removed.

[0124] In the step of removing the dummy mask sidewall spacer 150 a in this embodiment, the etching selectivity ratio between the dummy mask sidewall spacer 150 a and the core layer 130 is greater than 5, thereby reducing the probability of causing mis-etching to the core layer 130 .

[0125] In this embodiment, the dummy mask sidewall 150a is removed by dry etching, which can easily achieve a larger etching selectivity ratio, and has good process controllability and etching accuracy, which is beneficial to improving the process effect of removing the dummy mask sidewall 150a.

[0126] In this embodiment, the material of the dummy mask sidewall 150a is silicon oxide, and the main etching gas of the dry etching process includes C x F y , Cx H y F z and C x H y One or more of the auxiliary etching gases include one or more of H2, Cl2, HBr, Ar, O2 and SO2.

[0127] Continue to refer Fig.18 In this embodiment, after removing the dummy mask sidewall 150a, the forming method further includes: removing the second mask layer 156. Thus, the core layer 130 and the mask sidewall 150 are exposed, preparing for the subsequent patterning of the substrate 100. In this embodiment, the second mask layer 156 is removed by an ashing process.

[0128] refer to Figure 19 to Figure 20 The substrate 100 is patterned using the mask sidewall 150 and the remaining core layer 130 as masks. In this embodiment, the dummy core layer 130a is removed before the substrate 100 is patterned. Therefore, after the substrate 100 is patterned, the desired target pattern is directly formed in the substrate 100.

[0129] Specifically, in this embodiment, after the substrate 100 is patterned, the remaining substrate 100 is used as a substrate to form the fins 180. In this embodiment, before the substrate 100 is patterned, the dummy core layer 130a is removed, so that after the fins 180 are formed, adjacent fins 180 have different spacings.

[0130] In this embodiment, before patterning the substrate 100 , the dummy mask sidewalls 150 a are removed, and thus the substrate 100 is patterned using the remaining mask sidewalls 150 and the remaining core layer 130 as masks.

[0131] In this embodiment, the fin 180 and the substrate are an integrated structure. In other embodiments, when the substrate includes a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, in the step of etching the substrate, only the first semiconductor layer is etched, the first semiconductor layer is used as the substrate, and the remaining second semiconductor layer protruding from the first semiconductor layer is used as the fin. Accordingly, the material of the fin may also be different from that of the substrate.

[0132] In this embodiment, the steps of patterning the substrate 100 include:

[0133] like Fig.19 As shown, the remaining mask sidewall 150 and the remaining core layer 130 are used as masks to pattern the hard mask material layer 120 (eg Fig.18 As shown), a hard mask layer 170 is formed.

[0134] By first transferring the patterns of the remaining mask sidewalls 150 and the remaining core layer 130 to the hard mask layer 170 , the substrate 100 is subsequently patterned using only the hard mask layer 170 as a mask, which is beneficial to improving the process stability and process effect of the patterned substrate 100 .

[0135] It should be noted that, during the pattern transfer process, the mask spacers 150 and the core layer 130 are also lost. Therefore, after the hard mask layer 170 is formed, the mask spacers 150 and the core layer 130 are removed.

[0136] like Fig. 20 As shown, the substrate 100 is patterned using the hard mask layer 170 as a mask.

[0137] In this embodiment, a pad oxide layer 105 and a grinding stop layer 110 located on the pad oxide layer 105 are also formed on the substrate 100. Therefore, before patterning the substrate 100, the pad oxide layer 105 and the grinding stop layer 110 are patterned using the hard mask layer 170 as a mask.

[0138] Accordingly, the present invention also provides a semiconductor structure. Fig.12 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0139] The semiconductor structure includes: a substrate 100; a plurality of groups of mask pattern layers 200 separated and arranged at intervals on the substrate 100, used as masks for forming fins, the mask pattern layers 200 include a core layer 130 and mask sidewalls 150 located on both sides of the core layer 130 and arranged at intervals with the core layer 130, and the core layer 130 of a portion of the mask pattern layers 200 serves as a pseudo core layer 130a, corresponding to the position of the fin cut.

[0140] The pseudo core layer 130a corresponds to the position of the fin cut, that is, the pseudo core layer 130a needs to be removed later, and in the semiconductor process, the step of removing the pseudo core layer 130a generally includes: forming a mask layer on the substrate 100; forming a mask opening in the mask layer to expose the pseudo core layer 130a. In this embodiment, mask sidewalls 150 are formed on both sides of the core layer 130 and are arranged at intervals with the core layer 130. When the mask opening is formed, even if there is an overlay offset that causes the mask opening to expose the mask sidewalls 150 on both sides of the pseudo core layer 130a, since the mask sidewalls 150 and the core layer 130 are made of different materials, when removing the pseudo core layer 130a, the probability of causing the mask sidewalls 150 adjacent to the pseudo core layer 130a to be erroneously etched is also low, which is beneficial to reducing the process difficulty of removing the pseudo core layer 130a and increasing the process window for removing the pseudo core layer 130a.

[0141] In addition, the process window for subsequent removal of the dummy core layer 130a is relatively large, so it is easy to completely remove the dummy core layer 130a by increasing the opening size of the mask opening or over-etching the dummy core layer 130a, thereby helping to reduce the probability of residual dummy core layer 130a. After the substrate 100 is subsequently patterned using the mask side wall 150 and the remaining core layer 130 as a mask, it is helpful to make the fins formed in the substrate 100 meet the process requirements.

[0142] The substrate 100 is used to provide a process platform for the process, and is also used as a material layer to be etched in a patterning process. In this embodiment, the substrate 100 is used to form a substrate and a fin protruding from the substrate.

[0143] In this embodiment, the material of the substrate 100 is silicon.

[0144] After the dummy core layer 130 a is subsequently removed, the remaining mask pattern layer 200 is used as a mask for patterning the substrate 100 to form the fin.

[0145] The material of the core layer 130 includes amorphous silicon, silicon nitride, silicon oxide, amorphous carbon, photoresist or metal oxide. In this embodiment, the material of the core layer 130 is amorphous silicon. Amorphous silicon is a core layer material commonly used in patterning processes.

[0146] In this embodiment, the material of the mask sidewall 150 is silicon oxide. The mask sidewall 150 is usually formed by deposition and etching. The silicon oxide material has a large etching selectivity ratio with amorphous silicon, thereby preventing the etching process when forming the mask sidewall 150 from damaging the core layer 130, and facilitating the subsequent removal of the dummy core layer 130a. At the same time, the process of removing the dummy core layer 130a has little effect on the mask sidewall 150.

[0147] In other embodiments, according to the material of the core layer, the material of the mask sidewalls may also be amorphous carbon, silicon oxide, silicon, silicon nitride or metal oxide, etc. Among them, the metal oxide may be titanium oxide, etc.

[0148] It should be noted that, in the present embodiment, a portion of the mask sidewalls 150 of the mask pattern layer 200 serves as dummy mask sidewalls 150 a , corresponding to the position of the fin cut.

[0149] The dummy mask spacer 150 a is a mask spacer 150 to be removed subsequently, so as to prevent a dummy fin from being formed in the substrate 100 subsequently.

[0150] It should also be noted that, in this embodiment, the semiconductor structure further includes: a pad oxide layer 105, located on the substrate 100; a grinding stop layer 110, located on the pad oxide layer 105; and a hard mask material layer 120, located on the grinding stop layer 110. Accordingly, in this embodiment, the mask pattern layer 200 is separated on the hard mask material layer 120.

[0151] The pad oxide layer 105 is used to provide a buffering effect when forming the grinding stop layer 110, so as to avoid the problem of dislocation when the grinding stop layer 110 is directly formed on the substrate 100. In this embodiment, the material of the pad oxide layer 105 is silicon oxide.

[0152] After the substrate 100 is subsequently patterned to form a substrate and a fin protruding from the substrate, a step of forming an isolation structure on the substrate where the fin is exposed is usually included, and the formation of the isolation structure usually includes a grinding process, and the grinding stop layer 110 is used to define the stop position of the grinding process.

[0153] In this embodiment, the material of the grinding stop layer 110 is silicon nitride.

[0154] The hard mask material layer 120 is used to form a hard mask layer after a subsequent etching process, thereby serving as a mask for etching the substrate 100, and subsequently the pattern in the mask pattern layer 200 is first transferred to the hard mask material layer 120 to form a hard mask layer, so that the substrate 100 is subsequently etched directly using the hard mask layer as a mask, which is beneficial to improving the process stability and process effect of the subsequent patterning of the substrate 100.

[0155] In addition, the core layer 130 and the mask sidewalls 150 are usually formed by a process combining deposition and etching, and the top surface of the hard mask material layer 120 is also used to define the stop position of the etching process to avoid over-etching.

[0156] In this embodiment, the material of the hard mask material layer 120 is titanium nitride. In other embodiments, the material of the hard mask material layer may also be silicon oxide, silicon oxynitride, silicon oxycarbonitride or silicon or other suitable materials according to the materials of the substrate, the core layer and the mask sidewalls.

[0157] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0158] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, and forming a hard mask material layer on the substrate; forming a pad oxide layer on the substrate; forming a grinding stop layer on the pad oxide layer; forming the hard mask material layer on the grinding stop layer; forming a discrete core layer on the substrate, wherein the core layer is formed on the hard mask material layer, wherein the core layer to be removed serves as a dummy core layer, and the discrete core layer includes two adjacent dummy core layers; Forming a sacrificial sidewall on the sidewall of the core layer; the steps of forming the sacrificial sidewall include: forming a first sidewall film that conformally covers the top and sidewall of the core layer and the hard mask material layer; removing the first sidewall film on the top of the core layer and the top of the hard mask material layer, and the remaining first sidewall film is used as a sacrificial sidewall; A mask sidewall is formed on the sidewall of the sacrificial sidewall, wherein two mask sidewalls are located between two adjacent pseudo core layers. In the step of forming the mask sidewall on the sidewall of the sacrificial sidewall, the mask sidewall to be removed is used as a pseudo mask sidewall, and the mask sidewalls on the sidewalls of different sacrificial sidewalls are spaced apart. The step of forming the mask sidewall comprises: forming a second sidewall film conformally covering the top and sidewall of the sacrificial sidewall, the top of the core layer, and the top of the hard mask material layer; removing the second sidewall film located on the sacrificial sidewall, the top of the core layer, and the top of the hard mask material layer, and the remaining second sidewall film is used as a mask sidewall; The sacrificial sidewalls are removed, and after the sacrificial sidewalls are removed, a plurality of discrete groups of mask pattern layers arranged at intervals are formed on the substrate, including a core layer and mask sidewalls located on both sides of the core layer and arranged at intervals from the core layer; After removing the sacrificial sidewall, the dummy core layer is removed; after removing the sacrificial sidewall, the forming method further comprises: removing the dummy mask sidewall, in the step of removing the dummy mask sidewall, removing at least two adjacent dummy mask sidewalls; Using the remaining mask side walls and the remaining core layer as masks, the hard mask material layer, the grinding stop layer, the pad oxide layer and the base are patterned to form a substrate, a fin separated from the substrate, a pad oxide layer located on top of the fin, a grinding stop layer located on top of the pad oxide layer and a hard mask layer located on top of the grinding stop layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the step of removing the dummy mask sidewalls, an etching selectivity ratio between the dummy mask sidewalls and the core layer is greater than 5.

3. The method for forming a semiconductor structure according to claim 2, wherein: The pseudo mask sidewall is removed by dry etching process, wherein the main etching gas of the dry etching process includes C x F y , C x H y F z and C x H y One or more of the auxiliary etching gases include one or more of H2, Cl2, HBr, Ar, O2 and SO2.

4. The method for forming a semiconductor structure according to claim 1, wherein: In the step of removing the dummy core layer, an etching selectivity ratio between the dummy core layer and the mask sidewall is greater than 5.

5. The method for forming a semiconductor structure according to claim 4, wherein: The dummy core layer is removed by a dry etching process, wherein the main etching gas of the dry etching process includes C x F y , Cl2 and HBr, the auxiliary etching gas includes C x H y F z , C x H y , H2, Ar, O2 and SO2.

6. The method for forming a semiconductor structure according to claim 1, wherein: The material of the sacrificial spacer includes amorphous carbon, silicon oxide, silicon nitride, silicon or metal oxide.

7. The method for forming a semiconductor structure according to claim 1, wherein: In the step of removing the sacrificial sidewall, an etching selectivity ratio between the sacrificial sidewall and the core layer, and an etching selectivity ratio between the sacrificial sidewall and the mask sidewall are both greater than 10.

8. The method for forming a semiconductor structure according to claim 7, wherein: The sacrificial sidewall is removed by using a phosphoric acid solution.

9. The method for forming a semiconductor structure according to claim 7, wherein: The sacrificial sidewall is removed by a dry etching process, wherein the main etching gas of the dry etching process includes C x F y , C x H y F z and C x H y One or more of the auxiliary etching gases include one or more of H2, Cl2, HBr, Ar, O2 and SO2.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the core layer includes amorphous silicon, silicon nitride, silicon oxide, amorphous carbon, photoresist or metal oxide.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the mask sidewalls includes amorphous carbon, silicon nitride, silicon oxide, silicon, or metal oxide.

12. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the sacrificial spacer includes an atomic layer deposition process.

13. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the mask sidewalls includes an atomic layer deposition process.

14. The method for forming a semiconductor structure according to claim 1, wherein: After the substrate is patterned, the remaining substrate is used as a substrate to form fins.

15. A semiconductor structure, characterized in that: Formed by the method according to any one of claims 1 to 14, comprising: substrate; A fin portion, separated on the substrate; a pad oxide layer located on top of the fin; a grinding stop layer located on top of the pad oxide layer; A hard mask layer is located on top of the grinding stop layer.

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