A display panel and a manufacturing method thereof, and a display device

Abstract

The present application discloses a display panel and a manufacturing method thereof, and a display device, wherein the display panel comprises: a substrate; a plurality of sub-pixels, arranged on the substrate; a pixel defining layer, arranged on the substrate, the pixel defining layer is used to define the positions of the plurality of sub-pixels; an isolation column, arranged on the pixel defining layer, the isolation structure is used to isolate the plurality of sub-pixels, the isolation column comprises a first insulating layer, a conductive layer, and a second insulating layer stacked in sequence, the cathode layers of two adjacent sub-pixels are connected through the conductive layer; a cathode auxiliary layer, arranged on the second insulating layer, the cathode auxiliary layer is connected to the conductive layer through a via hole on the second insulating layer. In the above manner, the resistance on the cathode layer can be reduced, thereby reducing the voltage drop, and thus improving the picture quality of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) has many advantages such as wide color gamut, high brightness, and high contrast, and is becoming increasingly competitive in the field of display technology.

[0003] At present, graphic evaporation is an important technology for the development of fine metal masks. However, the cathodes of R / G / B are horizontally connected through the conductive layer in the OH structure. When transmitting electrical signals, the resistance is large, which increases power consumption and generates a large voltage drop, which in turn affects the display quality of the display panel. Therefore, how to reduce the voltage drop has become an urgent problem to be solved. Summary of the invention

[0004] To solve the above problems, the present application discloses a display panel and a manufacturing method thereof, and a display device, which can reduce the resistance on the cathode layer, thereby reducing the voltage drop, and further improving the picture quality of the display panel.

[0005] The first technical solution adopted in the present application is: to provide a display panel, which includes: a substrate; a plurality of sub-pixels, arranged on the substrate; a pixel defining layer, arranged on the substrate, the pixel defining layer is used to define the positions of the plurality of sub-pixels; an isolation column, arranged on the pixel defining layer, the isolation column is used to isolate the plurality of sub-pixels, the isolation column includes a first insulating layer, a conductive layer and a second insulating layer stacked in sequence, the cathode layers of two adjacent sub-pixels are connected through the conductive layer; a cathode auxiliary layer, arranged on the second insulating layer, the cathode auxiliary layer is connected to the conductive layer through a via hole on the second insulating layer.

[0006] The conductive layer and the cathode layer are sequentially connected to form a first conductive line, the cathode auxiliary layer forms a second conductive line, and the extension direction of the first conductive line and the extension direction of the second conductive line are perpendicular to each other.

[0007] The two ends of the first conductive line are configured to receive a common signal respectively, and the two ends of the second conductive line are configured to receive a common signal respectively.

[0008] The display panel further includes: a first common signal source, connected to the first ends of multiple first wires; a second common signal source, connected to the second ends of multiple first wires; a third common signal source, connected to the first ends of multiple second wires; and a fourth common signal source, connected to the second ends of multiple second wires; wherein the first common signal source, the second common signal source, the third common signal source and the fourth common signal source are configured to provide a common signal.

[0009] The sub-pixel includes an anode layer, an organic light-emitting layer and a cathode layer which are stacked, the organic light-emitting layer overlaps the pixel defining layer and contacts the first insulating layer, and the upper surface of the organic light-emitting layer is not higher than the first insulating layer.

[0010] The display panel further includes: a first encapsulation layer, which is arranged on the sub-pixel and contacts the conductive layer and the second insulating layer; and a second encapsulation layer, which is arranged on the first encapsulation layer and the cathode auxiliary layer.

[0011] The second technical solution adopted in the present application is: to provide a method for manufacturing a display panel, which includes: providing a substrate; forming a plurality of sub-pixels, a pixel defining layer and an isolation column on the substrate, the pixel defining layer is used to define the positions of the plurality of sub-pixels, the isolation column is arranged on the pixel defining layer, the isolation structure is used to isolate the plurality of sub-pixels, the isolation column includes a first insulating layer, a conductive layer and a second insulating layer stacked in sequence, the cathode layers of two adjacent sub-pixels are connected through the conductive layer; forming a via hole on the second insulating layer; forming a cathode auxiliary layer on the second insulating layer, the cathode auxiliary layer is connected to the conductive layer through the via hole.

[0012] Among them, a plurality of sub-pixels, a pixel defining layer and an isolation column are formed on a substrate, including: forming an anode layer on a substrate; forming a pixel defining layer on a substrate; forming an isolation column on the pixel defining layer; and sequentially forming an organic light-emitting layer and a cathode layer on the anode layer, wherein the anode layer, the organic light-emitting layer and the cathode layer form sub-pixels.

[0013] The method for manufacturing the display panel further includes: forming a first encapsulation layer on the sub-pixel, the first encapsulation layer contacts the conductive layer and the second insulating layer; and forming a second encapsulation layer on the first encapsulation layer and the cathode auxiliary layer.

[0014] The third technical solution adopted in the present application is: to provide a display device, which includes the display panel as described above, or a display panel manufactured by the manufacturing method of the display panel described above.

[0015] The present application provides a display panel and a manufacturing method thereof, and a display device. The display panel includes: a substrate; a plurality of sub-pixels, arranged on the substrate; a pixel defining layer, arranged on the substrate, the pixel defining layer is used to define the positions of the plurality of sub-pixels; an isolation column, arranged on the pixel defining layer, the isolation column is used to isolate the plurality of sub-pixels, the isolation column includes a first insulating layer, a conductive layer, and a second insulating layer stacked in sequence, the cathode layers of two adjacent sub-pixels are connected through the conductive layer; a cathode auxiliary layer, arranged on the second insulating layer, the cathode auxiliary layer is connected to the conductive layer through a via hole on the second insulating layer. In the above manner, since the cathode auxiliary layer is connected to the conductive layer through the via hole on the second insulating layer, and the conductive layer is connected to the cathode layer, an additional common signal is added at both ends of the second wire, so that it forms a cathode layer connection mode of a mesh structure with the original common signal, thereby reducing the resistance of the cathode layer, thereby reducing the voltage drop of the cathode layer, and further reducing the problem of uneven brightness caused by the voltage drop; in addition, the isolation column isolates multiple sub-pixels, which can avoid the phenomenon of cross-color. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0017] Figure 1 is a schematic structural diagram of an embodiment of a display panel provided by the present application;

[0018] Figure 2 is based on Figure 1 Schematic diagram of the connection between the cathode layer and the common signal;

[0019] Figure 3 is a schematic diagram of a process for manufacturing a display panel provided in the present application;

[0020] Figure 4 It is a flowchart of a specific embodiment of a method for manufacturing a display panel provided by the present application;

[0021] Figure 5(a)-Figure 5(i) yes Figure 4 A schematic diagram of the structures corresponding to each step in the provided method for manufacturing a display panel;

[0022] Figure 6 It is a structural schematic diagram of an embodiment of a display device provided in the present application.

[0023] In the figure: display panel 100; substrate 10; pixel defining layer 30; sub-pixel 20; isolation column 40; cathode auxiliary layer 50; first insulating layer 410; conductive layer 420; second insulating layer 430; first wire 60; second wire 70; common signal VSS; anode layer 210; organic light-emitting layer 220; red light-emitting layer 220a; green light-emitting layer 220b; blue light-emitting layer 220c; cathode layer 230; first cathode layer 230a; second cathode layer 230b; third cathode layer 230c; first encapsulation layer 80; second encapsulation layer 90; third encapsulation layer 80a; fourth encapsulation layer 80b; fifth encapsulation layer 80c. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be appreciated that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the art without making creative work are within the scope of protection of the present application.

[0025] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0026] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0027] See also Figure 1 and Figure 2 , Figure 1 It is a schematic structural diagram of an embodiment of a display panel provided in the present application. Figure 2 is based on Figure 1 The display panel 100 includes a substrate 10 , a plurality of sub-pixels 20 , a pixel defining layer 30 , a spacer 40 , a cathode auxiliary layer 50 , a first encapsulation layer 80 and a second encapsulation layer 90 .

[0028] A plurality of sub-pixels 20 are arranged on a substrate 10; a pixel defining layer 30 is arranged on the substrate 10, and the pixel defining layer 30 is used to define the positions of the plurality of sub-pixels 20; an isolation column 40 is arranged on the pixel defining layer 30, and the isolation column 40 is used to isolate the plurality of sub-pixels 20, and the isolation column 40 includes a first insulating layer 410, a conductive layer 420, and a second insulating layer 430 stacked in sequence, and the cathode layers 230 of two adjacent sub-pixels 20 are connected through the conductive layer 420; the sub-pixel 20 includes an anode layer 210, an organic light-emitting layer 2 20 and the cathode layer 230, the organic light-emitting layer 220 is overlapped on the pixel defining layer 30 and contacts the first insulating layer 410, and the upper surface of the organic light-emitting layer 220 is not higher than the first insulating layer 410; the cathode auxiliary layer 50 is arranged on the second insulating layer 430, and the cathode auxiliary layer 50 is connected to the conductive layer 420 through the via hole on the second insulating layer 430; the first encapsulation layer 80 is arranged on the sub-pixel 20 and contacts the conductive layer 420 and the second insulating layer 430; the second encapsulation layer 90 is arranged on the first encapsulation layer 80 and the cathode auxiliary layer 50.

[0029] The conductive layer 420 and the cathode layer 230 are connected in sequence to form a first conductive wire 60, and the cathode auxiliary layer 50 forms a second conductive wire 70. The extension direction of the first conductive wire 60 and the extension direction of the second conductive wire 70 are perpendicular to each other. The two ends of the first conductive wire 60 are configured to receive the common signal VSS respectively, and the two ends of the second conductive wire 70 are configured to receive the common signal VSS respectively. It can be understood that since the cathode auxiliary layer 50 is connected to the conductive layer 420 through the via hole on the second insulating layer 430, the conductive layer 420 and the cathode auxiliary layer 50 can form the second conductive wire 70, and an additional common signal VSS is added to the two ends of the second conductive wire 70, so that on the basis of the common signal VSS at the two ends of the original first conductive wire 60, the driving force of the cathode signal is increased, and the cathode connection method of the formed mesh structure reduces the load of the cathode, so that the uniformity of the common signal VSS is improved, and the voltage drop is reduced.

[0030] Optionally, in one embodiment, the common signal VSS includes a first common signal source VSS1, a second common signal source VSS2, a third common signal source VSS3 and a fourth common signal source VSS4, wherein the first common signal source VSS1 is connected to the first ends of the plurality of first wires 60; the second common signal source VSS2 is connected to the second ends of the plurality of first wires 60; the third common signal source VSS3 is connected to the first ends of the plurality of second wires 70; the fourth common signal source VSS4 is connected to the second ends of the plurality of second wires 70; wherein the first common signal source VSS1, the second common signal source VSS2, the third common signal source VSS3 and the fourth common signal source VSS4 are configured to provide the common signal VSS, belonging to. In this embodiment, the third common signal source VSS3 and the fourth common signal source VSS4 are external signal sources.

[0031] Different from the prior art, the present application provides a display panel, which includes: a substrate; a plurality of sub-pixels, which are arranged on the substrate; a pixel defining layer, which is arranged on the substrate, and the pixel defining layer is used to define the positions of the plurality of sub-pixels; an isolation column, which is arranged on the pixel defining layer, and the isolation structure is used to isolate the plurality of sub-pixels, and the isolation column includes a first insulating layer, a conductive layer, and a second insulating layer which are stacked in sequence, and the cathode layers of two adjacent sub-pixels are connected through the conductive layer; a cathode auxiliary layer, which is arranged on the second insulating layer, and the cathode auxiliary layer is connected to the conductive layer through a via hole on the second insulating layer. In the above manner, since the cathode auxiliary layer is connected to the conductive layer through the via hole on the second insulating layer, and the conductive layer is connected to the cathode layer, and an additional common signal is added at both ends of the second wire, so that it forms a cathode layer connection mode of a mesh structure with the original common signal, thereby reducing the resistance of the cathode layer, thereby reducing the voltage drop of the cathode layer, and further reducing the problem of uneven brightness caused by the voltage drop; in addition, the isolation column isolates a plurality of sub-pixels, which can avoid the phenomenon of cross-color.

[0032] See also Figure 3 , Figure 3 1 is a flow chart of a method for manufacturing a display panel provided by the present invention. This embodiment provides a method for manufacturing a display panel 100, and the manufacturing method of the display panel 100 includes the following steps:

[0033] Step S301: providing a substrate.

[0034] Step S302: A plurality of sub-pixels, a pixel defining layer and an isolation column are formed on a substrate, wherein the pixel defining layer is used to define the positions of the plurality of sub-pixels, the isolation column is disposed on the pixel defining layer, the isolation structure is used to isolate the plurality of sub-pixels, the isolation column comprises a first insulating layer, a conductive layer and a second insulating layer which are sequentially stacked, and the cathode layers of two adjacent sub-pixels are connected via a conductive layer.

[0035] Step S303: forming a via hole on the second insulating layer.

[0036] Step S304: forming a cathode auxiliary layer on the second insulating layer, wherein the cathode auxiliary layer is connected to the conductive layer through a via hole.

[0037] In this embodiment, a via is formed on the second insulating layer 430, and then a cathode auxiliary layer 50 is formed, so that the cathode auxiliary layer 50 is connected to the conductive layer 420 through the via, and then a common signal VSS is added at both ends of the second conductive line 70, so that the resistance of the cathode layer 230 is reduced, thereby reducing the voltage drop.

[0038] See also Figure 4 and Figure 5(a)-Figure 5(i) , Figure 4 It is a flowchart of a specific embodiment of a method for manufacturing a display panel provided by the present application; Figure 5(a)-Figure 5(i) yes Figure 4 A schematic diagram of the structure corresponding to each step in the manufacturing method of the display panel provided. The manufacturing method specifically includes the following:

[0039] Step S401: forming an anode layer on a substrate; forming a pixel defining layer on the substrate; forming an isolation column on the pixel defining layer; the isolation column comprises a first insulating layer, a conductive layer and a second insulating layer which are sequentially stacked.

[0040] Specifically, a substrate 10 is obtained. Optionally, the substrate 10 includes a substrate and a driving circuit, and the display panel 100 is an active OLED. Optionally, the substrate 10 includes a substrate but does not include a driving circuit, and the display panel 100 is a passive OLED. Optionally, the substrate can be a thin film transistor (TFT).

[0041] Optionally, an anode layer 210 is deposited on the substrate 10, as shown in FIG5(a). The material of the anode layer 210 includes, but is not limited to, aluminum, titanium, gold, silver, copper, ITO, a combination thereof, or other suitable conductive materials. The anode layer 210 includes a first anode layer 210a, a second anode layer 210b, and a third anode layer 210c.

[0042] Optionally, a coating machine is used to coat the pixel defining layer 30 on the substrate 10, as shown in Fig. 5(b). The pixel defining layer 30 may be made of epoxy resin, phenolic resin, polyamide resin, polyimide resin, benzocyclobutene (BCB) or a combination thereof.

[0043] Optionally, after forming the first insulating layer 410 on the pixel defining layer 30, a conductive layer 420 is formed on the first insulating layer 410, and then a second insulating layer 430 is formed on the conductive layer 420, wherein the first insulating layer 410, the conductive layer 420 and the second insulating layer 430 are isolation columns 40, as shown in FIG5(c). Specifically, the first insulating layer 410 is formed on the pixel defining layer 30 by evaporation, a deposited conductive layer 420 is formed on the first insulating layer 410, and then a second insulating layer 430 is formed on the conductive layer 420. The material of the first insulating layer 410 may be an insulating inorganic material, an organic polymer material, a photoresist, and the like. The insulating material of the first insulating layer 410 is silicon nitride, silicon carbide, silicon oxide, and the like. The organic polymer material of the first insulating layer 410 is polytetrafluoroethylene, polyimide (PI), and the like. The first insulating layer 410 is used to isolate light-emitting materials of different colors, thereby avoiding color mixing. The material of the conductive layer 420 may be an organic molecule or a polymer, and the polymer material of the conductive layer 420 includes but is not limited to polyaniline. The material of the second insulating layer 430 may be an insulating inorganic material, an organic polymer material, and a photoresist. The material of the second insulating layer 430 may be the same as or different from that of the first insulating layer 410, and may be selected according to actual conditions.

[0044] Optionally, in one embodiment, the isolation column 40 may be an OH structure.

[0045] Step S402: forming an organic light-emitting layer and a cathode layer in sequence on the anode layer, the anode layer, the organic light-emitting layer and the cathode layer forming a sub-pixel, and forming a first encapsulation layer on the sub-pixel.

[0046] Two adjacent cathode layers 230 are connected via the conductive layer 420. It should be noted that when the organic light emitting layer 220 is formed, its upper surface is not higher than the first insulating layer 410 so that the first insulating layer 410 can isolate light emitting materials of different colors to avoid color mixing.

[0047] The organic light emitting layer 220 is used to emit red light, green light or blue light when powered on, and the organic light emitting layer 220 can be specifically divided into a red light emitting layer 220a, a green light emitting layer 220b and a blue light emitting layer 220c. Optionally, the cathode layer 230 is divided into a first cathode layer 230a, a second cathode layer 230b and a third cathode layer 230c; the first encapsulation layer 80 is divided into a third encapsulation layer 80a, a fourth encapsulation layer 80b and a fifth encapsulation layer 80c.

[0048] First, a red light-emitting layer 220a is formed on the first anode layer 210a, a first cathode layer 230a is formed on the red light-emitting layer 220a, and then a third encapsulation layer 80a is formed on the first cathode layer 230a, as shown in FIG5(d). Specifically, the red light-emitting layer 220a is made on the first anode layer 210a using an Array exposure and etching process, the first cathode layer 230a is formed on the red light-emitting layer 220a by evaporation, and then the third encapsulation layer 80a is formed on the first cathode layer 230a by chemical vapor deposition (CVD) to complete the encapsulation. The Array process includes thin film deposition, exposure, development, etching and stripping. It can be understood that the use of a patterned evaporation technique and the use of an Array exposure and etching process to make the red light-emitting layer 220a can save the evaporation metal mask, thereby reducing costs. In addition, the material formed by the first cathode layer 230a can be a transparent metal or metal alloy material.

[0049] Secondly, a green light-emitting layer 220b is formed on the second anode layer 210b, a second cathode layer 230b is formed on the green light-emitting layer 220b, and then a fourth encapsulation layer 80b is formed on the second cathode layer 230b, as shown in FIG5(e). Specifically, the green light-emitting layer 220b is made on the second anode layer 210b using an array exposure and etching process, the second cathode layer 230b is formed on the green light-emitting layer 220b by evaporation, and then the fourth encapsulation layer 80b is formed on the second cathode layer 230b by a CVD method to complete the encapsulation. The material forming the second cathode layer 230b may be a transparent metal or metal alloy material, etc.

[0050] Finally, a blue light-emitting layer 220c is formed on the third anode layer 210c, a third cathode layer 230c is formed on the blue light-emitting layer 220c, and a fifth encapsulation layer 80c is formed on the third cathode layer 230c, as shown in FIG5(f). Specifically, the blue light-emitting layer 220c is made on the third anode layer 210c using an array exposure and etching process, the third cathode layer 230c is formed on the blue light-emitting layer 220c by evaporation, and the fifth encapsulation layer 80c is formed on the third cathode layer 230c by CVD to complete the encapsulation. The material forming the third cathode layer 230c may be a transparent metal or metal alloy material, etc.

[0051] Step S403: forming a via hole on the second insulating layer.

[0052] Specifically, via holes are formed on the second insulating layer 430 by exposure, development, and etching, as shown in FIG. 5( g ).

[0053] Step S404: forming a cathode auxiliary layer on the second insulating layer, wherein the cathode auxiliary layer is connected to the conductive layer through a via hole.

[0054] Specifically, the cathode auxiliary layer 50 is formed in the area where the via hole is formed on the second insulating layer 430 by plating, exposure, development, and etching, so that the cathode auxiliary layer 50 can be connected to the conductive layer 420 through the via hole, as shown in FIG5(h). Optionally, the cathode auxiliary layer 50 can be formed of an alloy material or other conductive material formed by any one or more materials of aluminum, titanium, gold, silver, copper and titanium.

[0055] Step S405: forming a second encapsulation layer on the first encapsulation layer and the cathode auxiliary layer.

[0056] Specifically, TFE encapsulation is performed on the first encapsulation layer 80 and the cathode auxiliary layer 50 to form a second encapsulation layer 90 to obtain an OLED device, as shown in Figure 5(i). It can be understood that encapsulation is performed again to form the second encapsulation layer 90, so that the OLED device has good water-oxygen isolation properties and increases reliability.

[0057] See also Figure 6 , Figure 6 1 is a schematic diagram of the structure of an embodiment of a display device provided by the present application. The display device 600 includes the display panel 100 as described above, or includes the display panel 100 manufactured by the display panel manufacturing method as described above. The display panel 100 and the display panel 100 manufactured by the display panel manufacturing method are as described in the above embodiments, and will not be described in detail here.

[0058] It can be understood that the display device 600 in the embodiment of the present application is an OLED display device, which can be specifically applied to display screens of personal computers, tablet computers, mobile phones, televisions, etc., without limitation here.

[0059] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: substrate; A plurality of sub-pixels are disposed on the substrate; A pixel defining layer, disposed on the substrate, and used to define positions of a plurality of sub-pixels; An isolation column, disposed on the pixel defining layer, the isolation column is used to isolate a plurality of the sub-pixels, the isolation column comprises a first insulating layer, a conductive layer, and a second insulating layer stacked in sequence, and cathode layers of two adjacent sub-pixels are connected through the conductive layer; The cathode auxiliary layer is disposed on the second insulating layer, and the cathode auxiliary layer is connected to the conductive layer through a via hole on the second insulating layer.

2. The display panel according to claim 1, characterized in that: The conductive layer and the cathode layer are sequentially connected to form a first conductive line, and the cathode auxiliary layer forms a second conductive line. The extension direction of the first conductive line and the extension direction of the second conductive line are perpendicular to each other.

3. The display panel according to claim 2, characterized in that: Two ends of the first conductive line are configured to receive a common signal respectively, and two ends of the second conductive line are configured to receive the common signal respectively.

4. The display panel according to claim 3, characterized in that: The display panel further includes: A first common signal source connected to the first ends of the plurality of first conducting wires; A second common signal source connected to the second ends of the plurality of first conducting wires; A third common signal source connected to the first ends of the plurality of second conductive lines; a fourth common signal source connected to the second ends of the plurality of second conductive lines; The first common signal source, the second common signal source, the third common signal source and the fourth common signal source are configured to provide the common signal.

5. The display panel according to claim 1, characterized in that: The sub-pixel includes an anode layer, an organic light-emitting layer and the cathode layer which are stacked, the organic light-emitting layer overlaps the pixel defining layer and contacts the first insulating layer, and the upper surface of the organic light-emitting layer is not higher than the first insulating layer.

6. The display panel according to claim 1, characterized in that: The display panel further includes: A first encapsulation layer is disposed on the sub-pixel and contacts the conductive layer and the second insulating layer; The second packaging layer is disposed on the first packaging layer and the cathode auxiliary layer.

7. A method for manufacturing a display panel, characterized in that: The manufacturing method of the display panel includes: providing a substrate; A plurality of sub-pixels, a pixel defining layer and an isolation column are formed on the substrate, comprising: forming an anode layer on the substrate; forming a pixel defining layer on the substrate; forming an isolation column on the pixel defining layer; forming an organic light-emitting layer and a cathode layer on the anode layer in sequence, wherein the anode layer, the organic light-emitting layer and the cathode layer form the sub-pixel; wherein the pixel defining layer is used to define the positions of the plurality of sub-pixels, the isolation column is disposed on the pixel defining layer, the isolation column is used to isolate the plurality of sub-pixels, the isolation column comprises a first insulating layer, a conductive layer and a second insulating layer which are sequentially stacked, and the cathode layers of two adjacent sub-pixels are connected via the conductive layer; forming a via hole in the second insulating layer; A cathode auxiliary layer is formed on the second insulating layer, and the cathode auxiliary layer is connected to the conductive layer through the via hole.

8. The method for manufacturing a display panel according to claim 7, characterized in that: The method for manufacturing the display panel further includes: forming a first encapsulation layer on the sub-pixel, wherein the first encapsulation layer contacts the conductive layer and the second insulating layer; A second encapsulation layer is formed on the first encapsulation layer and the cathode auxiliary layer.

9. A display device, characterized in that: The display device includes the display panel according to any one of claims 1 to 6, or includes a display panel manufactured by the method for manufacturing a display panel according to any one of claims 7 or 8.

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