A microwave digitally controlled delay device chip

Abstract

The invention discloses a microwave digital control delay device chip, including a radio frequency signal input terminal, an input signal switch path selection circuit, an output signal switch path selection circuit, a delay channel circuit, a reference channel circuit and a microwave signal output terminal; the input terminal of the input signal switch path selection circuit is connected to the radio frequency signal input terminal, the output terminal of the input signal switch path selection circuit is connected to the input terminal of the reference channel circuit and the input terminal of the delay channel circuit, the output terminal of the reference channel circuit and the output terminal of the delay channel circuit are connected to the input terminal of the output signal switch path selection circuit, and the output terminal of the output signal switch path selection circuit is connected to the microwave signal output terminal; the reference channel circuit includes an amplitude and equalization adjustment circuit for adjusting the signal amplitude and the signal equalization amount, and the delay channel circuit includes a plurality of delay unit circuits connected in series. The invention has the beneficial effects of high amplitude consistency, miniaturization, high integration and low insertion loss.

Description

Technical Field

[0001] The invention belongs to the field of microwave technology, and in particular relates to a microwave digitally controlled delay device chip. Background Art

[0002] The main function of the microwave digital control delay device is to quantitatively delay the microwave radio frequency signal and compensate for the phase difference caused by different frequencies. It is a key component in electronic communication systems such as electronic countermeasure radar, digital mobile communication, microwave millimeter wave communication, etc. Common delay devices include coaxial cable delay devices, static magnetostatic wave delay devices, surface acoustic wave delay devices, etc., but they are often low in integration, large in loss, and severe in dispersion, so their scope of use is limited. In addition, the microwave transmission line structure delay device has the characteristics of high integration and wide working bandwidth, but the transmission line required for large delay is relatively long, which is not conducive to miniaturized design and application. The research on delay device chips with high amplitude consistency, miniaturization, high integration, and low insertion loss has become a hot research topic at home and abroad. Summary of the invention

[0003] The purpose of the present invention is to provide a microwave digitally controlled delay device chip with high amplitude consistency, miniaturization, high integration and low insertion loss.

[0004] In order to achieve the above-mentioned object, one aspect of the present invention provides a microwave digitally controlled delay device chip, comprising a radio frequency signal input terminal, an input signal switch path selection circuit, an output signal switch path selection circuit, a delay channel circuit, a reference channel circuit and a microwave signal output terminal;

[0005] The input end of the input signal switch path selection circuit is connected to the RF signal input end, the output end of the input signal switch path selection circuit is connected to the input end of the reference channel circuit and the input end of the delay channel circuit, the output end of the reference channel circuit and the output end of the delay channel circuit are connected to the input end of the output signal switch path selection circuit, and the output end of the output signal switch path selection circuit is connected to the microwave signal output end;

[0006] The reference channel circuit includes an amplitude and equalization amount adjustment circuit for adjusting the signal amplitude and the signal equalization amount, and the delay channel circuit includes a plurality of delay unit circuits connected in series.

[0007] Preferably, the input signal switch path selection circuit comprises a first switch device, a third switch device, a fifth switch device, a seventh switch device, a first resistor device, a third resistor device, a fifth resistor device, and a seventh resistor device;

[0008] The microwave signal input end is connected to the input ends of the third switch device and the fifth switch device, the output end of the third switch device is connected to the input end of the first switch device and the input end of the reference channel circuit, the control end of the third switch device is connected to the input end of the third resistor device, the output end of the third resistor device is connected to the first control voltage, the output end of the first switch device is connected to the ground, the control end of the first switch device is connected to the input end of the first resistor device, the output end of the first resistor device is connected to the second control voltage, the output end of the fifth switch device is connected to the input end of the seventh switch device and the input end of the delay channel circuit, the control end of the fifth switch device is connected to the input end of the fifth resistor device, the output end of the fifth resistor device is connected to the second control voltage, the output end of the seventh switch device is connected to the ground, the control end of the seventh switch device is connected to the input end of the seventh resistor device, and the output end of the seventh resistor device is connected to the first control voltage.

[0009] Preferably, the reference channel circuit comprises a ninth resistor device, a tenth resistor device, an eleventh resistor device, and a first capacitor device, and the ninth resistor device, the tenth resistor device, the eleventh resistor device, and the first capacitor device constitute an amplitude and balance adjustment circuit, wherein the ninth resistor device, the tenth resistor device, and the eleventh resistor device are used to adjust the signal amplitude, and the first capacitor device is used to adjust the signal balance amount;

[0010] The input end of the ninth resistor device serves as the input end of the reference channel circuit and is connected to the output end of the input signal switch path selection circuit. The output end of the ninth resistor device is connected to the input ends of the first capacitor device, the tenth resistor device, and the eleventh resistor device. The output end of the first capacitor device and the output end of the eleventh resistor device are connected to ground. The output end of the tenth resistor device serves as the output end of the reference channel circuit and is connected to the input end of the output signal switch path selection circuit.

[0011] Preferably, the delay channel circuit comprises a first delay unit circuit and a second delay unit circuit connected in series, the first delay unit circuit comprises a second capacitor, a first coupling coil formed by a combination of a first inductor and a second inductor, and a third capacitor, and the second delay unit circuit comprises a fourth capacitor, a second coupling coil formed by a combination of a third inductor and a fourth inductor, and a fifth capacitor;

[0012] The input end of the first inductor device serves as the input end of the delay channel circuit and the input end of the first coupling coil, the output end of the second inductor device serves as the output end of the first coupling coil, the output end of the first inductor device is connected to the input end of the second inductor device and the input end of the third capacitor device, the output end of the third capacitor device is grounded, the input end of the first coupling coil is connected to the output end of the input signal switch path selection circuit, the output end of the first coupling coil is connected to the input end of the second coupling coil, the input end of the third inductor device serves as the input end of the second coupling coil, the output end of the fourth inductor device serves as the output end of the second coupling coil, the output end of the third inductor device and the input end of the fourth inductor device are connected to the input end of the fifth capacitor device, the output end of the fifth capacitor device is grounded, and the output end of the second coupling coil serves as the output end of the delay channel circuit and is connected to the input end of the output signal switch path selection circuit.

[0013] Preferably, the output signal switch path selection circuit includes a second switch device, a fourth switch device, a sixth switch device, an eighth switch device, a second resistor device, a fourth resistor device, a sixth resistor device, and an eighth resistor device;

[0014] The microwave signal output end is connected to the input ends of the fourth switch device and the sixth switch device, the output end of the fourth switch device is connected to the input end of the second switch device and the output end of the reference channel circuit, the control end of the fourth switch device is connected to the input end of the fourth resistor device, the output end of the fourth resistor device is connected to the first control voltage, the output end of the second switch device is connected to the ground, the control end of the second switch device is connected to the input end of the second resistor device, the output end of the second resistor device is connected to the second control voltage, the output end of the sixth switch device is connected to the input end of the eighth switch device and the output end of the delay channel circuit, the control end of the sixth switch device is connected to the input end of the sixth resistor device, the output end of the sixth resistor device is connected to the second control voltage, the output end of the eighth switch device is connected to the ground, the control end of the eighth switch device is connected to the input end of the eighth resistor device, and the output end of the eighth resistor device is connected to the first control voltage.

[0015] The microwave digitally controlled delay device chip of the above aspect of the present invention has the beneficial effects of high amplitude consistency, miniaturization, high integration and low insertion loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings used in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work:

[0017] Figure 1A structural block diagram of a microwave digitally controlled delay device chip according to an embodiment of the present invention;

[0018] Figure 2 The present invention is a schematic diagram of the circuit structure of a microwave digitally controlled delay device chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] The embodiment of the present invention provides a microwave digitally controlled delay device chip. Figure 1 FIG. 1 is a block diagram of a microwave digitally controlled delay device chip according to an embodiment of the present invention. Figure 1 As shown, the microwave digitally controlled delay device chip of the embodiment of the present invention includes a radio frequency signal input terminal RFin, an input signal switch path selection circuit, an output signal switch path selection circuit, a delay channel circuit, a reference channel circuit and a microwave signal output terminal RFout.

[0021] The RF signal is input into the microwave digital controlled delay device chip from the RF signal input terminal RFin. The input terminal of the input signal switch path selection circuit is connected to the RF signal input terminal RFin, the output terminal of the input signal switch path selection circuit is connected to the input terminal of the reference channel circuit and the input terminal of the delay channel circuit, the output terminal of the reference channel circuit and the output terminal of the delay channel circuit are connected to the input terminal of the output signal switch path selection circuit, and the output terminal of the output signal switch path selection circuit is connected to the microwave signal output terminal RFout. The microwave signal is output from the microwave digital controlled delay device chip from the microwave signal output terminal RFout.

[0022] The reference channel circuit includes an amplitude and equalization adjustment circuit for adjusting the signal amplitude and the signal equalization amount, and the amplitude and equalization adjustment circuit can use different lumped parameter devices to achieve the purpose of adjusting the signal amplitude and the equalization amount. The delay channel circuit includes a plurality of (N, N ≥ 2) delay unit circuits connected in series, and the delay unit circuit can achieve the purpose of delay through different coupling coil combinations.

[0023] Figure 2 The schematic diagram of the circuit structure of a microwave digitally controlled delay device chip according to one embodiment of the present invention is shown in FIG. Figure 2In the embodiment of the present invention, the input signal switch path selection circuit includes a first switch device S1, a third switch device S3, a fifth switch device S5, a seventh switch device S7, a first resistor device R1, a third resistor device R3, a fifth resistor device R5, and a seventh resistor device R7. The microwave signal input terminal RFin is connected to the input terminals (sources) of the third switch device S3 and the fifth switch device S5, the output terminal (drain) of the third switch device S3 is connected to the input terminal (source) of the first switch device S1 and the input terminal of the reference channel circuit, the control terminal (gate) of the third switch device S3 is connected to the input terminal of the third resistor device R3, and the output terminal of the third resistor device R3 is connected to the first control voltage The output terminal (drain) of the first switch device S1 is connected to the ground, the control terminal (gate) of the first switch device S1 is connected to the input terminal of the first resistor device R1, and the output terminal of the first resistor device R1 is connected to the second control voltage The output end (drain) of the fifth switch device S5 is connected to the input end (source) of the seventh switch device S7 and the input end of the delay channel circuit, the control end (gate) of the fifth switch device S5 is connected to the input end of the fifth resistor device R5, and the output end of the fifth resistor device R5 is connected to the second control voltage The output terminal (drain) of the seventh switch device S7 is connected to the ground, the control terminal (gate) of the seventh switch device S7 is connected to the input terminal of the seventh resistor device R7, and the output terminal of the seventh resistor device R7 is connected to the first control voltage .

[0024] exist Figure 2 In the embodiment of the present invention, the reference channel circuit includes a ninth resistor device R9, a tenth resistor device R10, an eleventh resistor device R11, and a first capacitor device C1, and the ninth resistor device R9, the tenth resistor device R10, the eleventh resistor device R11, and the first capacitor device C1 constitute an amplitude and balance adjustment circuit, wherein the ninth resistor device R9, the tenth resistor device R10, and the eleventh resistor device R11 are used to adjust the signal amplitude, and the first capacitor device C1 is used to adjust the signal balance. The input end of the ninth resistor device R9 is connected to the output end of the input signal switch path selection circuit (the output end of the third switch device S3) as the input end of the reference channel circuit, the output end of the ninth resistor device R9 is connected to the input end of the first capacitor device C1, the tenth resistor device R10, and the eleventh resistor device R11, the output end of the first capacitor device C1 and the output end of the eleventh resistor device R11 are connected to the ground, and the output end of the tenth resistor device R10 is connected to the input end of the output signal switch path selection circuit as the output end of the reference channel circuit.

[0025] exist Figure 2 In the embodiment of the invention, the delay channel circuit includes two delay unit circuits connected in series (such as Figure 2 The first delay unit circuit includes a second capacitor C2, a first coupling coil CP1 formed by combining the first inductor L1 and the second inductor L2, and a third capacitor C3; the second delay unit circuit includes a fourth capacitor C4, a second coupling coil CP2 formed by combining the third inductor L3 and the fourth inductor L4, and a fifth capacitor C5.

[0026] The input end of the first inductor L1 serves as the input end of the delay channel circuit and the input end of the first coupling coil CP1, the output end of the second inductor L2 serves as the output end of the first coupling coil CP1, the output end of the first inductor L1, the input end of the second inductor L2 and the input end of the third capacitor C3 are connected, the output end of the third capacitor C3 is grounded, the input end of the first coupling coil CP1 is connected to the output end of the input signal switch path selection circuit, the output end of the first coupling coil CP1 is connected to the input end of the second coupling coil CP2, the input end of the third inductor L3 serves as the input end of the second coupling coil CP2, the output end of the fourth inductor L4 serves as the output end of the second coupling coil CP2, the output end of the third inductor L3 and the input end of the fourth inductor L4 are connected to the input end of the fifth capacitor C5, the output end of the fifth capacitor C5 is grounded, and the output end of the second coupling coil CP2 serves as the output end of the delay channel circuit and is connected to the input end of the output signal switch path selection circuit.

[0027] exist Figure 2 In the embodiment, the output signal switch path selection circuit includes a second switch device S2, a fourth switch device S4, a sixth switch device S6, an eighth switch device S8, a second resistor device R2, a fourth resistor device R4, a sixth resistor device R6, and an eighth resistor device R8. The microwave signal output terminal RFout is connected to the input terminals (sources) of the fourth switch device S4 and the sixth switch device S6, the output terminal (drain) of the fourth switch device S4 is connected to the input terminal (source) of the second switch device S2 and the output terminal of the reference channel circuit, the control terminal (gate) of the fourth switch device S4 is connected to the input terminal of the fourth resistor device R4, and the output terminal of the fourth resistor device R4 is connected to the first control voltage The output terminal (drain) of the second switch device S2 is connected to the ground, the control terminal (gate) of the second switch device S2 is connected to the input terminal of the second resistor device R2, and the output terminal of the second resistor device R2 is connected to the second control voltage The output end (drain) of the sixth switch device S6 is connected to the input end (source) of the eighth switch device S8 and the output end of the delay channel circuit, the control end (gate) of the sixth switch device S6 is connected to the input end of the sixth resistor device R6, and the output end of the sixth resistor device R6 is connected to the second control voltage The output terminal (drain) of the eighth switch device S8 is connected to the ground, the control terminal (gate) of the eighth switch device S8 is connected to the input terminal of the eighth resistor device R8, and the output terminal of the eighth resistor device R8 is connected to the first control voltage .

[0028] Compared with the prior art, the microwave digitally controlled delay device chip of the embodiment of the present invention has the following main advantages: 1. The electrical performance is greatly improved and the amplitude consistency is higher; 2. The traditional reference channel is further improved, and the channel insertion loss flatness can be adjusted by adding lumped parameter devices (capacitors, inductors, etc.) at different positions; 3. The chip size is reduced and the integration is improved.

[0029] The above description is only by way of illustration of certain exemplary embodiments of the present invention. It is undoubted that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A microwave digitally controlled delay device chip, characterized in that: It includes a radio frequency signal input terminal, an input signal switch path selection circuit, an output signal switch path selection circuit, a delay channel circuit, a reference channel circuit and a microwave signal output terminal; The input end of the input signal switch path selection circuit is connected to the RF signal input end, the output end of the input signal switch path selection circuit is connected to the input end of the reference channel circuit and the input end of the delay channel circuit, the output end of the reference channel circuit and the output end of the delay channel circuit are connected to the input end of the output signal switch path selection circuit, and the output end of the output signal switch path selection circuit is connected to the microwave signal output end; The reference channel circuit includes an amplitude and equalization amount adjustment circuit for adjusting the signal amplitude and the signal equalization amount, and the delay channel circuit includes a plurality of delay unit circuits connected in series; The reference channel circuit includes a ninth resistor device, a tenth resistor device, an eleventh resistor device, and a first capacitor device, and the ninth resistor device, the tenth resistor device, the eleventh resistor device, and the first capacitor device constitute an amplitude and balance adjustment circuit, wherein the ninth resistor device, the tenth resistor device, and the eleventh resistor device are used to adjust the signal amplitude, and the first capacitor device is used to adjust the signal balance; The input end of the ninth resistor device is connected to the output end of the input signal switch path selection circuit as the input end of the reference channel circuit, the output end of the ninth resistor device is connected to the input ends of the first capacitor device, the tenth resistor device, and the eleventh resistor device, the output end of the first capacitor device and the output end of the eleventh resistor device are connected to the ground, and the output end of the tenth resistor device is connected to the input end of the output signal switch path selection circuit as the output end of the reference channel circuit; The delay channel circuit includes a first delay unit circuit and a second delay unit circuit connected in series, the first delay unit circuit includes a second capacitor, a first coupling coil formed by a combination of a first inductor and a second inductor, and a third capacitor, and the second delay unit circuit includes a fourth capacitor, a second coupling coil formed by a combination of a third inductor and a fourth inductor, and a fifth capacitor; The input end of the first inductor device serves as the input end of the delay channel circuit and the input end of the first coupling coil, the output end of the second inductor device serves as the output end of the first coupling coil, the output end of the first inductor device is connected to the input end of the second inductor device and the input end of the third capacitor device, the output end of the third capacitor device is grounded, the input end of the first coupling coil is connected to the output end of the input signal switch path selection circuit, the output end of the first coupling coil is connected to the input end of the second coupling coil, the input end of the third inductor device serves as the input end of the second coupling coil, the output end of the fourth inductor device serves as the output end of the second coupling coil, the output end of the third inductor device and the input end of the fourth inductor device are connected to the input end of the fifth capacitor device, the output end of the fifth capacitor device is grounded, and the output end of the second coupling coil serves as the output end of the delay channel circuit and is connected to the input end of the output signal switch path selection circuit.

2. The microwave digitally controlled delay device chip according to claim 1, characterized in that: The input signal switch path selection circuit includes a first switch device, a third switch device, a fifth switch device, a seventh switch device, a first resistor device, a third resistor device, a fifth resistor device, and a seventh resistor device; The microwave signal input end is connected to the input ends of the third switch device and the fifth switch device, the output end of the third switch device is connected to the input end of the first switch device and the input end of the reference channel circuit, the control end of the third switch device is connected to the input end of the third resistor device, the output end of the third resistor device is connected to the first control voltage, the output end of the first switch device is connected to the ground, the control end of the first switch device is connected to the input end of the first resistor device, the output end of the first resistor device is connected to the second control voltage, the output end of the fifth switch device is connected to the input end of the seventh switch device and the input end of the delay channel circuit, the control end of the fifth switch device is connected to the input end of the fifth resistor device, the output end of the fifth resistor device is connected to the second control voltage, the output end of the seventh switch device is connected to the ground, the control end of the seventh switch device is connected to the input end of the seventh resistor device, and the output end of the seventh resistor device is connected to the first control voltage.

3. The microwave digitally controlled delay device chip according to claim 1 or 2, characterized in that: The output signal switch path selection circuit includes a second switch device, a fourth switch device, a sixth switch device, an eighth switch device, a second resistor device, a fourth resistor device, a sixth resistor device, and an eighth resistor device; The microwave signal output end is connected to the input ends of the fourth switch device and the sixth switch device, the output end of the fourth switch device is connected to the input end of the second switch device and the output end of the reference channel circuit, the control end of the fourth switch device is connected to the input end of the fourth resistor device, the output end of the fourth resistor device is connected to the first control voltage, the output end of the second switch device is connected to the ground, the control end of the second switch device is connected to the input end of the second resistor device, the output end of the second resistor device is connected to the second control voltage, the output end of the sixth switch device is connected to the input end of the eighth switch device and the output end of the delay channel circuit, the control end of the sixth switch device is connected to the input end of the sixth resistor device, the output end of the sixth resistor device is connected to the second control voltage, the output end of the eighth switch device is connected to the ground, the control end of the eighth switch device is connected to the input end of the eighth resistor device, and the output end of the eighth resistor device is connected to the first control voltage.

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