Processing technology matched with diffusion of monocrystalline silicon battery piece for improving efficiency of high sheet resistance

Abstract

The invention discloses a processing technology matched with diffusion of a monocrystalline silicon battery piece for high sheet resistance and efficiency improvement, and the processing technology comprises the following operation steps: placing a silicon wafer to be diffused in a diffusion furnace, heating to 780 DEG C, introducing N2 with a large size of 3000 sccm and N2 with a small size of 1000 sccm at the same time, and carrying out the low pressure pumping through a closed pipe; after the temperature is stable, the temperature of each temperature zone in the furnace is raised to 820 DEG C, meanwhile, large N2 of 2000 sccm and small N2 of 600 sccm are introduced, and the time is 300 s. According to the processing technology for improving the diffusion efficiency of the high sheet resistance matched with the monocrystalline silicon battery piece, the conversion efficiency of the battery can be effectively improved through high resistance, the impurity recombination center of the surface can be effectively reduced through the design of the high sheet resistance and the low surface shallow junction, the survival rate of surface minority carriers is improved, meanwhile, the response of short waves is increased, and therefore Isc and Uoc are effectively increased, and the diffusion efficiency of the monocrystalline silicon battery piece is improved. By matching LECO with the sintering temperature, the FF can be effectively improved while the Uoc and Isc are improved, and the purpose of improving the efficiency by 0.03% is achieved.

Description

Technical Field

[0001] The present invention relates to the field of battery cell preparation and processing, and in particular to a processing technology for matching single crystal silicon battery cells with high square resistance and efficiency improvement. Background Art

[0002] The processing technology of diffusing high square resistance to improve efficiency of battery cells is a method for preparing and processing battery cells. The junction depth of currently produced solar cells becomes shallower and the square resistance increases, which can increase its absorption of short-wave light and reduce recombination to increase the opening voltage current, while improving the uniformity of the diffused square resistance within the cell. With the continuous development of science and technology, people have higher and higher requirements for the manufacturing process of the processing technology of diffusing high square resistance to improve efficiency of battery cells.

[0003] The existing cell preparation and processing technology has certain drawbacks when used. The current boron expansion preparation methods for solar cells in the market are divided into two technical routes: single boron expansion and boron expansion + SE + oxidation. Cells of these two processes are suitable for conventional component production. At the same time, our company has also carried out large-scale production of single-boron expansion solar cells. Compared with the process of secondary boron expansion cells, the single-boron expansion of 300Ω square resistance cells is increased by about 0.056%. The original intention of the design of this technology is to cancel the SE + oxidation process, which can effectively reduce the production time and improve production efficiency. At the same time, the purpose of shortening the process time is achieved by optimizing the boron flow, nitrogen, oxygen, temperature, process time, etc. The most direct impact of adjusting the temperature, time, and boron flow is that the junction depth becomes shallower and the square resistance of the cell is increased. For this reason, we propose a processing technology that matches the high square resistance of the diffusion of monocrystalline silicon cells to improve efficiency. Summary of the invention

[0004] Technical problem to be solved: In view of the shortcomings of the prior art, the present invention provides a processing technology for matching the high square resistance of the diffusion of monocrystalline silicon solar cells to improve efficiency. The high resistance can effectively improve the battery conversion efficiency, and the design of high square resistance and low shallow junction can effectively reduce the impurity recombination center on the surface, improve the survival rate of surface minority carriers, and increase the short-wave response at the same time, thereby effectively increasing Isc and Uoc to achieve the purpose of improving efficiency. By matching LECO with the sintering temperature, while improving Uoc and Isc, FF can be effectively improved to achieve the purpose of improving efficiency by 0.03%, which can effectively solve the problems in the background technology.

[0005] Technical solution: To achieve the above purpose, the technical solution adopted by the present invention is: a processing technology for matching the diffusion of high square resistance and improving efficiency of single crystal silicon solar cells, including the following steps: S1: Place the silicon wafer to be diffused in a diffusion furnace, raise the temperature to 780°C, and simultaneously introduce 3000sccm of large N2 and 1000sccm of small N2 to close the tube and pump down the pressure; S2: After the temperature stabilizes, the temperature of each temperature zone in the furnace is raised to 820°C, and 2000 sccm of large N2 and 600 sccm of small N2 are introduced at the same time for 300 seconds, and the tube pressure is controlled at 135 mbar; S3: Continue to control the temperature of each temperature zone in the furnace at 820°C, and introduce 1200 sccm O2 and 600 sccm small N2 at the same time, temporarily do not introduce phosphorus source, the time is 180s, and the tube pressure is controlled at 135mbar; S4: Continue to control the temperature of each temperature zone in the furnace at 820°C, and simultaneously introduce 2500sccm of large N2, 550sccm of O2, 120sccm of BCl3 and 600sccm of small N2 for 210s, and control the tube pressure at 135mbar; S5: After the temperature is stabilized, the temperature of each temperature zone in the furnace is raised to 850°C, and 3000 sccm of large N2 and 600 sccm of small N2 are introduced for 60 seconds, and the tube pressure is controlled at 135 mbar; S6: Continue to control the temperature of each temperature zone in the furnace at 850°C, and simultaneously introduce 2500sccm of large N2 and 550sccm of small O2, 140sccm of BCl3 and 600sccm of small N2 for 210s, and control the tube pressure at 135mbar; S7: Continue to raise the temperature of each temperature zone in the furnace to 890°C, and simultaneously introduce 3000sccm of large N2 and 600sccm of small N2 for 1170s, and control the tube pressure at 150mbar; S8: After the temperature is stabilized, stabilize the temperature zones in the furnace to 890°C, and introduce 15000sccm of large N2 and 2000sccm of small N2 at the same time for 60s, and control the tube pressure at 900mbar; S9: Continue to raise the temperature of each temperature zone in the furnace to 1000°C, and simultaneously introduce 25000sccm of large O2 and 2000sccm of small N2 for 720s, and control the tube pressure at 900mbar; S10: Continue to raise the temperature of each temperature zone in the furnace to 1040°C, and simultaneously introduce 28000sccm of large O2 and 3000sccm of small N2 for 3600s, and control the tube pressure at 900mbar; S11: Continue to raise the temperature of each temperature zone in the furnace to 1040°C, and simultaneously introduce 2500sccm of large N2, 26000sccm of large O2, and 2000sccm of small N2 for 600s, and the tube pressure is controlled at 900mbar; S12: lower the temperature of each temperature zone in the furnace to 800°C, and introduce 2500sccm of large N2, 10000sccm of large O2 and 2000sccm of small N2 at the same time, the time is 2100s, and the tube pressure is controlled at 900mbar; S13: The temperature of each temperature zone in the furnace is lowered to 780°C, and 15000sccm of large N2 and 2000sccm of small N2 are introduced at the same time for 600s, and the tube pressure is controlled at 900mbar; S14: The temperature of each temperature zone in the furnace is lowered to 780°C, and 15000sccm of large N2 and 2000sccm of small N2 are introduced at the same time for 120s, and the tube pressure is controlled at 900mbar; S15: Continue to cool down, return the pressure, and take out the silicon wafer.

[0006] As a preferred technical solution of the present application, the S1-S15 steps adopt a high square resistance and low surface shallow junction design to reduce the surface impurity recombination centers, improve the survival rate of surface minority carriers, and increase the short-wave response, thereby effectively increasing Isc and Uoc.

[0007] As a preferred technical solution of the present application, in the steps S1-S15, LECO is matched with the sintering temperature to effectively improve FF while increasing Uoc and Isc, with the efficiency increased by 0.03%.

[0008] As a preferred technical solution of the present application, the steps S1-S15 minimize the recombination efficiency in the solar cell, optimize the emitter, optimize the metal contact ohmic resistance, minimize the series resistance, and minimize the dark current density in the emitter region.

[0009] As a preferred technical solution of the present application, in the steps S1-S15, at the same emitter concentration, the battery efficiency decreases with the increase of junction depth. When it exceeds a certain peak value, this performance decreases rapidly. This is because the higher the concentration in the emitter, the shorter the lifetime of photogenerated carriers, the greater the probability of recombination, and the current battery density decreases. The deeper the emitter junction depth, the more light is absorbed by the emitter, and the greater this impact. At the same time, as the current battery density decreases, the open circuit voltage will also decrease, so the junction depth effectively improves the battery conversion efficiency.

[0010] As a preferred technical solution of the present application, the silicon wafer to be diffused in the step S1 is a single crystal silicon wafer, and the high square resistance battery manufactured using this diffusion process has a square resistance of 350Ω.

[0011] As a preferred technical solution of the present application, a constant temperature control system is provided in the steps S1-S15, and the constant temperature control system is provided with a temperature monitoring module, a data transmission module, a data processing module, a temperature display module and a temperature constant temperature control module. The temperature monitoring module is connected to the data transmission module, the data transmission module is connected to the data processing module, and the data processing module is connected to the temperature display module and the temperature constant temperature control module.

[0012] As a preferred technical solution of the present application, the output end of the temperature monitoring module is electrically connected to the input end of the data processing module through the data transmission module, and the output end of the data processing module is electrically connected to the input end of the temperature display module and the temperature constant temperature control module.

[0013] Beneficial effects: Compared with the prior art, the present invention provides a processing technology for matching the diffusion of high square resistance of monocrystalline silicon solar cells to improve efficiency, which has the following beneficial effects: the processing technology for matching the diffusion of high square resistance of monocrystalline silicon solar cells to improve efficiency, high resistance can effectively improve the conversion efficiency of the battery, and the design of high square resistance and low surface shallow junction can effectively reduce the impurity recombination center on the surface, improve the survival rate of surface minority carriers, and increase the short-wave response at the same time, so as to effectively increase Isc and Uoc, so as to achieve the purpose of improving efficiency. By matching LECO with the sintering temperature, while improving Uoc and Isc, FF can be effectively improved, so as to achieve the purpose of improving efficiency by 0.03%; Minimize the recombination efficiency in the solar cell, optimize the emitter, optimize the metal contact ohmic resistance, and minimize the series resistance. First, optimize the emitter to minimize the dark current density in its emitter region. At the same emitter concentration, the battery efficiency decreases with the increase of junction depth. When it exceeds a certain peak value, this performance decreases rapidly. Because the higher the concentration in the emitter, the shorter the lifetime of photogenerated carriers, the greater the probability of recombination, and the lower the current battery density. The deeper the emitter junction, the more light is absorbed by the emitter, and the greater this effect. At the same time, as the current battery density decreases, the open circuit voltage will also decrease, so the junction depth can effectively improve the battery conversion efficiency; Because at the same emitter doping concentration, the front surface recombination is the largest, and the square resistance for obtaining higher battery efficiency is also larger. This is because a large square resistance corresponds to a shallow junction depth, and the shallower the emitter, the less light is absorbed by the emitter, thereby reducing the probability of photogenerated carriers being affected by the surface and recombining. Therefore, theoretically, adjusting the junction depth and surface concentration to control the size of the square resistance, such as square resistance values ​​of 380Ω, 400Ω, and 450Ω, can have a direct impact on efficiency. The entire cell diffusion high square resistance efficiency improvement process has a simple structure, is easy to operate, and has better results than traditional methods. DETAILED DESCRIPTION

[0014] A processing technology for matching the diffusion of high square resistance and improving efficiency of monocrystalline silicon solar cells, comprising the following steps: S1: Place the silicon wafer to be diffused in a diffusion furnace, raise the temperature to 780°C, and simultaneously introduce 3000sccm of large N2 and 1000sccm of small N2 to close the tube and pump down the pressure; S2: After the temperature stabilizes, the temperature of each temperature zone in the furnace is raised to 820°C, and 2000 sccm of large N2 and 600 sccm of small N2 are introduced at the same time for 300 seconds, and the tube pressure is controlled at 135 mbar; S3: Continue to control the temperature of each temperature zone in the furnace at 820°C, and introduce 1200 sccm O2 and 600 sccm small N2 at the same time, temporarily do not introduce phosphorus source, the time is 180s, and the tube pressure is controlled at 135mbar; S4: Continue to control the temperature of each temperature zone in the furnace at 820°C, and simultaneously introduce 2500sccm of large N2, 550sccm of O2, 120sccm of BCl3 and 600sccm of small N2 for 210s, and control the tube pressure at 135mbar; S5: After the temperature is stabilized, the temperature of each temperature zone in the furnace is raised to 850°C, and 3000 sccm of large N2 and 600 sccm of small N2 are introduced for 60 seconds, and the tube pressure is controlled at 135 mbar; S6: Continue to control the temperature of each temperature zone in the furnace at 850°C, and simultaneously introduce 2500sccm of large N2 and 550sccm of small O2, 140sccm of BCl3 and 600sccm of small N2 for 210s, and control the tube pressure at 135mbar; S7: Continue to raise the temperature of each temperature zone in the furnace to 890°C, and simultaneously introduce 3000sccm of large N2 and 600sccm of small N2 for 1170s, and control the tube pressure at 150mbar; S8: After the temperature is stabilized, stabilize the temperature zones in the furnace to 890°C, and introduce 15000sccm of large N2 and 2000sccm of small N2 at the same time for 60s, and control the tube pressure at 900mbar; S9: Continue to raise the temperature of each temperature zone in the furnace to 1000°C, and simultaneously introduce 25000sccm of large O2 and 2000sccm of small N2 for 720s, and control the tube pressure at 900mbar; S10: Continue to raise the temperature of each temperature zone in the furnace to 1040°C, and simultaneously introduce 28000sccm of large O2 and 3000sccm of small N2 for 3600s, and control the tube pressure at 900mbar; S11: Continue to raise the temperature of each temperature zone in the furnace to 1040°C, and simultaneously introduce 2500sccm of large N2, 26000sccm of large O2, and 2000sccm of small N2 for 600s, and the tube pressure is controlled at 900mbar; S12: lower the temperature of each temperature zone in the furnace to 800°C, and introduce 2500sccm of large N2, 10000sccm of large O2 and 2000sccm of small N2 at the same time, the time is 2100s, and the tube pressure is controlled at 900mbar; S13: The temperature of each temperature zone in the furnace is lowered to 780°C, and 15000sccm of large N2 and 2000sccm of small N2 are introduced at the same time for 600s, and the tube pressure is controlled at 900mbar; S14: The temperature of each temperature zone in the furnace is lowered to 780°C, and 15000sccm of large N2 and 2000sccm of small N2 are introduced at the same time for 120s, and the tube pressure is controlled at 900mbar; S15: Continue to cool down, return the pressure, and take out the silicon wafer.

[0015] Furthermore, a high square resistance and low surface shallow junction design is adopted in the S1-S15 steps to reduce the surface impurity recombination centers, improve the survival rate of surface minority carriers, and increase the short-wave response, thereby effectively increasing Isc and Uoc.

[0016] Furthermore, in steps S1-S15, LECO is matched with the sintering temperature to effectively improve FF while increasing Uoc and Isc, with an efficiency improvement of 0.03%.

[0017] Furthermore, in steps S1-S15, the recombination efficiency in the solar cell is minimized, the emitter is optimized, the metal contact ohmic resistance is optimized, the series resistance is minimized, and the dark current density in the emitter region is minimized.

[0018] Furthermore, in steps S1-S15, at the same emitter concentration, the battery efficiency decreases with the increase of junction depth. When it exceeds a certain peak value, this performance decreases rapidly. This is because the higher the concentration in the emitter, the shorter the lifetime of photogenerated carriers, the greater the probability of recombination, and the current battery density decreases. The deeper the emitter junction, the more light is absorbed by the emitter, and the greater this effect. At the same time, as the current battery density decreases, the open circuit voltage will also decrease. Therefore, the junction depth effectively improves the battery conversion efficiency.

[0019] Furthermore, the silicon wafer to be diffused in step S1 is a single crystal silicon wafer, and the high square resistance battery manufactured using this diffusion process has a square resistance of 350Ω.

[0020] Furthermore, a constant temperature control system is provided in steps S1-S15, and a temperature monitoring module, a data transmission module, a data processing module, a temperature display module and a temperature constant temperature control module are provided in the constant temperature control system. The temperature monitoring module is connected to the data transmission module, the data transmission module is connected to the data processing module, and the data processing module is connected to the temperature display module and the temperature constant temperature control module.

[0021] Furthermore, the output end of the temperature monitoring module is electrically connected to the input end of the data processing module through the data transmission module, and the output end of the data processing module is electrically connected to the input end of the temperature display module and the temperature constant temperature control module.

[0022] Because at the same emitter doping concentration, the front surface recombination is the largest, and the square resistance for obtaining higher battery efficiency is also larger. This is because a large square resistance corresponds to a shallow junction depth, and the shallower the emitter, the less light is absorbed by the emitter, thereby reducing the probability of photogenerated carriers being affected by the surface and recombining. Therefore, theoretically, adjusting the junction depth and surface concentration to control the size of the square resistance, such as square resistance values ​​of 380Ω, 400Ω, and 450Ω, can have a direct impact on efficiency.

[0023] 1 2 3 S1 step temperature 780℃ 750℃ 720℃ S2 step temperature 820℃ 780℃ 750℃ S3 step temperature 820℃ 780℃ 750℃ S4 step temperature 820℃ 780℃ 750℃ S5 step temperature 850℃ 810℃ 780℃ S6 step temperature 850℃ 810℃ 780℃ S7 step temperature 890℃ 840℃ 800℃ S8 step temperature 890℃ 840℃ 820℃ S9 step temperature 1000℃ 900℃ 850℃ S10 step temperature 1040℃ 920℃ 860℃ S11 step temperature 1040℃ 920℃ 860℃ S12 step temperature 800℃ 850℃ 780℃ S13 step temperature 780℃ 790℃ 740℃ S14 step temperature 780℃ 790℃ 740℃ S15 step temperature 700℃ 720℃ 710℃ efficiency 98.65% 98.20% 98.05% Working principle: The working principle of the present invention is that in a tubular diffusion furnace, BCl3 enters from the furnace during ventilation. Boron trichloride decomposes at high temperature and reacts with Si to generate elemental boron, which diffuses into the silicon matrix to form a PN junction; the diffusion is divided into two steps: pre-diffusion and redistribution. Pre-diffusion: at a lower temperature, a constant surface source diffusion method is adopted; redistribution: limited surface source diffusion is adopted, and the impurities introduced by pre-diffusion are used as diffusion sources, and diffusion is carried out at a higher concentration to control the surface concentration and diffusion depth. At the same time, a concentration gradient will be formed in the tube during this process. In order to eliminate this effect, it is necessary to continue to reduce the temperature during deposition and reduce the tube pressure control, so as to reduce the deposition of boron in the oxide layer in the front reaction zone, and at the same time increase the pre-oxygen process steps, so that more boron atoms can be more evenly diffused on the surface of the silicon wafer when passing through the oxide layer, and at the same time, the uniformity of the square resistance value can be improved. The reaction is promoted by high-temperature oxidation to ensure the depth of the PN junction, optimize the surface doping concentration, and increase the square resistance.

[0024] A single crystal silicon higher square resistance solar cell diffusion process, the specific preparation method is as follows: 1. Place the silicon wafer to be diffused in a diffusion furnace, raise the temperature to 780°C, and introduce 3000sccm of large N2 and 1000sccm of small N2 in a closed tube to pump down the pressure; 2. After the temperature stabilizes, raise the temperature of each temperature zone in the furnace to 820°C, and introduce 2000sccm of large N2 and 600sccm of small N2 at the same time for 300s, and control the tube pressure at 135mbar; 3. Continue to control the temperature of each temperature zone in the furnace at 820°C, and introduce 1200sccm O2 and 600sccm small N2 (without phosphorus source for the time being) for 180s, and control the tube pressure at 135mbar; 4. Continue to control the temperature of each temperature zone in the furnace at 820℃, and introduce 2500sccm large N2, 550sccm O2, 120sccm BCl3 and 600sccm small N2 at the same time, the time is 210s, and the tube pressure is controlled at 135mbar; 5. After the temperature stabilizes, raise the temperature of each temperature zone in the furnace to 850°C, introduce 3000sccm of large N2 and 600sccm of small N2 for 60S, and control the tube pressure at 135mbar; 6. Continue to control the temperature of each temperature zone in the furnace at 850°C, and introduce 2500sccm of large N2 and 550sccm of small O2, 140sccm of BCl3 and 600sccm of small N2 at the same time, the time is 210s, and the tube pressure is controlled at 135mbar; 7. Continue to raise the temperature of each temperature zone in the furnace to 890°C, and introduce 3000sccm of large N2 and 600sccm of small N2 at the same time for 1170s, and control the tube pressure at 150mbar; 8. After the temperature is stabilized, stabilize the temperature zones in the furnace to 890°C, and introduce 15000sccm of large N2 and 2000sccm of small N2 at the same time for 60s, and control the tube pressure at 900mbar; 9. Continue to raise the temperature of each temperature zone in the furnace to 1000°C, and at the same time introduce 25000sccm of large O2 and 2000sccm of small N2 for 720s, and control the tube pressure at 900mbar; 10. Continue to raise the temperature of each temperature zone in the furnace to 1040°C, and at the same time introduce 28000sccm of large O2 and 3000sccm of small N2 for 3600s, and control the tube pressure at 900mbar; 11. Continue to raise the temperature of each temperature zone in the furnace to 1040°C, and at the same time introduce 2500sccm of large N2, 26000sccm of large O2, and 2000sccm of small N2 for 600s, and the tube pressure is controlled at 900mbar; 12. Reduce the temperature of each temperature zone in the furnace to 800°C, and introduce 2500sccm of large N2, 10000sccm of large O2 and 2000sccm of small N2 at the same time. The time is 2100s, and the tube pressure is controlled at 900mbar; 13. The temperature of each temperature zone in the furnace was lowered to 780°C, and 15000sccm of large N2 and 2000sccm of small N2 were introduced at the same time for 600s, and the tube pressure was controlled at 900mbar; 14. Reduce the temperature of each temperature zone in the furnace to 780°C, and introduce 15000sccm of large N2 and 2000sccm of small N2 at the same time for 120s, and control the tube pressure at 900mbar; 15. Continue to cool down, return the pressure, and take out the silicon wafer.

[0025] The silicon wafer to be diffused is a single crystal silicon wafer. The high square resistance battery manufactured using this diffusion process has a square resistance of 350Ω.

[0026] It should be noted that, in this article, relational terms such as first and second (number one, number two), etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0027] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited by the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, and these changes and improvements all fall within the scope of the present invention to be protected.

Claims

1. A processing technology that matches the diffusion of high square resistance and improves efficiency of monocrystalline silicon solar cells. Features: The steps include: S1: Place the silicon wafer to be diffused in a diffusion furnace, raise the temperature to 780°C, and simultaneously introduce 3000sccm of large N2 and 1000sccm of small N2 to close the tube and pump down the pressure; S2: After the temperature stabilizes, the temperature of each temperature zone in the furnace is raised to 820°C, and 2000 sccm of large N2 and 600 sccm of small N2 are introduced at the same time for 300 seconds, and the tube pressure is controlled at 135 mbar; S3: Continue to control the temperature of each temperature zone in the furnace at 820°C, and introduce 1200 sccm O2 and 600 sccm small N2 at the same time, temporarily do not introduce phosphorus source, the time is 180s, and the tube pressure is controlled at 135mbar; S4: Continue to control the temperature of each temperature zone in the furnace at 820°C, and simultaneously introduce 2500sccm of large N2, 550sccm of O2, 120sccm of BCl3 and 600sccm of small N2 for 210s, and control the tube pressure at 135mbar; S5: After the temperature is stabilized, the temperature of each temperature zone in the furnace is raised to 850°C, and 3000 sccm of large N2 and 600 sccm of small N2 are introduced for 60 seconds, and the tube pressure is controlled at 135 mbar; S6: Continue to control the temperature of each temperature zone in the furnace at 850°C, and simultaneously introduce 2500sccm of large N2 and 550sccm of small O2, 140sccm of BCl3 and 600sccm of small N2 for 210s, and control the tube pressure at 135mbar; S7: Continue to raise the temperature of each temperature zone in the furnace to 890°C, and simultaneously introduce 3000sccm of large N2 and 600sccm of small N2 for 1170s, and control the tube pressure at 150mbar; S8: After the temperature is stabilized, stabilize the temperature zones in the furnace to 890°C, and introduce 15000sccm of large N2 and 2000sccm of small N2 at the same time for 60s, and control the tube pressure at 900mbar; S9: Continue to raise the temperature of each temperature zone in the furnace to 1000°C, and simultaneously introduce 25000sccm of large O2 and 2000sccm of small N2 for 720s, and control the tube pressure at 900mbar; S10: Continue to raise the temperature of each temperature zone in the furnace to 1040°C, and simultaneously introduce 28000sccm of large O2 and 3000sccm of small N2 for 3600s, and control the tube pressure at 900mbar; S11: Continue to raise the temperature of each temperature zone in the furnace to 1040°C, and simultaneously introduce 2500sccm of large N2, 26000sccm of large O2, and 2000sccm of small N2 for 600s, and the tube pressure is controlled at 900mbar; S12: lower the temperature of each temperature zone in the furnace to 800°C, and introduce 2500sccm of large N2, 10000sccm of large O2 and 2000sccm of small N2 at the same time, the time is 2100s, and the tube pressure is controlled at 900mbar; S13: The temperature of each temperature zone in the furnace is lowered to 780°C, and 15000sccm of large N2 and 2000sccm of small N2 are introduced at the same time for 600s, and the tube pressure is controlled at 900mbar; S14: The temperature of each temperature zone in the furnace is lowered to 780°C, and 15000sccm of large N2 and 2000sccm of small N2 are introduced at the same time for 120s, and the tube pressure is controlled at 900mbar; S15: Continue to cool down, return the pressure, and take out the silicon wafer.

2. According to claim 1, a processing technology for matching single crystal silicon cell diffusion high square resistance and improving efficiency, Features: In the S1-S15 steps, a high square resistance and low surface shallow junction design is adopted to reduce the impurity recombination center on the surface, improve the survival rate of surface minority carriers, and increase the short-wave response, thereby effectively increasing Isc and Uoc.

3. According to claim 1, a processing technology for matching single crystal silicon cell diffusion high square resistance and improving efficiency, Features: In the steps S1-S15, LECO is matched with the sintering temperature to effectively improve FF while increasing Uoc and Isc, with the efficiency increased by 0.03%.

4. According to claim 1, a processing technology for matching single crystal silicon solar cell diffusion high square resistance and improving efficiency, Features: In the steps S1-S15, the recombination efficiency in the solar cell is minimized, the emitter is optimized, the metal contact ohmic resistance is optimized, the series resistance is minimized, and the dark current density in the emitter region is minimized.

5. According to claim 1, a processing technology for matching single crystal silicon solar cell diffusion high square resistance and improving efficiency, Features: In the steps S1-S15, at the same emitter concentration, the battery efficiency decreases with the increase of junction depth. When exceeding a certain peak value, this performance decreases rapidly. This is because the higher the concentration in the emitter, the shorter the lifetime of photogenerated carriers, the greater the probability of recombination, and the current battery density decreases. The deeper the emitter junction, the more light is absorbed by the emitter, and the greater this effect. At the same time, as the current battery density decreases, the open circuit voltage will also decrease. Therefore, the junction depth effectively improves the battery conversion efficiency.

6. According to claim 1, a processing technology for matching single crystal silicon solar cell diffusion high square resistance and improving efficiency, Features: The silicon wafer to be diffused in step S1 is a single crystal silicon wafer, and the high square resistance battery manufactured using this diffusion process has a square resistance of 350Ω.

7. According to claim 1, a processing technology for matching single crystal silicon solar cell diffusion high square resistance and improving efficiency, Features: A constant temperature control system is provided in the steps S1-S15, and a temperature monitoring module, a data transmission module, a data processing module, a temperature display module and a temperature constant temperature control module are provided in the constant temperature control system. The temperature monitoring module is connected to the data transmission module, the data transmission module is connected to the data processing module, and the data processing module is connected to the temperature display module and the temperature constant temperature control module.

8. A processing technology for matching single crystal silicon solar cell diffusion high square resistance and improving efficiency according to claim 7, Features: The output end of the temperature monitoring module is electrically connected to the input end of the data processing module through the data transmission module, and the output end of the data processing module is electrically connected to the input end of the temperature display module and the temperature constant temperature control module.