Semiconductor structure and preparation method thereof
By forming a protective layer on the surface of the hard mask layer and forming a film layer through hole, the problem of residue generation of hard mask in the etching process is solved, the electrical signal conduction and device stability of semiconductor devices are improved, and the The electronic transmission efficiency and yield of integrated circuits are achieved.
Patent Information
- Application Number
- CN202310708355.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-13
- Publication Date
- 2024-12-13
AI Technical Summary
In semiconductor technology, hard masks produce non-volatile residues during the etching process, resulting in poor device stability and yield, especially at process nodes of 40nm and below, making it difficult to effectively control the characteristic size of the metal interconnect layer and profile, affecting electrical signal conduction and device reliability.
By forming a protective layer on the first surface and the second surface of the first mask layer, setting ions are injected into the mask layer using an ion implantation process to enhance oxidation resistance and wear resistance, and avoid reaction of the mask layer with the etching gas. , the residue generation is reduced, and the film layer through hole is formed in the subsequent process to expose the conductive structure.
It improves the conductivity of the metal interconnect layer, reduces void defects, improves voltage stability and device electronic transmission efficiency, and enhances the reliability and yield of the integrated circuit.
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Figure CN119133140A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art
[0002] With the development of semiconductor technology, in order to meet the requirements of integrated circuit (IC) manufacturing with higher precision and complexity, the etching of grooves and through holes in the back-end-of-the-line (BEOL) metal interconnection layer has higher and higher process structure and requirements, especially for 40nm and below process nodes. At present, hard masks are widely used in the etching process of grooves and through holes. Due to the introduction of hard masks, non-volatile residues will be generated during and after the etching process, resulting in poor stability and yield of the device. Summary of the invention
[0003] An embodiment of the present application provides a semiconductor structure, including:
[0004] a substrate comprising a conductive structure;
[0005] A stacked structure, the stacked structure comprising an etch stop layer, a first dielectric material layer, a first stress buffer layer, and a first mask layer stacked in sequence, the etch stop layer covering a side surface of the substrate;
[0006] A film layer through hole, wherein the film layer through hole penetrates the stacked structure and exposes the conductive structure;
[0007] A protection layer is located on a first surface of the first mask layer facing away from the substrate, and on a second surface of the first mask layer exposed by the film layer through hole.
[0008] In some possible implementations, the first mask layer includes a metal nitride layer, and the protective layer includes at least one of a carbon-containing metal nitride layer and a carbon-containing metal layer.
[0009] In some possible implementations, the thickness of the protective layer is between 10 angstroms and 100 angstroms.
[0010] In some possible embodiments, the membrane layer through hole includes a first part and a second part, the first part penetrates the first dielectric material layer and the etch barrier layer, the second part penetrates the first mask layer and the first stress buffer layer, and the opening size of the first part is smaller than the opening size of the second part.
[0011] In some possible implementations, the semiconductor structure further includes: a passivation layer, wherein the passivation layer is at least located on a surface of the first dielectric material layer exposed by the film layer through hole.
[0012] The present invention provides a method for preparing a semiconductor structure, comprising:
[0013] providing a substrate in which a conductive structure is formed;
[0014] forming a stacked structure, the stacked structure comprising an etch stop layer, a first dielectric material layer, a first stress buffer layer, and a first mask layer sequentially formed on the substrate;
[0015] forming a first groove, wherein the first groove extends from the first mask layer to the first dielectric material layer;
[0016] forming a protection layer, wherein the protection layer covers a first surface of the first mask layer facing away from the substrate, and covers a second surface of the first mask layer located at a sidewall of the first groove;
[0017] Using the first mask layer formed with the protective layer as a mask, the first dielectric material layer and the etching stop layer at the bottom of the first groove are etched to form a film layer through hole penetrating the first dielectric material layer and the etching stop layer, wherein the film layer through hole exposes the conductive structure.
[0018] In some possible implementations, forming a protective layer includes:
[0019] An ion implantation process is adopted to implant set ions into the first surface and the second surface of the first mask layer respectively to form the protection layer.
[0020] In some possible implementations, the step of respectively implanting set ions into the first surface and the second surface of the first mask layer includes:
[0021] A dissociation gas and a doping gas are introduced into a reaction chamber where the semiconductor structure is placed, the doping gas is used to generate the set ions, and the set ions are respectively injected into the first surface and the second surface of the first mask layer to form the protection layer.
[0022] In some possible implementations, the set ions include carbon ions, and the doping gas includes a carbon-containing gas.
[0023] In some possible implementations, after exposing the conductive structure, the method further includes: forming a passivation layer, wherein the passivation layer is at least located on a surface of the first dielectric material layer exposed by the film layer through hole.
[0024] In the embodiment of the present application, after the first surface and the second surface of the first mask layer are completely exposed, protective layers are formed on the first surface and the second surface of the first mask layer respectively, and the protective layers have better oxidation resistance, wear resistance and corrosion resistance than the first mask layer, so that the first mask layer can be protected in the etching process to avoid the first mask layer from reacting with the etching gas and reduce the generation of residues. In this way, when the metal interconnect layer is subsequently formed, the metal interconnect layer can be prevented from generating void defects, thereby improving the conduction of electrical signals, improving voltage stability, reducing the resistance of the device, and reducing the impact on the electromigration and reliability of the semiconductor structure, thereby improving the electronic transmission efficiency of the integrated circuit and improving the yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present application;
[0026] Figure 2 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0027] Figure 3 A flow chart of a preparation method provided in an embodiment of the present application;
[0028] Figure 4 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0029] Figure 5 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0030] Figure 6 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0031] Figure 7 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0032] Figure 8 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0033] Fig. 9 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0034] Fig.10 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0035] Fig.11 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0036] Fig.12 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0037] Fig.13 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0038] Fig.14 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0039] Fig.15 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0040] Fig.16 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0041] Fig.17 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0042] Fig.18 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;
[0043] Fig.19 A schematic diagram of another semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION
[0044] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. And in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in the field without creative work belong to the scope of protection of this application.
[0045] Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. "First", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and other similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
[0046] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present application. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.
[0047] With the development of semiconductor technology, in order to meet the requirements of integrated circuit manufacturing with higher precision and complexity, the groove etching of BEOL (back-end-of-the-line, BEOL) metal interconnection layer has higher and higher requirements on process structure and process structure, especially for process nodes of 40nm and below. In order to control the metal interconnection layer to have smaller feature size and better profile, the through-hole / groove integrated (All In One, AIO) etching process is widely used (previously, the 55nm process generally used the hole-first and groove-later etching process, and the AIO process currently used in the 40nm process is the groove-first and hole-later etching process and the groove-simultaneous etching process). Among them, the metal hard mask (HARD MASK, MHM) and the integrated (All In One, AIO) etching process are used to define smaller through-holes and grooves in the interconnection between copper (Cu) and low-K materials. Usually, masks are commonly used to improve the etching selectivity of low-K materials. The main reason is that low-K materials have poor mechanical properties and are easily deformed during the etching process. Metal hard masks have good adhesion to the dielectric layer and good wear resistance and corrosion resistance. Therefore, better profile (Profile) and critical dimension (CD) control can be obtained during the process preparation.
[0048] However, during the etching process, the etching gas reacts with the metal hard mask to produce residues. The residues are solid and not easily volatile, and are difficult to remove through a wet cleaning process. As a result, the residues grow over time and become dense. When a metal interconnect layer is formed in subsequent grooves and through holes, void defects are generated in the metal interconnect layer, which in turn hinders the conduction of electrical signals, reduces voltage stability, increases device resistance, and affects device electromigration and reliability.
[0049] For example, titanium nitride metal hard masks are currently commonly used to improve the etching selectivity of low-K materials. Due to the introduction of titanium nitride hard masks, non-volatile titanium fluoride compounds (TixFy) defects are generated during and after the process. Non-volatile titanium fluoride compounds (TixFy) defects are generated during and after the process.
[0050] There are two ways to form this TixFy defect, such as Figure 1As shown, during the process of integrated etching of the groove through hole of the wafer, the first surface of the first mask layer 40 made of titanium nitride (TiN) material facing away from the substrate 100 and the second surface of the first mask layer 40 located at the side wall of the groove will be oxidized by oxygen free radicals in the etching gas, thereby generating titanium oxide (TiO), and the oxide layer 401 is composed of titanium oxide (TiO). The oxide layer 401 has a lower hardness than the first mask layer 40 and is easily detached when bombarded by argon ions in the etching gas. The detached titanium oxide (TiO) will chemically react with the fluorine-containing gas in the etching gas to generate a fluorine-titanium compound (TixFy) that is difficult to remove, that is, a residue 404. For example, the defect generation reaction process is as follows: TiN+O*→TiO, TiO+CxFy→TixFy.
[0051] For example, Figure 2 As shown, after the wafer is integrated with the process of etching the recessed through hole and before entering the wet cleaning process, after the semiconductor structure completes the etching process, the residual etching gas contains fluorine-containing gas, which reacts with water molecules in the atmosphere to generate hydrogen fluoride HF, and the titanium oxide peeled off from the oxide layer 401 reacts chemically with the hydrogen fluoride HF to generate a difficult-to-remove fluorine-titanium compound (TixFy), i.e., residue 404. For example, the defect generation reaction process is as follows: CxFy+H2O→CO2+HF, HF+TiO→TixFy.
[0052] The above-mentioned fluorine titanium compound (TixFy) defects will seriously affect the electron transmission efficiency of the semiconductor structure and reduce the yield of the semiconductor structure, and greatly increase the risk of semiconductor structure breakdown during reliability testing. Therefore, how to reduce the number of fluorine titanium compound (TixFy) defects while ensuring that the profile of the etched groove is well controlled and improve the stability of the semiconductor structure and product yield is the focus of current research.
[0053] The present application provides a semiconductor structure and a preparation method thereof, which can ensure that the metal nitride is used as a hard mask, has good control over the profile and feature size of the etched groove, and at the same time enhances its antioxidant ability, corrosion resistance and wear resistance, reduces the risk of titanium metal elements combining with fluorine free radicals, reduces the generation rate of fluorine titanium compound (TixFy) defects, widens the process window, reduces voltage breakdown and improves electron transmission efficiency, and improves the interconnection performance and reliability of integrated circuits.
[0054] To this end, the present application provides a method for preparing a semiconductor structure, such as Figure 3 As shown, including:
[0055] S100 , providing a substrate, and forming a conductive structure in the substrate.
[0056] S200 , forming a stack structure, wherein the stack structure includes an etch stop layer, a first dielectric material layer, a first stress buffer layer, and a first mask layer sequentially formed on a substrate.
[0057] S300 , forming a first groove, wherein the first groove extends from the first mask layer to the first dielectric material layer.
[0058] S400 , forming a protection layer, wherein the protection layer covers a first surface of the first mask layer facing away from the substrate, and covers a second surface of the first mask layer located at a sidewall of the first groove.
[0059] S500, using the first mask layer formed with the protective layer as a mask, etching the first dielectric material layer and the etching stop layer at the bottom of the first groove to form a film layer through hole penetrating the first dielectric material layer and the etching stop layer, wherein the film layer through hole exposes the conductive structure.
[0060] The present application forms a protective layer on the first surface of the first mask layer away from the substrate and the second surface of the first mask layer located at the sidewall of the first groove, respectively, and makes the protective layer have better oxidation resistance, wear resistance and corrosion resistance than the first mask layer, so that in the etching process, the first mask layer can be protected to avoid the first mask layer from reacting with the etching gas and reduce the generation of residues. In this way, when the metal interconnection layer is subsequently formed, the metal interconnection layer can be prevented from generating void defects, thereby improving the conduction of electrical signals, improving voltage stability, reducing the resistance of the device, and reducing the impact on the electromigration and reliability of the semiconductor structure, thereby improving the electronic transmission efficiency of the integrated circuit (IC) and improving the yield.
[0061] In some embodiments of the present application, forming a protective layer may include the following process: using an ion implantation process to implant set ions into the first surface and the second surface of the first mask layer, respectively, to form a protective layer. Generally, a semiconductor structure is placed in a reaction chamber for various process preparation processes. Therefore, in an embodiment of the present application, a semiconductor structure may be placed in a reaction chamber, and an ion implantation process may be used in the reaction chamber to form a protective layer.
[0062] Exemplarily, injecting set ions into the first surface and the second surface of the first mask layer, respectively, may include the following process: introducing a dissociation gas and a doping gas into a reaction chamber in which the semiconductor structure is placed, so that the doping gas produces set ions, and injecting the set ions into the first surface and the second surface of the first mask layer, respectively, to form a protective layer.
[0063] Exemplarily, the dissociation gas is an inactive gas. Optionally, the dissociation gas includes an inert gas, such as argon, helium, etc. Exemplarily, when the dissociation gas is argon, argon ions bombard the first surface and the second surface of the first mask layer, remove impurities on the first surface and the second surface of the first mask layer, and increase the contact area between the set ions and the first surface and the second surface of the first mask layer, which is conducive to the reaction between the set ions and the first surface and the second surface of the first mask layer to generate a protective layer. Of course, the dissociation gas can also be other types of gases, which are not limited here.
[0064] Exemplarily, the reaction chamber is in an ultra-low pressure state and a high vacuum state, which is conducive to the dissociation of the doping gas to generate the set ions. Exemplarily, the vacuum degree in the reaction chamber is less than 0.1 mToor. The higher the vacuum degree, the fewer the number of gas molecules in the reaction chamber and the lower the pressure. Of course, the vacuum degree in the reaction chamber can also be set to other values, and the values can be set as needed, which is not limited here.
[0065] The present application does not limit the set ions. For example, the set ions include carbon ions. In order to form carbon ions, the doping gas may include a carbon-containing gas. Of course, the set ions may also be ions that can realize the protective layer in the present application, which is not limited here.
[0066] Since the titanium nitride mask has a high etching selectivity for low-K materials, and the titanium nitride mask has good dielectric layer adhesion, and good wear resistance and corrosion resistance, better profile (Profile) and critical dimension (CD) control can be obtained during the process preparation. In some embodiments of the present application, the material of the first mask layer includes: titanium nitride. Of course, the material of the first mask layer can also be other materials, which are not limited here.
[0067] In some embodiments of the present application, when the material of the first mask layer includes titanium nitride, carbon ions are implanted into titanium nitride to form a carbon-containing protective layer. Based on this, the material of the protective layer may include: at least one of a carbon titanium compound and a carbon-nitride titanium compound. It should be noted that the corrosion resistance, oxidation resistance and bombardment resistance of the carbon titanium compound and the carbon-nitride titanium compound are better than those of titanium nitride (TiN), so they can be used as the protective layer material of the first mask layer of titanium nitride (TiN).
[0068] In some embodiments of the present application, after exposing the conductive structure, the method further includes: forming a passivation layer, wherein the passivation layer is at least located on the surface of the first dielectric material layer exposed by the through hole of the film layer.
[0069] In some embodiments of the present application, after the conductive structure is exposed, the method further includes: forming a patterned interconnection line on the stacked structure, and filling the film layer through hole with the interconnection line to connect the interconnection line to the conductive structure. Exemplarily, the material of the interconnection line includes metal, such as aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), etc.
[0070] In some embodiments of the present application, after exposing the conductive structure and before forming the patterned interconnection lines, the process further includes: sequentially removing the protective layer, the first mask layer, the first stress buffer layer, a portion of the first dielectric material layer, and the etching stop layer.
[0071] Exemplarily, removing the first mask layer, the first stress buffer layer, and a portion of the first dielectric material layer can further thin the semiconductor structure, which is beneficial to the pursuit of ultra-thinness of the final product.
[0072] The following will be combined Figures 4 to 17 , further explain the preparation process of the semiconductor structure in detail.
[0073] like Figure 4 As shown, a substrate through hole is formed in the substrate 100 , and a conductive material is filled in the substrate through hole to form a conductive structure 110 .
[0074] Exemplarily, a suitable process can be selected from chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD) to fill the substrate through hole with a conductive material to form a conductive structure D.
[0075] Optionally, the material of the substrate includes, but is not limited to, silicon, silicon carbide, silicon germanium, multinary semiconductor materials composed of III-V group elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, multinary semiconductor materials composed of III-V group elements include InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, which are not limited here.
[0076] Optionally, the conductive material includes, but is not limited to, nickel (Ni), tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), molybdenum (Mo), etc., which are not limited here.
[0077] like Figure 5 As shown, an etching stop layer 10 , a first dielectric material layer 20 , a first stress buffer layer 30 , a first mask layer 40 , a second stress buffer layer 50 , a second mask layer 60 , and a first photoresist layer 90 are sequentially deposited on a substrate 100 by a deposition process.
[0078] Exemplarily, the material of the etching stop layer 10 includes, but is not limited to, carbon-doped silicon nitride. Of course, it may also be other materials, which are not limited here.
[0079] Exemplarily, the low-k material of the first dielectric material layer 20 includes, but is not limited to: one of silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon nitride carbon (SiCN), silicon oxynitride carbon (SiCON), silicon carbide (SiC), silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, organo-siloxane, carbon fluoride, fluorinated polyimide, or a combination thereof. Of course, the low-k material may also be set to other materials, which are not limited here.
[0080] Exemplarily, the material of the second mask layer 60 includes, but is not limited to, silicon dioxide, etc., which is not limited here.
[0081] Exemplarily, the material of the first photoresist layer 90 includes, but is not limited to, photoresist.
[0082] Exemplary deposition processes include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), and atomic layer deposition (ALD), etc., which are not limited here.
[0083] like Figure 5 As shown, the first photoresist layer 90 is patterned to form a first opening in the first photoresist layer 90 , the remaining first photoresist layer 90 covers a portion of the second mask layer 60 , and the first opening position exposes the remaining portion of the second mask layer 60 .
[0084] like Figure 6As shown, the first photoresist layer 90 is used as a mask and an etching process is adopted to etch the first mask layer 40 , the second stress buffer layer 50 and the second mask layer 60 in the first opening to form a groove penetrating the first mask layer 40 , the second stress buffer layer 50 and the second mask layer 60 .
[0085] Optionally, the groove may have any suitable aspect ratio (ie, the ratio of the depth to the width of the groove). The present application does not limit the specific value of the aspect ratio, which can be determined according to the needs of actual applications and is not limited here.
[0086] Optionally, the groove may have any suitable shape (eg, circular, rectangular). The present application does not limit the shape of the groove, which may be determined according to the requirements of actual application and is not limited here.
[0087] Exemplarily, a dry etching process may be used, such as reactive ion etching, ion beam etching, plasma etching, or any combination of these methods. Alternatively, a wet etching process may also be used.
[0088] like Figure 7 As shown, the first photoresist layer 90 is removed to completely expose the surface of the second mask layer 60. The pattern transfer layer 70, the first anti-reflection layer 80, and the second photoresist layer 95 are sequentially deposited on the second mask layer 60.
[0089] Exemplarily, the pattern transfer layer 70 is an organic dielectric layer (ODL) material. Exemplarily, the material of the pattern transfer layer 70 includes, but is not limited to, carbon-containing organic matter, which is not limited here.
[0090] Exemplarily, the materials of the first stress buffer layer 30 , the second stress buffer layer 50 , and the first anti-reflection layer 80 are dielectric anti-reflective coating (DARC) materials, including but not limited to silicon-nitrogen-carbon compounds, which are not limited here.
[0091] Exemplarily, the material of the second photoresist layer 95 includes, but is not limited to, photoresist.
[0092] like Figure 8 As shown, the second photoresist layer 95 is patterned to form a second opening in the second photoresist layer 95 , the remaining second photoresist layer 95 covers a portion of the first anti-reflection layer 80 , and the second opening position exposes the remaining portion of the first anti-reflection layer 80 .
[0093] like Fig. 9As shown, the second photoresist layer 95 is used as a mask and an etching process is adopted to etch the first anti-reflection layer 80 in the second opening to form a first film layer through hole penetrating the first anti-reflection layer 80 .
[0094] It should be noted that the orthographic projection of the groove on the substrate 100 covers the orthographic projection of the first film layer through hole on the substrate 100 .
[0095] Optionally, the first film layer through hole may have any suitable aspect ratio (ie, the ratio of the depth to the width of the first film layer through hole). The present application does not limit the specific value of the aspect ratio, which can be determined according to the needs of actual applications and is not limited here.
[0096] Optionally, the through hole of the first film layer may have any suitable shape (eg, circular, rectangular). The present application does not limit the shape of the through hole of the first film layer, which may be determined according to the requirements of actual application and is not limited here.
[0097] like Fig.10 As shown, the second photoresist layer 95 is removed, and the pattern transfer layer 70 is etched using the first anti-reflection layer 80 as a mask to form a second film layer through hole penetrating the pattern transfer layer 70 .
[0098] like Fig.11 As shown, the first anti-reflection layer 80 is removed, and the first stress buffer layer 30 and a portion of the first dielectric material layer 20 are etched using the pattern transfer layer 70 as a mask. A third film layer through hole extending from the first stress buffer layer 30 to a portion of the first dielectric material layer 20 is formed. Then, as shown in FIG. Fig.12 As shown, pattern transfer layer 70 is removed.
[0099] like Fig.13 As shown, the second mask layer 60, the second stress buffer layer 50 and the first mask layer 40 are used as masks to etch the first stress buffer layer 30 and a portion of the first dielectric material layer 20 to form a first groove extending from the first mask layer 40 to a portion of the first dielectric material layer 20, and the second mask layer 60 and the second stress buffer layer 50 are removed in sequence to completely expose the first surface of the first mask layer 40 facing away from the substrate and the second surface of the first mask layer 40 located at the sidewall of the first groove.
[0100] like Fig.14 As shown, argon gas and carbon-containing gas are introduced into a reaction chamber where the semiconductor structure is placed, so that the carbon-containing gas is dissociated to generate carbon ions, and the carbon ions are respectively injected into the first surface and the second surface of the first mask layer 40 to form a protective layer 410.
[0101] like Fig.15As shown, the first mask layer 40 formed with the protective layer 410 is used as a mask to etch the first dielectric material layer 20 and a portion of the etching stop layer 10 at the bottom of the first groove to form a fourth film layer through hole extending from the first dielectric material layer 20 to a portion of the etching stop layer 10, and further modify the opening morphology on the first dielectric material layer 20. The first dielectric material layer 20 located at the corner of the opening is mainly removed by etching to correct the shape of the opening to prevent the overhang from being easily generated at the corner position when the metal material is subsequently filled due to the small size of the opening on the first dielectric material layer 20, resulting in premature sealing when the metal material is filled, and then generating void defects in the metal interconnect structure, affecting the conductive performance.
[0102] like Fig.16 As shown, the first mask layer 40 formed with the protection layer 410 is used as a mask to further etch the etch stop layer 10 to form a fifth film layer through hole penetrating the etch stop layer 10 , exposing the conductive structure 110 .
[0103] It should be noted that the orthographic projection of the fifth film layer through hole on the substrate 100 covers the conductive structure 110 .
[0104] Illustratively, after completing the above etching process, gases such as carbon monoxide gas, carbon dioxide gas, etc. can be used to remove residues (such as carbon-containing polymers, etc.) generated during the etching process. Of course, other gases can also be used, which is not limited here.
[0105] For example, since the conductive structure 110 is exposed, the conductive structure 110 will be oxidized. For example, carbon monoxide gas can be used to reduce the oxidized conductive structure 110. Of course, other gases can also be used, which is not limited here. Fig.17 As shown, nitrogen gas, for example, may be used to form a very thin passivation layer on the exposed surfaces of the first dielectric material layer 20 , the etching stop layer 10 , and the conductive structure 110 . Of course, other gases may also be used, which is not limited here.
[0106] It should be noted that the passivation layer is very thin and has little effect on the conductivity of the semiconductor structure. The main function of the passivation layer is to protect the exposed first dielectric material layer (i.e., the low-k material layer). After the passivation layer is formed, the passivation layer above the conductive structure can be removed by etching. For example, when the material of the conductive structure is copper (Cu) and nitrogen is used for passivation treatment, copper nitride (CuN) will be formed on the surface of the conductive structure. The formed copper nitride (CuN) can be decomposed by heating to remove nitrogen in the passivation layer on the surface of the conductive structure and converted into conductive metal copper (Cu), thereby avoiding affecting the performance of the copper (Cu) interconnected conductive structure.
[0107] The embodiments of the present application provide a semiconductor structure, which is formed by using the method for preparing the semiconductor structure provided by the above embodiments.
[0108] The semiconductor structure provided by the embodiment of the present application is as follows: Fig.18 As shown, including:
[0109] A substrate 100, the substrate 100 includes a conductive structure 110;
[0110] A stacked structure 200, the stacked structure 200 comprises an etch stop layer 10, a first dielectric material layer 20, a first stress buffer layer 30, and a first mask layer 40 stacked in sequence, wherein the etch stop layer 10 covers a surface of one side of the substrate 100;
[0111] A film layer through hole 300 , wherein the film layer through hole 300 penetrates the stack structure 200 and exposes the conductive structure 110 ;
[0112] The protection layer 410 is located on the first surface of the first mask layer 40 facing away from the substrate 100 , and on the second surface of the first mask layer 40 exposed by the film layer through hole 300 .
[0113] The protective layer in the present application is located on the first surface of the first mask layer away from the substrate side and on the second surface of the first mask layer exposed by the through hole of the film layer. The protective layer has better oxidation resistance, wear resistance and corrosion resistance than the first mask layer, so that in the etching process, the first mask layer can be protected to prevent the first mask layer from reacting with the etching gas and reduce the generation of residues. In this way, when the metal interconnection layer is subsequently formed, the metal interconnection layer can be prevented from generating void defects, thereby improving the conduction of electrical signals, improving voltage stability, reducing the resistance of the device, and reducing the impact on the electromigration and reliability of the semiconductor structure, thereby improving the electronic transmission efficiency of the integrated circuit (IC) and improving the yield.
[0114] In some embodiments of the present application, Fig.18 As shown, the first mask layer 40 includes a metal nitride layer, and the protective layer 410 includes at least one of a metal carbonitride layer and a metal carbide layer.
[0115] Exemplarily, when the material of the first mask layer includes titanium nitride, carbon ions are implanted into titanium nitride to form a carbon-containing protective layer. Based on this, the material of the protective layer may include: at least one of a carbon titanium compound and a carbonitride titanium compound. It should be noted that the corrosion resistance, oxidation resistance and bombardment resistance of the carbon titanium compound and the carbonitride titanium compound are better than those of titanium nitride (TiN), so they can be used as the protective layer material of the first mask layer of titanium nitride (TiN).
[0116] Exemplarily, the thickness of the first mask layer may be between 150 angstroms and 300 angstroms. For example, the thickness of the first mask layer is 150 angstroms, 170 angstroms, 190 angstroms, 240 angstroms, 260 angstroms, 280 angstroms, 300 angstroms, and the like.
[0117] The present application does not limit the thickness of the protective layer. For example, the thickness of the protective layer can be between 10 angstroms and 100 angstroms. For example, the thickness of the protective layer is 10 angstroms, 25 angstroms, 37 angstroms, 48 angstroms, 59 angstroms, 66 angstroms, 71 angstroms, 84 angstroms, 93 angstroms, 100 angstroms, etc.
[0118] In some embodiments of the present application, Fig.18 As shown, the film layer through hole 300 includes a first part 310 and a second part 320, the first part 310 penetrates the first dielectric material layer 20 and the etch barrier layer 10, the second part 320 penetrates the first mask layer 40 and the first stress buffer layer 30, and the opening size of the first part 310 is smaller than the opening size of the second part 320.
[0119] In some embodiments of the present application, the semiconductor structure further includes: a passivation layer, the passivation layer being at least located on a surface of the first dielectric material layer exposed by the film layer through hole.
[0120] For example, the following will be combined with Fig.19 The formation process of the protective layer is further described in detail, taking the case where the material of the first mask layer is titanium nitride (TiN) as an example for explanation.
[0121] After the first surface and the second surface of the first mask layer 40 are completely exposed, argon gas and a carbon-containing gas are introduced into a reaction chamber where the semiconductor structure is placed. Argon ions Ar* dissociated from the argon gas bombard the first surface and the second surface of the first mask layer to activate and increase the dissociation rate of the carbon-containing gas. Carbon ions C* dissociated from the carbon-containing gas penetrate into the surface of the first mask layer 40 to react and replace the position of N in TiN, thereby forming a protective layer 410 made of carbon titanium compound (TiC) and\or carbon nitrogen titanium compound (Ti(C,N)).
[0122] It should be noted that the carbon-containing gas includes but is not limited to CH4, C3H8, CO, etc. The reaction chamber in which the semiconductor structure is placed is in an ultra-low pressure state and a high vacuum state, which is conducive to the dissociation of the carbon-containing gas to generate carbon ions, and in this state, the carbon ion concentration can be increased, which is more conducive to the carburizing efficiency.
[0123] In addition, a higher bias voltage is set at the machine equipment end, so as to accelerate the activation of the surface of the first mask layer by argon ions and accelerate the penetration of carbon ions generated by the dissociation of the carbon-containing gas into the surface of the first mask layer. The argon ions bombard the first surface and the second surface of the first mask layer, which can remove impurities on the first surface and the second surface of the first mask layer and increase the contact area between the first surface and the second surface of the first mask layer, which is beneficial to the reaction activity of the carbon ions and the first mask layer.
[0124] In the embodiment of the present application, when the surface of titanium nitride (TiN) is completely exposed, carbon-containing gas is dissociated to form carbon ions C* to perform carburization treatment on the surface of titanium nitride (TiN) mask layer, and C* penetrates into the surface of titanium nitride (TiN) mask layer to replace the position of nitrogen atoms to form a carbon-containing protective layer (such as TiC and\or Ti(C,N)), wherein TiC and Ti(C,N) have better oxidation resistance, wear resistance and corrosion resistance than titanium nitride (TiN), thereby preventing TiN from being oxidized by oxygen free radicals in large quantities during the process to increase the risk of reaction with fluorine-containing gas, and preventing hydrofluoric acid (HF) from corroding titanium nitride (TiN) after the process, thereby reducing the formation of fluorine titanium compound (TixFy) residue defects. In this way, when a metal interconnection layer is subsequently formed, void defects can be avoided in the metal interconnection layer, thereby improving the conduction of electrical signals, improving voltage stability, and enhancing the conductive performance of the metal interconnection layer structure.
[0125] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.
[0126] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A semiconductor structure, characterized in that: include: a substrate comprising a conductive structure; A stacked structure, the stacked structure comprising an etch stop layer, a first dielectric material layer, a first stress buffer layer, and a first mask layer stacked in sequence, the etch stop layer covering a side surface of the substrate; A film layer through hole, wherein the film layer through hole penetrates the stacked structure and exposes the conductive structure; A protection layer is located on a first surface of the first mask layer facing away from the substrate, and on a second surface of the first mask layer exposed by the film layer through hole.
2. The semiconductor structure according to claim 1, characterized in that: The first mask layer includes a metal nitride layer, and the protective layer includes at least one of a metal carbonitride layer and a metal carbide layer.
3. The semiconductor structure according to claim 2, characterized in that: The thickness of the protective layer is between 10 angstroms and 100 angstroms.
4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The membrane layer through hole includes a first part and a second part, the first part penetrates the first dielectric material layer and the etch stop layer, the second part penetrates the first mask layer and the first stress buffer layer, and the opening size of the first part is smaller than the opening size of the second part.
5. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The semiconductor structure further includes: a passivation layer, wherein the passivation layer is at least located on a surface of the first dielectric material layer exposed by the film layer through hole.
6. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate in which a conductive structure is formed; forming a stacked structure, the stacked structure comprising an etch stop layer, a first dielectric material layer, a first stress buffer layer, and a first mask layer sequentially formed on the substrate; forming a first groove, wherein the first groove extends from the first mask layer to the first dielectric material layer; forming a protection layer, wherein the protection layer covers a first surface of the first mask layer facing away from the substrate, and covers a second surface of the first mask layer located at a sidewall of the first groove; Using the first mask layer formed with the protective layer as a mask, the first dielectric material layer and the etching stop layer at the bottom of the first groove are etched to form a film layer through hole penetrating the first dielectric material layer and the etching stop layer, wherein the film layer through hole exposes the conductive structure.
7. The preparation method according to claim 6, characterized in that: The forming of the protective layer comprises: An ion implantation process is adopted to implant set ions into the first surface and the second surface of the first mask layer respectively to form the protection layer.
8. The preparation method according to claim 7, characterized in that: The step of respectively implanting set ions into the first surface and the second surface of the first mask layer comprises: A dissociation gas and a doping gas are introduced into a reaction chamber where the semiconductor structure is placed, the doping gas is used to generate the set ions, and the set ions are respectively injected into the first surface and the second surface of the first mask layer to form the protection layer.
9. The preparation method according to claim 8, characterized in that: The set ions include carbon ions, and the doping gas includes a carbon-containing gas.
10. The preparation method according to any one of claims 6 to 9, characterized in that: After the conductive structure is exposed, the method further includes: forming a passivation layer, wherein the passivation layer is at least located on the surface of the first dielectric material layer exposed by the film layer through hole.