Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a first wafer and a second wafer, and enabling the first wafer to comprise a first surface and a second surface which are opposite to each other; forming a sacrificial layer and a first metal layer surrounding the sacrificial layer on the first surface; forming an electric interconnection structure on the surfaces of the sacrificial layer and the first metal layer; after the electric interconnection structure is formed, enabling the first surface to face the second wafer to bond the first wafer and the second wafer; after the first wafer and the second wafer are mutually bonded, the first wafer is etched from the second surface, a through hole is formed in the first wafer, the bottom of the through hole exposes the surface of the sacrificial layer, the through hole has a first projection on the surface of the first wafer, the first metal layer has a second projection on the surface of the first wafer, and the first projection and the second projection are at least partially overlapped; removing the sacrificial layer exposed at the bottom of the through hole to expose a part of the first metal layer and a part of the electric interconnection structure; the conductive connection layer is formed in the through hole, so that the probability of tilting of the first metal layer is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Through-Silicon-Via (TSV) is the core technology of 3D IC packaging. It is the latest technology to interconnect chips by making vertical connections between chips and wafers. Different from the previous IC packaging bonding and stacking technology using bumps, TSV can maximize the density of chip stacking in the three-dimensional direction, minimize the size, and greatly improve the chip speed and low power consumption performance.

[0003] There is a significant difference between TSV technology and conventional packaging technology. The production of TSV can be integrated into different stages of the manufacturing process. Placing TSV in the packaging production stage is usually called Via-last. The obvious advantage of this solution is that it does not change the existing integrated circuit process and design.

[0004] However, the structural performance formed by the existing Via-last through-silicon via technology needs to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a first wafer and a second wafer bonded to each other, the first wafer including a first surface and a second surface relative to each other, and the first surface is bonded to the second wafer; a first metal layer arranged in a ring shape on the first surface; an electrical interconnection structure located on the surface of the first metal layer; a through hole located in the first wafer and extending from the second surface to the first surface, the through hole also exposing a portion of the first metal layer and a portion of the electrical interconnection structure, the through hole having a first projection on the surface of the first wafer, the first metal layer having a second projection on the surface of the first wafer, the first projection and the second projection at least partially overlapping; a conductive connection layer located in the through hole.

[0007] Optionally, it includes: an anti-diffusion layer located between the through hole and the conductive connection layer.

[0008] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a first wafer and a second wafer, the first wafer comprising a first surface and a second surface relative to each other; forming a sacrificial layer and a first metal layer surrounding the sacrificial layer on the first surface; forming an electrical interconnection structure on the surfaces of the sacrificial layer and the first metal layer; after forming the electrical interconnection structure, bonding the first wafer and the second wafer with the first surface facing the second wafer; after the first wafer and the second wafer are bonded to each other, etching the first wafer from the second surface to form a through hole in the first wafer, the bottom of the through hole exposing the surface of the sacrificial layer, the through hole having a first projection on the surface of the first wafer, the first metal layer having a second projection on the surface of the first wafer, the first projection and the second projection at least partially overlapping; removing the sacrificial layer exposed at the bottom of the through hole to expose part of the first metal layer and part of the electrical interconnection structure; forming a conductive connection layer in the through hole.

[0009] Optionally, the method for forming the sacrificial layer and the first metal layer includes: forming a first dielectric layer structure on the first surface; performing graphing on the first dielectric layer structure to form a first annular opening in the first dielectric layer structure, and the first dielectric layer structure surrounded by the first opening is the sacrificial layer; and forming the first metal layer in the first opening.

[0010] Optionally, the electrical interconnection structure includes several contact layers and a second metal layer located on the several contact layers; the method for forming the electrical interconnection structure includes: forming a second dielectric layer structure on the first dielectric layer structure, the sacrificial layer and the first metal layer; forming a second opening and several third openings located under the second opening in the second dielectric layer structure, wherein a portion of the sacrificial layer and a portion of the first metal layer are exposed at the bottom of the third opening; filling the second opening and the several third openings with conductive material to form the second metal layer in the second opening and the several contact layers in the several third openings.

[0011] Optionally, the method for forming the through hole includes: forming a hard mask layer on the second surface; etching the first wafer using the hard mask layer as a mask to form an initial through hole in the first wafer; forming a protective layer on the side wall of the initial through hole; after forming the protective layer, continuing to etch the first wafer exposed at the bottom of the initial through hole.

[0012] Optionally, the process for forming the initial through hole includes a dry etching process.

[0013] Optionally, the method for forming the protection layer includes: forming a protection material layer on the sidewall and bottom of the initial through hole; and etching back the protection material layer until the bottom surface of the initial through hole is exposed.

[0014] Optionally, the process of removing the sacrificial layer exposed at the bottom of the through hole includes one or both of a dry etching process and a wet etching process.

[0015] Optionally, the process for forming the conductive connection layer includes an electroplating process.

[0016] Optionally, before forming the conductive connection layer, an anti-diffusion layer is formed on the surface of the through hole.

[0017] Optionally, after bonding the first wafer and the second wafer to each other and before forming the through hole, the method further includes: thinning the first wafer from the second surface.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] In the semiconductor structure provided by the technical solution of the present invention, a through hole is located in the first wafer and passes through from the second surface to the first surface. The through hole also exposes part of the first metal layer and part of the electrical interconnection structure. The through hole has a first projection on the surface of the first wafer, and the first metal layer has a second projection on the surface of the first wafer. The first projection and the second projection at least partially overlap. The conductive connection layer located in the through hole and the contact area at the connection between the conductive connection layer and the first metal layer are larger, so the adhesion between the two is stronger and the contact resistance is lower, which is also beneficial to improving the electrical performance and performance stability of the chip finally formed.

[0020] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a sacrificial layer and a first metal layer surrounding the sacrificial layer are formed on the first surface, and a through hole is formed in the first wafer, the surface of the sacrificial layer is exposed at the bottom of the through hole. After the through hole is formed, the sacrificial layer exposed at the bottom of the through hole is removed to expose part of the first metal layer and part of the electrical interconnection structure, and a conductive connection layer is formed in the through hole. Since the surface of the sacrificial layer is exposed at the bottom of the through hole, the stress release process of the through hole formation reduces the probability of the first metal layer warping, improves the adhesion strength between the first metal layer and the electrical interconnection structure, and thus improves the electrical performance and performance stability of the chip finally formed; in addition, the contact surface at the connection between the conductive connection layer and the first metal layer is larger, so the adhesion between the two is stronger and the contact resistance is lower, which is also beneficial to improving the electrical performance and performance stability of the chip finally formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 3 It is a cross-sectional schematic diagram of the formation process of a semiconductor structure;

[0022] Figures 4 to 11 It is a structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0024] As the background technology, the structural performance formed by the existing through silicon via technology needs to be further improved. Now, a semiconductor structure is combined for explanation and analysis.

[0025] Figures 1 to 3 It is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0026] Please refer to Figure 1 , providing a first wafer structure and a second wafer structure bonded to each other, wherein the first wafer structure includes a first wafer 101, a first dielectric layer 102 located on the first wafer 101, and a second dielectric layer 103 located on the first dielectric layer 102, the second wafer structure includes a second wafer 201, a third dielectric layer structure 202 located on the second wafer 201, and a metal interconnection layer located in the third dielectric layer 202, the metal interconnection layer includes a first metal layer 204, a plurality of contact layers 205 located on the first metal layer 204, and a second metal layer 206 located on the plurality of contact layers 205, the second wafer 201 also has an isolation structure 203, the metal interconnection layer is located on the surface of the isolation structure 203, the second wafer 201 also includes a first surface (not shown in the figure) and a second surface (not shown in the figure) opposite to each other, the third dielectric layer structure 202 is located on the second surface, and the third dielectric layer structure 202 and the second dielectric layer 103 are bonded to each other.

[0027] Please refer to Figure 2 , forming a mask layer 207 on a portion of the first surface; using the mask layer 207 as a mask, etching the second wafer structure until the surface of the first metal layer 204 is exposed, and forming a through hole 208 in the second wafer structure.

[0028] Please refer to Figure 3 , a conductive layer 209 is formed in the through hole 208 .

[0029] In the semiconductor structure formed by the above-mentioned through silicon via process, after the through hole 208 is formed, as the stress is released during the formation of the through hole 208, the metal material layer of the first metal layer 204 at the bottom of the through hole 208 is prone to warping, causing a break between the first metal layer 204 and the contact layer 205, resulting in a short circuit, which seriously affects the electrical performance and performance stability of the chip finally formed.

[0030] In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the same, in which a conductive connection layer is formed in the through hole. Since the surface of the sacrificial layer is exposed at the bottom of the through hole, the stress release process formed by the through hole reduces the probability of the first metal layer warping, improves the adhesion strength between the first metal layer and the electrical interconnection structure, and thus improves the electrical performance and performance stability of the chip finally formed. In addition, the contact area at the connection between the conductive connection layer and the first metal layer is larger, so the adhesion between the two is stronger and the contact resistance is lower, which is also beneficial to improving the electrical performance and performance stability of the chip finally formed.

[0031] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 4 to 11 It is a structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0033] Please refer to Figure 4 , a first wafer 301 and a second wafer 400 are provided, wherein the first wafer 301 includes a first surface 300 a and a second surface 300 b opposite to each other.

[0034] In this embodiment, the second wafer 400 includes a substrate 401 and a first device region 402 located on the substrate 401 .

[0035] In this embodiment, the first wafer 301 has a second device region (not shown) and an isolation structure region 302, and the isolation structure region 302 is located on the side wall of the second device region. Subsequently, a through hole is formed in the isolation structure region 302 to reduce the impact on the second device region.

[0036] Please refer to Figure 5 and Figure 6 , Figure 5 for Figure 6 A top view of the structure. Figure 6 yes Figure 5 , a cross-sectional structural diagram along the EE1 direction, a sacrificial layer 303 and a first metal layer 304 surrounding the sacrificial layer 303 are formed on the first surface 300a.

[0037] In this embodiment, the projection of the sacrificial layer 303 on the surface of the first wafer 301 is circular. In other embodiments, the projection of the sacrificial layer on the surface of the first wafer 301 may be other shapes.

[0038] In this embodiment, the method for forming the sacrificial layer 303 and the first metal layer 304 includes: forming a first dielectric layer structure on the first surface 300a; performing a graphic processing on the first dielectric layer structure to form a first annular opening (not shown in the figure) in the first dielectric layer structure, and the first dielectric layer structure surrounded by the first opening is the sacrificial layer 303; and forming the first metal layer 304 in the first opening.

[0039] Subsequently, a through hole is formed in the first wafer 301 . In this embodiment, please refer to the position indicated by the dotted line A for the projection of the through hole on the surface of the first metal layer 304 .

[0040] In this embodiment, the first dielectric layer structure includes a first etch stop layer 305 and a first dielectric layer 306 located on the first etch stop layer 305 .

[0041] Please refer to Figure 7 , an electrical interconnection structure is formed on the surfaces of the sacrificial layer 303 and the first metal layer 304 .

[0042] In this embodiment, the electrical interconnection structure includes a plurality of contact layers 307 and a second metal layer 308 located on the plurality of contact layers 307 .

[0043] In this embodiment, the method for forming the electrical interconnection structure includes: forming a second dielectric layer structure on the first dielectric layer structure, the sacrificial layer 303 and the first metal layer 304; forming a second opening (not shown in the figure) and a plurality of third openings (not shown in the figure) located under the second opening in the second dielectric layer structure, wherein a portion of the sacrificial layer 303 and a portion of the first metal layer 304 are exposed at the bottom of the third opening; filling the second opening and the plurality of third openings with a conductive material to form the second metal layer 308 in the second opening, and forming the plurality of contact layers 307 in the plurality of third openings.

[0044] In this embodiment, the second dielectric layer structure includes a second etch stop layer 309 and a second dielectric layer 310 located on the second etch stop layer 309 .

[0045] In this embodiment, after the second metal layer 308 is formed and before the first wafer and the second wafer are bonded, a third dielectric layer 311 is further formed on the second dielectric layer 310 and the second metal layer 308 .

[0046] Please refer to Figure 8 After forming the electrical interconnection structure, the first wafer 301 and the second wafer 400 are bonded with each other with the first surface 300 a facing the second wafer.

[0047] In this embodiment, before bonding the first wafer 301 and the second wafer 400 , a fourth dielectric material layer 403 is formed on the surface of the second wafer 400 .

[0048] Please refer to Fig. 9 After the first wafer 301 and the second wafer 400 are bonded to each other, the first wafer 301 is etched from the second surface 300b to form a through hole 312 in the first wafer 301, and the bottom of the through hole 312 exposes the surface of the sacrificial layer 303, and the through hole 312 has a first projection on the surface of the first wafer 301, and the first metal layer 304 has a second projection on the surface of the first wafer 301, and the first projection and the second projection at least partially overlap.

[0049] In this embodiment, after the first wafer 301 and the second wafer 400 are bonded to each other and before the through hole 312 is formed, the process further includes: thinning the first wafer 301 from the second surface 300 b .

[0050] In this embodiment, the method for forming the through hole 312 includes: forming a hard mask layer 313 on the second surface 300b; using the hard mask layer 313 as a mask, etching the first wafer 301 to form an initial through hole (not shown in the figure) in the first wafer 301; forming a protective layer 314 on the side wall of the initial through hole; after forming the protective layer 314, continuing to etch the first wafer 301 exposed at the bottom of the initial through hole.

[0051] In this embodiment, the process for forming the initial through hole includes a dry etching process.

[0052] In this embodiment, the method for forming the protection layer 314 includes: forming a protection material layer (not shown in the figure) on the sidewall and bottom of the initial through hole; and etching back the protection material layer until the bottom surface of the initial through hole is exposed.

[0053] Please refer to Fig.10 , removing the sacrificial layer 303 exposed at the bottom of the through hole 312, so that part of the first metal layer 304 and part of the electrical interconnection structure are exposed.

[0054] Since the surface of the sacrificial layer 303 is exposed at the bottom of the through hole 312, the stress release process formed by the through hole reduces the probability of the first metal layer 304 warping, improves the adhesion strength between the first metal layer 304 and the electrical interconnection structure, and thus improves the electrical performance and performance stability of the final chip.

[0055] The process of removing the sacrificial layer 303 exposed at the bottom of the through hole 312 includes one or both of a dry etching process and a wet etching process.

[0056] In this embodiment, the process of removing the sacrificial layer 303 exposed at the bottom of the through hole 312 is a dry etching process.

[0057] Please refer to Fig.11 , a conductive connection layer 315 is formed in the through hole 312 .

[0058] In the above structure, the contact area between the conductive connection layer 315 and the first metal layer 304 is larger, so the adhesion between the two is stronger and the contact resistance is lower, which is also beneficial to improving the electrical performance and performance stability of the chip finally formed.

[0059] In this embodiment, the formation process of the conductive connection layer 315 includes an electroplating process.

[0060] In this embodiment, the material of the conductive connection layer 315 includes copper.

[0061] In this embodiment, before forming the conductive connection layer 315 , an anti-diffusion layer (not shown in the figure) is formed on the surface of the through hole 312 .

[0062] In this embodiment, the anti-diffusion layer includes an adhesive layer (not shown in the figure) and an auxiliary layer (not shown in the figure) located on the surface of the adhesive layer; the material of the adhesive layer includes tantalum; the material of the auxiliary layer includes tantalum nitride. The anti-diffusion layer is used to reduce the diffusion of copper ions into the first wafer 301, and at the same time increase the adhesion between the conductive connection layer and the through hole, and reduce the occurrence of the conductive layer falling off.

[0063] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Fig.11 , comprising: a first wafer 301 and a second wafer 400 bonded to each other, wherein the first wafer 301 comprises a first surface 300a and a second surface 300b opposite to each other, and the first surface 300a is bonded to the second wafer 400; a first metal layer 304 arranged in an annular shape on the first surface 300a; an electrical interconnection structure located on the surface of the first metal layer 304; a through hole 312 (such as a through hole 312) located in the first wafer 301 and extending from the second surface 300b to the first surface 300a Fig.11 As shown), the through hole 312 also exposes a portion of the first metal layer 304 and a portion of the electrical interconnection structure, the through hole 312 has a first projection on the surface of the first wafer 301, the first metal layer 304 has a second projection on the surface of the first wafer 301, and the first projection and the second projection at least partially overlap; a conductive connection layer 315 is located in the through hole 312.

[0064] In the semiconductor structure, the contact area between the conductive connection layer 315 and the first metal layer 304 is larger, so the adhesion between the two is stronger and the contact resistance is lower, which is also beneficial to improving the electrical performance and performance stability of the chip finally formed.

[0065] In this embodiment, the semiconductor structure further includes: an anti-diffusion layer (not shown in the figure) located between the through hole 312 and the conductive connection layer 315 .

[0066] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A first wafer and a second wafer bonded to each other, wherein the first wafer comprises a first surface and a second surface opposite to each other, and the first surface is bonded to the second wafer; A first metal layer disposed in a ring shape on the first surface; an electrical interconnection structure located on a surface of the first metal layer; a through hole located in the first wafer and extending from the second surface to the first surface, the through hole also exposing a portion of the first metal layer and a portion of the electrical interconnection structure, the through hole having a first projection on the first wafer surface, the first metal layer having a second projection on the first wafer surface, and the first projection and the second projection at least partially overlapping; A conductive connection layer is located in the through hole.

2. The semiconductor structure according to claim 1, wherein: include: An anti-diffusion layer is located between the through hole and the conductive connection layer.

3. A method for forming a semiconductor structure, characterized in that: include: Providing a first wafer and a second wafer, wherein the first wafer comprises a first side and a second side opposite to each other; forming a sacrificial layer and a first metal layer surrounding the sacrificial layer on the first surface; forming an electrical interconnection structure on the surfaces of the sacrificial layer and the first metal layer; After forming the electrical interconnection structure, bonding the first wafer to the second wafer with the first surface facing the second wafer; After the first wafer and the second wafer are bonded to each other, the first wafer is etched from the second surface to form a through hole in the first wafer, wherein the bottom of the through hole exposes the surface of the sacrificial layer, the through hole has a first projection on the surface of the first wafer, the first metal layer has a second projection on the surface of the first wafer, and the first projection and the second projection at least partially overlap; Removing the sacrificial layer exposed at the bottom of the through hole to expose a portion of the first metal layer and a portion of the electrical interconnection structure; A conductive connection layer is formed in the through hole.

4. The method for forming a semiconductor structure according to claim 3, wherein: The method for forming the sacrificial layer and the first metal layer comprises: forming a first dielectric layer structure on the first surface; performing a patterning process on the first dielectric layer structure to form a first annular opening in the first dielectric layer structure, and the first dielectric layer structure surrounded by the first opening is the sacrificial layer; The first metal layer is formed in the first opening.

5. The method for forming a semiconductor structure according to claim 4, wherein: The electrical interconnect structure includes a plurality of contact layers and a second metal layer located on the plurality of contact layers; The method for forming the electrical interconnection structure includes: forming a second dielectric layer structure on the first dielectric layer structure, the sacrificial layer and the first metal layer; forming a second opening and a plurality of third openings located below the second opening in the second dielectric layer structure, wherein a portion of the sacrificial layer and a portion of the first metal layer are exposed at the bottom of the third opening; and filling the second opening and the plurality of third openings with a conductive material to form the second metal layer in the second opening and the plurality of contact layers in the plurality of third openings.

6. The method for forming a semiconductor structure according to claim 3, wherein: The method for forming the through hole includes: forming a hard mask layer on the second surface; etching the first wafer using the hard mask layer as a mask to form an initial through hole in the first wafer; forming a protective layer on the side wall of the initial through hole; after forming the protective layer, continuing to etch the first wafer exposed at the bottom of the initial through hole.

7. The method for forming a semiconductor structure according to claim 6, wherein: The initial through hole forming process includes a dry etching process.

8. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the protection layer comprises: forming a protection material layer on the sidewall and bottom of the initial through hole; and etching back the protection material layer until the bottom surface of the initial through hole is exposed.

9. The method for forming a semiconductor structure according to claim 3, wherein: The process of removing the sacrificial layer exposed at the bottom of the through hole includes one or both of a dry etching process and a wet etching process.

10. The method for forming a semiconductor structure according to claim 3, wherein: The process of forming the conductive connection layer includes an electroplating process.

11. The method for forming a semiconductor structure according to claim 3, wherein: Before forming the conductive connection layer, an anti-diffusion layer is formed on the surface of the through hole.

12. The method for forming a semiconductor structure according to claim 3, wherein: After bonding the first wafer and the second wafer to each other and before forming the through hole, the method further includes: thinning the first wafer from the second surface.

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