Method for forming photomask and semiconductor structure

Abstract

The invention provides a method for forming a photomask and a semiconductor structure, and relates to the technical field of semiconductors. The photomask is divided into four quadrant areas along two rectangular center lines, the four quadrant areas comprise three complete shading areas and one graph area, and the graph area is provided with a 1 / 4 mark graph; the photomask is used for forming the 1 / 4 mark pattern in a unit exposure area on an intermediate layer or a wafer, and the unit exposure area comprises four chip areas distributed in a 2 * 2 array and cutting channel areas among the four chip areas; the 1 / 4 mark pattern is located in the cutting channel area. Through the photomask of which the four pattern regions are positioned in different quadrant regions, four times of exposure superposition is carried out, so that a complete mark pattern can be obtained.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for forming a photomask and a semiconductor structure. Background Art

[0002] In semiconductor manufacturing and packaging, it is sometimes necessary to form a mark pattern in the scribe line area to facilitate measurement or alignment, etc. For example, based on the mark pattern, information such as overlap, offset, and bending in the semiconductor process can be monitored, which is beneficial to improving product quality.

[0003] Currently, in the process of forming a mark pattern, due to the uncertainty of the material of the film layer to be etched, positive photoresist materials are usually used for photolithography and etching. During the multiple exposure processes of forming the mark pattern, the integrity of the mark pattern may be affected. Summary of the invention

[0004] The present disclosure provides a method for forming a photomask and a semiconductor structure, which can at least to some extent solve the problem of difficulty in forming a complete marking pattern.

[0005] According to a first aspect of the present disclosure, a photomask is provided, which is divided into four quadrants along two rectangular center lines, including three completely shading areas and one graphic area, and the graphic area has a 1 / 4 mark pattern; the photomask is used to form the 1 / 4 mark pattern in a unit exposure area on an interposer or a wafer, and the unit exposure area includes four chip areas distributed in a 2*2 array and a cutting road area between the four chip areas; the 1 / 4 mark pattern is located in the cutting road area.

[0006] Optionally, the graphic area includes a light-shielding area of ​​1 / 4 of the mark graphic and a light-transmitting area of ​​the remaining part.

[0007] Optionally, the 1 / 4 mark pattern is a 1 / 4 cross pattern composed of two rectangles, and the length of the short sides of the two rectangles is less than or equal to half the width of the cutting road area.

[0008] Optionally, the width of the cutting road area is 500-600 μm.

[0009] According to a second aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising: providing an interposer or a wafer to be packaged; the interposer or the wafer comprising one or more unit exposure areas, the unit exposure area comprising four chip areas distributed in a 2*2 array and a cutting path area between the four chip areas; providing four types of masks; the mask is divided into four quadrants along two rectangular center lines, comprising three completely shading areas and one graphic area, the graphic area having a 1 / 4 marking graphic; the graphic areas of the four types of masks are respectively located in the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant; coating a positive photoresist material on the surface of the interposer or the wafer, exposing the positive photoresist material in turn through the four types of masks, and forming a marking photoresist layer after development, the marking photoresist layer having a complete marking graphic composed of four 1 / 4 marking graphics, and the complete marking graphic is located in the cutting path area.

[0010] Optionally, after forming the marking photoresist layer, the method further includes: using the marking photoresist layer as a mask to etch the intermediate layer or the target film layer in the wafer to form the complete marking pattern; and removing the marking photoresist layer.

[0011] Optionally, the target film layer includes a redistribution layer, in which metal lines are formed, and the thickness of the metal lines is 1.5-4 μm.

[0012] Optionally, the target film layer includes a marking layer; after removing the marking photoresist layer, the method further includes: forming a redistribution layer, wherein the redistribution layer exposes the cutting path area.

[0013] Optionally, after forming the complete marking pattern in the target film layer of the interposer and forming the complete marking pattern in the target film layer of the wafer, the method further includes: bonding the interposer to the wafer while aligning the complete marking pattern in the interposer with the complete marking pattern in the wafer.

[0014] Optionally, the four types of light masks include a first light mask, a second light mask, a third light mask, and a fourth light mask; providing four types of light masks includes: providing the first light mask; rotating the first light mask clockwise or counterclockwise by 90 degrees, 180 degrees, and 270 degrees to form the second light mask, the third light mask, and the fourth light mask, respectively.

[0015] The technical solution disclosed in this disclosure has the following beneficial effects:

[0016] By providing four kinds of masks in this solution and ensuring that the graphic areas of the four kinds of masks are respectively located in the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant, four exposures are performed through the four kinds of masks respectively, and then a complete marking pattern can be formed through development processing. In addition, this solution realizes the use of positive photoresist materials and dark field masks to form a complete marking pattern, which can be coordinated with film layer etching processes of various materials, that is, this solution relaxes the restrictions on film layer materials, which is conducive to improving the selectivity of the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram showing the formation of a cross mark pattern by four exposures.

[0018] Figure 2 A schematic diagram of a photomask in this exemplary embodiment is shown.

[0019] Figure 3 A schematic diagram showing an interposer and a unit exposure region in this exemplary embodiment is shown.

[0020] Figure 4 A flow chart of a method for forming a semiconductor structure in this exemplary embodiment is shown.

[0021] Figure 5 Schematic diagrams of a first light mask, a second light mask, a third light mask, and a fourth light mask in this exemplary embodiment are shown.

[0022] FIG. 6A to FIG. 6D A schematic diagram showing the distribution of positive photoresist material that has not been irradiated in four exposures.

[0023] Figure 7 A sub-flow chart of a method for forming a semiconductor structure in this exemplary embodiment is shown. DETAILED DESCRIPTION

[0024] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings.

[0025] The accompanying drawings are schematic diagrams of the present disclosure and are not necessarily drawn to scale. The technical solution of the present disclosure can be implemented in various forms and should not be construed as being limited to the examples set forth herein. The features, structures or characteristics described in the present disclosure may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full description of the embodiments of the present disclosure. However, it will be understood by those skilled in the art that one or more specific details may be omitted when implementing the technical solution of the present disclosure, or one or more specific details may be replaced by other methods, components, structures, etc.

[0026] The inventors of the present disclosure have found that if a negative photoresist material and a bright field mask are used to expose the marking pattern, the desired marking pattern can be easily formed by superimposing multiple exposures. For example, Figure 1 A schematic diagram of forming a cross mark pattern through 4 exposures is shown. The 4 exposures use 4 masks, namely Mask A, Mask B, Mask C, and Mask D, respectively, and each has a 1 / 4 cross pattern. Each exposure causes the photoresist area of ​​1 / 4 of the cross pattern to be illuminated. After 4 exposures, the photoresist area of ​​the complete cross pattern is illuminated, and then development is performed, so that the photoresist of the cross pattern can be retained.

[0027] If positive photoresist and dark field mask are used to expose the marking pattern, for example Figure 1 The four masks shown are dark field masks, and the area of ​​1 / 4 of the cross pattern is the light-shielding area. Therefore, each exposure causes the photoresist area outside the 1 / 4 cross pattern to be illuminated. It is impossible to form a complete cross pattern by superimposing 4 exposures like negative photoresist materials and bright field masks.

[0028] In the process of forming the marking pattern, due to the uncertainty of the film material to be etched, for example, if the marking pattern is formed in the redistribution layer (RDL), the metal in the redistribution layer needs to be etched, and the thickness of the metal may reach the micron level, which is not suitable for using negative photoresist materials and bright field masks. If positive photoresist materials and dark field masks are used, the above-mentioned problem of difficulty in forming a complete marking pattern exists.

[0029] In view of the above problems, an exemplary embodiment of the present disclosure first provides a photomask. Figure 2 As shown, the mask 100 may be rectangular (including square). The mask 100 is used to expose the unit exposure area on the interposer 200 or the wafer, so the shape and size of the mask 100 correspond to the unit exposure area. For example, the mask 100 may be the same as the shape and size of the unit exposure area, or the shape and size of the mask 100 may be obtained by scaling the unit exposure area by a certain ratio. Figure 2 As shown, in the interposer 200, the unit exposure area includes four chip areas distributed in a 2*2 array and a scribe line area between the four chip areas. Generally, if the chip area is a square, the unit exposure area is a square, and the corresponding mask 110 is also a square. If the chip area is a non-square rectangle, the unit exposure area is a non-square rectangle, and the corresponding mask 110 is also a non-square rectangle.

[0030] The mask 100 is divided into four quadrants along its two rectangular center lines. A rectangular center line refers to a line connecting the midpoints of a set of opposite sides of a rectangle. There are two rectangular center lines in a rectangle, which intersect at the center point of the rectangle. The four quadrants are four rectangles of exactly the same shape and size, and can be respectively referred to as the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant. It should be understood that the present disclosure does not limit the specific locations of the four quadrants. For example, Figure 2 It is shown in the figure that the first quadrant area is located at the upper right, and the first quadrant area can also be set to be located at the upper left, lower left or lower right.

[0031] The 4 quadrants include 3 completely shading areas and 1 graphic area. Figure 1 The second quadrant, the third quadrant, and the fourth quadrant are completely shielded areas. In the exposure process, the photoresist in these three areas will not be irradiated. The first quadrant is a graphic area, which has a 1 / 4 mark graphic, for example Figure 2 The 1 / 4 mark pattern in the first quadrant is shown to be a 1 / 4 cross pattern.

[0032] In one embodiment, the graphic area may include a light-shielding area of ​​1 / 4 of the mark graphic and a light-transmitting area of ​​the remaining part, that is, the portion where the 1 / 4 mark graphic is located is the light-shielding area, and the remaining part is the light-transmitting area. In this way, the mask 100 can be used as a dark field mask and used in conjunction with a positive photoresist material.

[0033] The mask 100 corresponds to the unit exposure area, and the mask 100 includes an area corresponding to the cutting road area in the unit exposure area, and the 1 / 4 mark pattern of the pattern area can be located in the corresponding area of ​​the cutting road area. The mask 100 is used to expose the unit exposure area to form a 1 / 4 mark pattern, and the 1 / 4 mark pattern formed on the interposer 200 or the wafer is located in the cutting road area.

[0034] The marking pattern may be a four-sided symmetrical pattern, that is, the marking pattern may be divided into four 1 / 4 marking patterns having a symmetrical relationship. Figure 1 The cross pattern shown is composed of four "broken line patterns", and its size can be 90 μm*90 μm. In addition, the marking pattern can also be other similar cross patterns (such as a cross-like pattern composed of quadrilaterals or ellipses).

[0035] The marking pattern can also be divided into four quadrants, which correspond to the four quadrants of the mask 100, and each quadrant is a 1 / 4 marking pattern. If four types of masks 100 are provided, and the pattern areas are located in different quadrants, such as the pattern areas of the four types of masks 100 are located in the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant, respectively, four exposures are performed through the four types of masks 100, and the four exposures are superimposed to form a complete marking pattern.

[0036] In one embodiment, the 1 / 4 marking pattern is a 1 / 4 cross pattern consisting of two rectangles. Figure 2 and Figure 3 As shown, two rectangles intersect vertically and have one corner point overlapped, forming a 1 / 4 cross figure. The sizes of the two rectangles can be the same or different. For example, the lengths of the long sides of the two rectangles can be different. Then, in the complete cross figure formed by the four 1 / 4 cross figures, the lengths of the four sides of the cross are different. Specifically, the lengths of the two horizontal sides are different from the two vertical sides, such as the two horizontal sides are shorter and the two vertical sides are longer. That is, the length of the cross side in the "row" cutting path area is different from the length of the cross side in the "column" cutting path area. In this way, the row and column directions in the interposer 200 or the wafer can be clearly marked by the cross pattern, and when alignment is performed by the cross pattern, the 90-degree misalignment can also be avoided. For example, when the wafer and the interposer 200 need to be aligned, if the wafer is mistakenly aligned with the interposer 200 rotated 90 degrees, the long side of the cross pattern on the wafer will be aligned with the short side of the cross pattern on the interposer 200, and the short side of the cross pattern on the wafer will be aligned with the long side of the cross pattern on the interposer 200, thereby making it easy to detect the 90-degree misalignment.

[0037] In one embodiment, the short side lengths of the two rectangles of the 1 / 4 cross pattern are both less than or equal to half the width of the cutting path area. For example, the short side lengths of the two rectangles are w, which can also be called the width of the 1 / 4 mark pattern. The width of the cutting path area is a. w is less than or equal to a / 2. Thus, it can be ensured that the 1 / 4 mark pattern formed by the mask 100 is completely located in the cutting path area, and the complete mark pattern formed by the four 1 / 4 mark patterns is also located in the cutting path area.

[0038] In one embodiment, the width of the cutting road area can be 500-600 μm, and the upper limit of the width of the 1 / 4 mark pattern is 250-300 μm. This can leave a relatively ample space for the mark pattern. For example, if the width of the cutting road area is 540 μm, the mark pattern can occupy the width of the cutting road area, and the width of the 1 / 4 mark pattern is 270 μm.

[0039] Exemplary embodiments of the present disclosure also provide a method for forming a semiconductor structure. Figure 4 An exemplary process of the method is shown, which may include the following steps S410 to S430:

[0040] Step S410, providing an interposer 200 or a wafer to be packaged; the interposer 200 or the wafer includes one or more unit exposure areas, and the unit exposure area includes 4 chip areas distributed in a 2*2 array and a cutting path area between the 4 chip areas.

[0041] The interposer 200 may be an interposer 200 that is not bonded to a chip or a wafer, or an interposer 200 formed on a wafer. For example, in a packaging process, a silicon interposer may be provided, a marking pattern may be formed on the silicon interposer by the formation method of this exemplary embodiment, and then the interposer may be bonded to a chip or a wafer, and finally bonded to a packaging substrate. Alternatively, the interposer 200 may be first formed on a packaging substrate, a marking pattern may be formed on the interposer 200 by this exemplary embodiment, and then the interposer may be bonded to a chip or a wafer.

[0042] In addition, the exemplary embodiment may also form a marking pattern on the wafers to be packaged, such as forming a marking pattern on both wafers to be packaged, and then aligning the two wafers by the marking pattern to perform hybrid bonding.

[0043] In one implementation, a marking pattern may be formed on both the interposer 200 and the wafer, and the marking pattern may be used for alignment when the interposer 200 is bonded to the wafer.

[0044] Step S420, providing 4 types of masks 100; the masks 100 are divided into 4 quadrants along two rectangular center lines, including 3 completely shading areas and 1 graphic area, and the graphic area has a 1 / 4 marking graphic; the graphic areas of the 4 types of masks 100 are respectively located in the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant.

[0045] For example, the four types of masks 100 may be respectively referred to as a first mask, a second mask, a third mask, and a fourth mask. Figure 5 As shown, the graphic area of ​​the first mask is located in the first quadrant, the graphic area of ​​the second mask is located in the second quadrant, the graphic area of ​​the third mask is located in the third quadrant, and the graphic area of ​​the fourth mask is located in the fourth quadrant.

[0046] In one embodiment, since the structures of the first mask, the second mask, the third mask, and the fourth mask are substantially the same, only the distribution orientations of the graphic areas are different. The above four types of masks may include the following steps:

[0047] providing a first mask;

[0048] The first light mask is rotated clockwise or counterclockwise by 90 degrees, 180 degrees, and 270 degrees to form a second light mask, a third light mask, and a fourth light mask, respectively.

[0049] For example, based on Figure 5The orientation of the graphic area of ​​the first mask, the second mask, the third mask, and the fourth mask shown can form the second mask, the third mask, and the fourth mask by rotating the first mask counterclockwise around its center point by 90 degrees, 180 degrees, and 270 degrees, respectively. Therefore, when manufacturing the four types of masks 100, it is actually only necessary to manufacture the first mask, and the orientation thereof is changed to obtain the second mask, the third mask, and the fourth mask, which can reduce the manufacturing cost of the mask 100.

[0050] In one embodiment, the portion of the graphic area where 1 / 4 of the marking graphic is located may be a light-shielding area, and the remaining portion may be a light-transmitting area.

[0051] In step S430, a positive photoresist material is coated on the surface of the intermediate layer 200 or the wafer, and the positive photoresist material is exposed through four masks in sequence. After development, the positive photoresist material forms a marking photoresist layer, and the marking photoresist layer has a complete marking pattern composed of four 1 / 4 marking patterns, and the complete marking pattern is located in the cutting path area.

[0052] FIG. 6A to FIG. 6D The distribution of the positive photoresist material that has not been exposed after four exposures through the first mask, the second mask, the third mask, and the fourth mask is shown. After the four exposures are superimposed, the positive photoresist material that has not been exposed is distributed in the intersection area of ​​the first mask, the second mask, the third mask, and the fourth mask, and its pattern is a marking pattern. After the development process, the remaining positive photoresist material forms a marking photoresist layer, which has a complete marking pattern composed of four 1 / 4 marking patterns.

[0053] In one embodiment, if the second mask, the third mask, and the fourth mask can be formed by rotating the first mask around its center point by 90 degrees, 180 degrees, and 270 degrees, then in step S430, after coating the positive photoresist material, the first mask can be used without rotation to perform the first exposure on the positive photoresist material, and then the first mask can be rotated 90 degrees for the second exposure, and then the first mask can be rotated 180 degrees for the third exposure, and finally the first mask can be rotated 270 degrees for the fourth exposure. In this way, the manufacturing cost of the mask 100 is reduced, and in the above four exposures, the mask does not need to be replaced, but only needs to be rotated to a specific angle, which simplifies the process.

[0054] In one embodiment, the marking pattern is located at the intersection of the two cutting lanes, and more specifically, the center point of the marking pattern may coincide with the center point of the intersection of the two cutting lanes. In this way, the array distribution position on the interposer 200 or the wafer can be quickly identified by the marking pattern.

[0055] exist Figure 4In the method shown, four exposures are performed through four types of structurally symmetrical masks 100, and then a marking photoresist layer with a marking pattern can be formed through development processing, thereby realizing the use of positive photoresist materials and dark field masks to form a complete marking pattern, which can be coordinated with film layer etching processes of various materials, that is, it relaxes the restrictions on film layer materials, which is beneficial to improving the selectivity of the process.

[0056] In one embodiment, after forming the marking photoresist layer, referring to Figure 7 As shown, the method for forming a semiconductor structure may further include the following steps S710 and S720:

[0057] Step S710, using the marking photoresist layer as a mask, etching the interposer 200 or the target film layer in the wafer to form a complete marking pattern;

[0058] Step S720, removing the marking photoresist layer.

[0059] The target film layer refers to a specific film layer located below the marking photoresist layer and can be used as a marking pattern. For example, considering that the target film layer is used as a marking pattern, it should have a contrast in color or reflectivity with the cutting path area. For example, the exposed portion of the cutting path area can be a silicon substrate, and the target film layer can be a metal layer with a brighter color.

[0060] exist Figure 7 In the step, the pattern of the marking photoresist layer is transferred downward to the target film layer to form a complete marking pattern in the target film layer, which is more stable than the marking photoresist layer and is conducive to achieving a more long-term and accurate measurement or alignment effect.

[0061] It should be noted that this exemplary embodiment realizes the use of positive photoresist material and dark field mask to form a complete marking pattern. The marking photoresist layer based on the positive photoresist material can etch the target film layer of different materials to form a high-quality marking pattern, and the material selectivity of the target film layer is relatively high.

[0062] In one embodiment, the target film layer can be a redistribution layer, that is, the redistribution layer can be distributed in the chip area to form the wiring between the chip and the interposer 200, and can also be distributed in the cutting path area to form a marking pattern. The redistribution layer is generally composed of a metal wire and a dielectric layer covering the metal wire. The metal wire can be a metal such as aluminum, copper, or an alloy thereof. Since a more complex wiring needs to be set up in the redistribution layer, the thickness of the metal wire (the thickness of the metal wire at different positions in the redistribution layer may be different, and the thickness here may be the maximum thickness) is usually large, such as 1.5-4μm, so it is difficult to use a negative photoresist material to etch the redistribution layer, and the present exemplary embodiment uses a positive photoresist material, which can solve the problem of etching process. In addition, the redistribution layer realizes both the wiring and marking pattern functions, which is conducive to simplifying the process and structure and improving production efficiency.

[0063] In one embodiment, before forming the marking photoresist layer, a redistribution layer may be formed in the following manner: first, a dielectric layer is deposited, which covers the chip area and the cutting road area. Then, a structure such as a metal wire through hole is etched in the dielectric layer, such as a structure that can be formed only in the dielectric layer on the chip area. Of course, the present disclosure does not limit this, and the specific structure may be determined by the distribution of metal wires required for bonding. Then, metal wires are formed by processes such as depositing metal materials, thereby forming a redistribution layer.

[0064] In one embodiment, after forming the marking photoresist layer, a mask layer can be formed on the entire interposer 200 or the wafer, and the mask layer will cover the target film layer (such as the redistribution layer) and the marking photoresist layer. Then, the mask layer above the marking photoresist layer is removed by processes such as chemical mechanical polishing, and only the mask layer in the area without the marking photoresist layer is retained. Then, the marking photoresist layer is removed. Finally, the mask layer is used as a mask to etch the target film layer, and the hole in the shape of a complete marking pattern in the target film layer is used as a complete marking pattern, which can be used for monitoring or alignment, etc. The mask layer can be removed later, and wafer bonding can be performed through the target film layer or other structures can be formed on the target film layer.

[0065] In one embodiment, the target film layer may be a marking layer, which is a film layer specifically used to form a marking pattern, and may not be used to realize other functions, so that the material selection of the marking layer is more flexible. The marking layer may be distributed only in the cutting road area as a marking pattern, but not distributed in the chip area. Exemplarily, before forming the marking photoresist layer, the marking layer may be formed in the following manner: firstly depositing a marking layer material, which may cover the chip area and the cutting road area; then removing the marking layer material covering the chip area through photolithography and etching processes, and only retaining the marking layer material in the cutting road area, to form the marking layer. Alternatively, if the upper surface of the cutting road area is lower than the upper surface of the chip area, firstly depositing a marking layer material, which may cover the chip area and the cutting road area; then removing the marking layer material covering the chip area through processes such as chemical mechanical polishing, and only retaining the marking layer material in the cutting road area, to form the marking layer. Regardless of which method is adopted, the marking layer and the complete marking pattern formed in the marking layer are located in the cutting road area, so that the film layer in the chip area is not affected.

[0066] In one embodiment, if a complete marking pattern is formed in the marking layer, after removing the marking photoresist layer, the method for forming the semiconductor structure may further include the following steps:

[0067] A redistribution layer is formed, wherein the redistribution layer exposes the scribe line area.

[0068] That is to say, the redistribution layer can be distributed only in the chip area without occupying the scribe line area, so that the redistribution layer exposes the scribe line area and does not block the marking pattern.

[0069] Exemplarily, after removing the marking photoresist layer, a redistribution layer can be formed in the following manner: first, a dielectric layer is deposited to cover the chip area and the cutting path area; then, structures such as metal wire through holes are etched in the dielectric layer on the chip area; then, metal wires are formed by processes such as depositing metal materials, so that the metal wires are only distributed on the chip area, and there are no metal wires in the dielectric layer on the cutting path area; finally, the dielectric layer on the cutting path area is removed by processes such as photolithography and etching, and only the dielectric layer on the chip area and the metal wires therein are retained, thereby forming a redistribution layer, which exposes the cutting path area.

[0070] In one embodiment, after forming the redistribution layer, other film layers, such as a passivation layer, etc., may be further formed, and other film layers may also expose the cutting path area to avoid blocking the marking pattern. For example, after depositing the passivation layer, an opening may be formed in the passivation layer on the cutting path area, such as by removing the passivation layer on the cutting path area through processes such as photolithography and etching to expose the cutting path area. Alternatively, transparent materials may be used to form other film layers on the redistribution layer, so that there is no need to form an opening in the cutting path area, and the marking pattern in the cutting path area can be observed through the transparent film layer.

[0071] In one embodiment, after forming a complete marking pattern in the target film layer of the interposer 200 and forming a complete marking pattern in the target film layer of the wafer, the method for forming the semiconductor structure may further include the following steps:

[0072] The interposer 200 is bonded to the wafer while aligning the complete mark pattern in the interposer 200 with the complete mark pattern in the wafer.

[0073] The marking pattern in the interposer 200 is located in the cutting path area of ​​the interposer 200, and the marking pattern in the wafer is located in the cutting path area of ​​the wafer. By aligning the two parts of the marking pattern, the chip area of ​​the interposer 200 and the chip area in the wafer can be aligned, thereby achieving precise alignment of the interposer 200 and the wafer. In the aligned state, the interposer 200 and the wafer are bonded, such as the wafer can be inverted and bonded to the upper surface of the interposer 200. By aligning the marking patterns, the position error in bonding can be reduced and the packaging quality can be improved.

[0074] In one embodiment, after a complete marking pattern is formed in a first wafer to be packaged and a complete marking pattern is formed in a second wafer to be packaged, the first wafer and the second wafer can be bonded while aligning the complete marking pattern in the first wafer with the complete marking pattern in the second wafer. For example, the first wafer and the second wafer can be hybrid bonded, which can also reduce position errors in bonding and achieve precise alignment.

[0075] It should be understood that the present disclosure is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from the scope thereof. The present application is intended to cover any variation, use or adaptation of the technical solution, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the art that are not disclosed herein. The contents of the specification are to be regarded as exemplary only, and the scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A photomask, characterized in that: The mask is divided into four quadrants along two rectangular center lines, including three completely light-shielding areas and one graphic area, and the graphic area has a 1 / 4 marking pattern; The mask is used to form the 1 / 4 mark pattern in a unit exposure area on an interposer or wafer, wherein the unit exposure area includes 4 chip areas distributed in a 2*2 array and a cutting path area between the 4 chip areas; the 1 / 4 mark pattern is located in the cutting path area.

2. The photomask according to claim 1, wherein: The graphic area includes a light-shielding area of ​​1 / 4 of the mark graphic and a light-transmitting area of ​​the remaining part.

3. The photomask according to claim 1 or 2, characterized in that: The 1 / 4 mark pattern is a 1 / 4 cross pattern composed of two rectangles, and the length of the short sides of the two rectangles is less than or equal to half of the width of the cutting road area.

4. The photomask according to claim 1 or 2, wherein: The width of the cutting road area is 500-600 μm.

5. A method for forming a semiconductor structure, characterized in that: include: Providing an interposer or a wafer to be packaged; the interposer or the wafer comprises one or more unit exposure areas, the unit exposure area comprising four chip areas distributed in a 2*2 array and a dicing road area between the four chip areas; Four kinds of masks are provided; the masks are divided into four quadrants along two rectangular center lines, including three completely light-shielding areas and one graphic area, and the graphic area has a 1 / 4 marking pattern; the graphic areas of the four kinds of masks are respectively located in the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant; A positive photoresist material is coated on the surface of the intermediate layer or the wafer, and the positive photoresist material is exposed through the four masks in sequence. After development, the positive photoresist material forms a marking photoresist layer, and the marking photoresist layer has a complete marking pattern composed of four 1 / 4 marking patterns, and the complete marking pattern is located in the cutting path area.

6. The method according to claim 5, characterized in that After forming the marking photoresist layer, the method further comprises: Using the marking photoresist layer as a mask, etching the target film layer in the interposer or the wafer to form the complete marking pattern; The marking photoresist layer is removed.

7. The method according to claim 6, characterized in that The target film layer includes a redistribution layer, in which metal lines are formed, and the thickness of the metal lines is 1.5-4 μm.

8. The method according to claim 6, characterized in that The target film layer includes a marking layer; after removing the marking photoresist layer, the method further includes: A redistribution layer is formed, wherein the redistribution layer exposes the scribe line area.

9. The method according to any one of claims 6 to 8, characterized in that: After forming the complete mark pattern in the target film layer of the interposer and forming the complete mark pattern in the target film layer of the wafer, the method further includes: The interposer is bonded to the wafer while aligning the complete mark pattern in the interposer with the complete mark pattern in the wafer.

10. The method according to any one of claims 5 to 8, characterized in that: The four types of light masks include a first light mask, a second light mask, a third light mask, and a fourth light mask; There are 4 types of masks provided, including: providing the first photomask; The first light mask is rotated clockwise or counterclockwise by 90 degrees, 180 degrees, and 270 degrees to form the second light mask, the third light mask, and the fourth light mask, respectively.

Images