Semiconductor device

By adopting an oxide semiconductor layer and a multi-layer insulating layer structure in a semiconductor device, the configuration of the conductive layer and insulating layer is optimized, and combined with the back gate structure, the problems of large on-state current, small parasitic capacitance and miniaturization in the prior art are solved. , realizes high-efficiency and low-power storage devices.

CN119277781APending Publication Date: 2025-01-07SEMICON ENERGY LAB CO LTD
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Patent Information

Application Number
CN202410883463.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Priority Date
2023-08-10
Filing Date
2024-07-03
Publication Date
2025-01-07

AI Technical Summary

Technical Problem

While achieving high density and low power consumption, existing semiconductor devices are difficult to take into account the needs of large on-state current, small parasitic capacitance and miniaturization, and the read and write speed and reliability of the storage device are insufficient.

Method used

Design of semiconductor device with an oxide semiconductor layer and a multi-layer insulating layer structure, in which the oxide semiconductor layer overlaps the multi-layer insulating layer and the conductive layer. By optimizing the configuration of the conductive layer and insulating layer, parasitic capacitance is reduced and through the back gate The structure controls the threshold voltage to realize high-pass current and normally shutdown transistors.

Benefits of technology

A transistor with high-pass current and large parasitic capacitance is realized, which reduces the power consumption of the memory device and improves the read and write speed and reliability of the memory device.

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Abstract

The invention discloses a semiconductor device. Provided is a transistor capable of achieving miniaturization. The semiconductor device includes an oxide semiconductor layer, first to fourth conductive layers, and first to fourth insulating layers, and a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer including a first opening overlapping the recess are sequentially disposed on the first conductive layer having the recess. The third insulating layer is in contact with at least a side surface of the second conductive layer in the first opening, the oxide semiconductor layer is in contact with a top surface of the third conductive layer and a bottom surface and a side surface of the recess and is in contact with the third insulating layer in the first opening, and the fourth insulating layer is located inside the oxide semiconductor layer in the first opening. The fourth conductive layer is located inside the fourth insulating layer within the first opening, and the oxide semiconductor layer has a region that overlaps the second conductive layer via the third insulating layer and overlaps the fourth conductive layer via the fourth insulating layer in a cross-sectional view.
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Claims

1. A semiconductor device comprising: an oxide semiconductor layer; a first conductive layer; a second conductive layer; a third conductive layer; a fourth conductive layer; a first insulating layer; a second insulating layer; A third insulating layer; as well as The fourth insulating layer, Wherein, the first insulating layer is located on the first conductive layer, The second conductive layer is located on the first insulating layer, The second insulating layer is located on the second conductive layer, The third conductive layer is located on the second insulating layer, The first conductive layer has a first recessed portion, The first insulating layer, the second conductive layer, the second insulating layer, and the third conductive layer have a first opening at a position overlapping the first recess. The third insulating layer is in contact with at least a side surface of the second conductive layer in the first opening. The oxide semiconductor layer is in contact with the top surface of the third conductive layer and the bottom surface and side surface of the first recess and is in contact with the third insulating layer in the first opening. The fourth insulating layer is located inside the oxide semiconductor layer in the first opening. The fourth conductive layer is located inside the fourth insulating layer in the first opening. Furthermore, when viewed in cross section, the oxide semiconductor layer has a region overlapping with the second conductive layer via the third insulating layer and overlapping with the fourth conductive layer via the fourth insulating layer.

2. The semiconductor device according to claim 1, further comprising a fifth insulating layer, The first conductive layer and the second insulating layer are located on the fifth insulating layer. Furthermore, the shortest distance between the top surface of the fifth insulating layer and the top surface of the first conductive layer in contact with the first insulating layer is longer than the shortest distance between the top surface of the fifth insulating layer and the bottom surface of the fourth insulating layer.

3. The semiconductor device according to claim 1, further comprising a fifth insulating layer, The first conductive layer and the fourth conductive layer are located on the fifth insulating layer. Furthermore, the shortest distance between the top surface of the fifth insulating layer and the top surface of the first conductive layer in contact with the first insulating layer is greater than the shortest distance between the top surface of the fifth insulating layer and the bottom surface of the fourth conductive layer.

4. The semiconductor device according to claim 1, The first conductive layer includes a fifth conductive layer and a sixth conductive layer on the fifth conductive layer, The sixth conductive layer includes a second recessed portion, The first opening overlaps with the second recess, Furthermore, the oxide semiconductor layer is in contact with the bottom surface and the side surface of the second recess.

5. The semiconductor device according to claim 1, further comprising a sixth insulating layer, wherein the fourth insulating layer covers the top surface and side surfaces of the oxide semiconductor layer on the second insulating layer, The sixth insulating layer is located on the fourth insulating layer and has a second opening at a position overlapping the first opening. The fourth conductive layer includes a portion overlapping the oxide semiconductor layer via the fourth insulating layer in the first opening and a portion located in the second opening.

6. The semiconductor device according to claim 1, further comprising a sixth insulating layer, wherein the sixth insulating layer is located on the second insulating layer, covers the top surface and side surfaces of the oxide semiconductor layer on the second insulating layer and has a second opening at a position overlapping with the first opening, The fourth insulating layer has a portion located in the second opening, And the fourth conductive layer is located inside the fourth insulating layer in the second opening.

7. The semiconductor device according to claim 1, wherein the third insulating layer includes a seventh insulating layer in contact with the oxide semiconductor layer and an eighth insulating layer located outside the seventh insulating layer in the first opening, Furthermore, one of the seventh insulating layer and the eighth insulating layer is an oxidized insulating layer, and the other is a nitrided insulating layer.

8. The semiconductor device according to claim 1, further comprising: a fifth insulating layer; as well as a fifth conductive layer, wherein the fifth insulating layer is located on the fourth insulating layer and has a second opening reaching the fourth conductive layer at a position overlapping with the first opening, And the fifth conductive layer is in contact with the fourth conductive layer in the second opening.

9. A semiconductor device comprising: First floor; as well as a second layer on the first layer, The second layer includes a first memory cell array and a second memory cell array. The first memory cell array includes a plurality of first memory cells. The second storage cell array includes a plurality of second storage cells, The first layer includes a transistor including silicon in a channel formation region, The first memory cell and the second memory cell both include vertical transistors. The vertical transistor includes an oxide semiconductor in a channel formation region, And, the first storage unit and the second storage unit have different structures from each other.

10. A semiconductor device comprising: First floor; a second layer on the first layer; and The third layer on the second layer, Wherein, the second layer comprises a first memory cell array, The third layer includes a second memory cell array, The first memory cell array includes a plurality of first memory cells. The second storage cell array includes a plurality of second storage cells, The first layer includes a transistor including silicon in a channel formation region, The first memory cell and the second memory cell both include vertical transistors. The vertical transistor includes an oxide semiconductor in a channel formation region, And, the first storage unit and the second storage unit have different structures from each other.

11. The semiconductor device according to claim 9, One of the first storage unit and the second storage unit can retain information for a longer period of time than the other in a state where no power is supplied.

12. The semiconductor device according to claim 10, One of the first storage unit and the second storage unit can retain information for a longer period of time than the other in a state where no power is supplied.

13. A semiconductor device comprising: First floor; as well as a second layer on the first layer, The second layer includes a first memory cell array and a second memory cell array. The first memory cell array includes a plurality of first memory cells. The second storage cell array includes a plurality of second storage cells, The first layer includes a transistor including silicon in a channel formation region, The first storage unit is composed of a vertical transistor and a capacitor. The second storage unit is composed of two vertical transistors. Furthermore, the vertical transistors included in the first memory cell and the second memory cell both include an oxide semiconductor in a channel formation region.

14. A semiconductor device comprising: First floor; a second layer on the first layer; and The third layer on the second layer, Wherein, the second layer comprises a first memory cell array, The third layer includes a second memory cell array, The first memory cell array includes a plurality of first memory cells. The second storage cell array includes a plurality of second storage cells, The first layer includes a transistor including silicon in a channel formation region, One of the first storage unit and the second storage unit is composed of a vertical transistor and a capacitor, and the other is composed of two vertical transistors. Furthermore, the vertical transistors included in the first memory cell and the second memory cell both include an oxide semiconductor in a channel formation region.

Citation Information

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