Manufacturing method of micro-nano cone structure with high aspect ratio
By combining reactive ion etching and inductively coupled plasma etching equipment and adjusting etching parameters, the fabrication challenge of high aspect ratio micro-nano cone structures in LED wafers was solved, improving the luminous efficiency of LEDs and adapting to miniaturization requirements.
Patent Information
- Application Number
- CN202411395617.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-08
- Publication Date
- 2025-01-10
AI Technical Summary
Existing technologies make it difficult to precisely control high aspect ratio micro-nano cone structures in LED wafers, especially the fabrication methods that limit their lateral dimensions to around 200 nanometers, leading to a decline in device performance.
The etching process involves three separate etching operations using reactive ion etching and inductively coupled plasma etching. By adjusting the etching parameters to reduce the physical bombardment ratio, vertical etching is achieved through chemical reactions, resulting in a high aspect ratio micro-nano cone structure.
The fabrication of micro-nano cone structures with high aspect ratios has been achieved, improving the luminous efficiency of LEDs and adapting to the trend of miniaturization, thus avoiding the degradation of device performance.
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Figure CN119284829A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of LEDs, and in particular to a method for manufacturing a micro-nano pyramidal structure with a high aspect ratio. Background Art
[0002] Surface micro-nanostructure roughening is an important means to improve the luminous efficiency of LEDs. Currently, most commercial high-power LED devices on the market are roughened to varying degrees during wafer processing. The more common practice is to use KOH solution for corrosion to form a pyramid-shaped structure. The aspect ratio of this structure is generally between 0.5-1, but it cannot be precisely controlled, so the pyramid-shaped structure is often at the micron level.
[0003] In the prior art, although the academic community can obtain nanostructures with higher aspect ratios through nanoimprinting, photolithography, etc., due to the limitations of equipment and methods, cone structures are still not obtained, and the cost is high, making it difficult to achieve commercial use. At the same time, the improvement in luminous efficiency brought about by coarsening is proportional to the height of the structure. If the traditional method wants to obtain a structure with a height exceeding 1 micron, its diameter will be around 1-2 microns, which is not conducive to the current trend of LED miniaturization. For the emerging Micro-LED, its device size is often less than 50 microns, and a larger cone structure will reduce the performance of the device. Therefore, improving the aspect ratio of the cone structure, especially a method for making a structure that can limit its lateral size to around 200 nanometers, is an urgent market demand. Summary of the invention
[0004] The purpose of the present invention is to provide a method for manufacturing a micro-nano pyramidal structure with a high aspect ratio, and to solve the following technical problems:
[0005] How to improve the aspect ratio of the pyramidal structure in LED wafers?
[0006] The purpose of the present invention can be achieved through the following technical solutions:
[0007] A method for manufacturing a micro-nano pyramidal structure with a high aspect ratio comprises the following steps:
[0008] S1: first depositing a SiO2 buffer layer on the cleaned target wafer, and then depositing a metal mask layer on the SiO2 buffer layer;
[0009] S2: Use a reactive ion etching device to perform the first etching and the second etching in sequence on the deposited metal mask layer, and then use an inductively coupled plasma etching device to perform the third etching; wherein, the first etching removes the metal mask layer to expose the SiO2 buffer layer; the second etching removes the SiO2 buffer layer exposed by the first etching to expose the target wafer; the third etching falls on the target wafer exposed by the second etching to form a micro-nano structure.
[0010] In a further embodiment of the present invention: in step S1, the deposition thickness of the SiO2 buffer layer is 600-650nm.
[0011] In a further embodiment of the present invention: the SiO2 buffer layer is deposited by plasma enhanced chemical vapor deposition technology.
[0012] In a further embodiment of the present invention: in step S1, the deposition thickness of the metal mask layer is 150-200 nm.
[0013] In a further embodiment of the present invention, the metal material of the metal mask layer is one of aluminum, gold, silver, platinum, copper, chromium, titanium and nickel.
[0014] In a further embodiment of the present invention: in step S2, the parameters of the first etching are: time 20-40 min; pressure 2-10 mtor r; power 325-465 W; gas composition is a combination of two or more of CHF3, SF6, CF4, O2.
[0015] In a further embodiment of the present invention: in step S2, the parameters of the second etching are: time 15-20 min; pressure 2-100 mtor r; power 105-165 W; gas composition is a combination of two or more of CHF3, SF6, CF4, O2.
[0016] In a further embodiment of the present invention: in step S2, the parameters of the third etching are: time 4-12 min; pressure 2-40 mtor r; ion concentration power 40-800 W; bias power 2-140 W; gas composition is a combination of two or more of Cl2, BCl2, Ar, and O2.
[0017] Beneficial effects of the present invention:
[0018] In the method for manufacturing a micro-nano pyramidal structure with a high aspect ratio of the present invention, when etching the deposited metal mask layer, a reactive ion etching device is used to sequentially perform the first etching and the second etching, and then an inductively coupled plasma etching device is used to perform the third etching; during the second etching, the etching parameters of the reactive ion etching device are adjusted, especially the power is reduced, thereby reducing the etching ratio of physical bombardment, the physical bombardment presents anisotropic etching, and the chemical reaction presents isotropic etching, reducing the proportion of physical bombardment, although the etching direction is uncontrollable, the mask formed by the voids in the metal layer will protect the silicon oxide, and the etching rate of the etching gas to the metal is low, so the effect of etching through the silicon oxide buffer layer can be achieved, and at the same time, it is ensured that the metal layer is not etched through, that is, the metal mask layer can be protected until the SiO2 buffer layer is etched through; at the same time, the mask formed by the voids in the metal layer protects the silicon oxide so that the etching is vertically downward, the lateral etching is reduced, and the etched structure is higher, so the aspect ratio of the obtained micro-nano pyramidal structure increases accordingly. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The present invention will be further described below in conjunction with the accompanying drawings.
[0020] Figure 1 It is a flow chart of the method for making a micro-nano pyramidal structure with a high aspect ratio of the present invention.
[0021] Figure 2 is a top view SEM image of the micro-nano pyramidal structure prepared in Example 1;
[0022] Figure 3 is a side view SEM image of the micro-nano pyramidal structure prepared in Example 1;
[0023] Figure 4 is a top view SEM image of the micro-nano pyramidal structure prepared in Example 2;
[0024] Figure 5 is a side view SEM image of the micro-nano pyramidal structure prepared in Example 2;
[0025] Figure 6 is a top view SEM image of the micro-nano pyramidal structure prepared in Example 3;
[0026] Figure 7 is a side view SEM image of the micro-nano pyramidal structure prepared in Example 3;
[0027] Figure 8 is a top view SEM image of the micro-nano pyramidal structure prepared in Example 4;
[0028] Fig. 9 is a side view SEM image of the micro-nano pyramidal structure prepared in Example 4;
[0029] Fig.10 is a top view SEM image of the micro-nano pyramidal structure prepared in Example 5;
[0030] Fig.11 is a side view SEM image of the micro-nano pyramidal structure prepared in Example 5;
[0031] Fig.12 This is a top view SEM image of the micro-nano pyramidal structure prepared in Comparative Example 1;
[0032] Fig.13 This is a side SEM image of the micro-nano pyramidal structure prepared in Comparative Example 1;
[0033] Fig.14 This is a top view SEM image of the micro-nano pyramidal structure prepared in Comparative Example 2;
[0034] Fig.15 This is a side view SEM image of the micro-nano pyramidal structure prepared in Comparative Example 2. DETAILED DESCRIPTION
[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0036] See also Figure 1 The present invention discloses a method for manufacturing a micro-nano pyramidal structure with a high aspect ratio, comprising the following steps:
[0037] Step 1: first deposit a SiO2 buffer layer on the cleaned target wafer, and then deposit a metal mask layer on the SiO2 buffer layer.
[0038] in:
[0039] The SiO2 buffer layer is obtained by plasma enhanced chemical vapor deposition technology, and its deposition thickness is 600-650nm.
[0040] The deposition thickness of the metal mask layer is 150-200 nm, and the metal material thereof is one of aluminum, gold, silver, platinum, copper, chromium, titanium, and nickel.
[0041] Step 2: Use a reactive ion etching device to perform the first etching and the second etching in sequence on the deposited metal mask layer, and then use an inductively coupled plasma etching device to perform the third etching; wherein, the first etching removes the metal mask layer to expose the SiO2 buffer layer; the second etching removes the SiO2 buffer layer exposed by the first etching to expose the target wafer; the third etching falls on the target wafer exposed by the second etching to form a micro-nano structure.
[0042] in:
[0043] The parameters of the first etching are: time 20-40min; pressure 2-10mtorr; power 325-465W; gas composition is a combination of two or more of CHF3, SF6, CF4, and O2.
[0044] The parameters of the second etching are: time 15-20min; pressure 2-100mtorr; power 105-165W; gas composition is a combination of two or more of CHF3, SF6, CF4, and O2.
[0045] The parameters of the third etching are: time 4-12min; pressure 2-40mtorr; ion concentration power 40-800W; bias power 2-140W; gas composition is a combination of two or more of Cl2, BCl2, Ar, and O2.
[0046] In step two, when a reactive ion etching device (RIE) is used to perform the first etching and the second etching in sequence on the deposited metal mask layer, the mechanism of the reactive ion etching device is mainly divided into two parts. One part is the chemical reaction between the etching gas and the sample to be etched, and the other part is the physical bombardment of the surface of the sample to be etched by the plasma formed under high pressure.
[0047] in:
[0048] During the first etching, the metal mask layer is acted on. Since the compatibility of the etching gas and the metal reaction is relatively low compared to SiO2, the physical bombardment can play a greater role at this time. As a result, small holes are bombarded on the surface of the metal mask layer. After the holes formed by the metal mask layer are completely etched through and reach the SiO2 buffer layer, the first etching is completed and the second etching is carried out.
[0049] During the second etching, chemical reaction plays a major role, and the etching rate is much greater than that of etching the metal mask layer. Deeper SiO2 holes are formed under the mask layer of the metal voids. At the same time, physical bombardment is still occurring. While SiO2 is being etched through, the metal mask layer is also completely etched, thus forming a pattern layer with only SiO2 holes.
[0050] For thinner metal mask layers and SiO2 buffer layers, one-step etching can be achieved. However, when the metal layer is thickened to reach the thickness of the present invention, continuing to use high-power etching will result in the metal mask layer being completely etched by physical bombardment before the silicon oxide is etched through, and deeper silicon oxide holes cannot be formed. Therefore, when manufacturing higher nanostructures, it is necessary to adjust the RIE etching parameters after the metal mask layer is formed, especially to reduce the power, so as to reduce the etching ratio of physical bombardment and protect the metal mask layer until the SiO2 buffer layer is etched through.
[0051] Next, the micro-nano pyramidal structure is manufactured by the manufacturing method of the present invention, as shown in the following embodiments 1-5.
[0052] Example 1
[0053] Step 1: On the cleaned target wafer, a SiO2 buffer layer with a thickness of 600 nm is first deposited by plasma enhanced chemical vapor deposition technology, and then a copper mask layer with a thickness of 150 nm is deposited on the SiO2 buffer layer.
[0054] Step 2: using a reactive ion etching device to perform a first etching and a second etching in sequence on the deposited metal mask layer, and then using an inductively coupled plasma etching device to perform a third etching; finally forming a micro-nano structure;
[0055] The parameters of the first etching are: time 20 min; pressure 10 mtorr; power 465 W; gas composition CHF3 and SF6.
[0056] The parameters of the second etching are: time 15 min; pressure 100 mtorr; power 165 W; gas composition CHF3 and SF6.
[0057] The parameters of the third etching are: time 4 minutes; pressure 40 mtorr; ion concentration power 800 W; bias power 2 W; gas composition is Cl2 and BC l2.
[0058] Example 2
[0059] Step 1: On the cleaned target wafer, a SiO2 buffer layer with a thickness of 610 nm is first deposited by plasma enhanced chemical vapor deposition technology, and then a copper mask layer with a thickness of 160 nm is deposited on the SiO2 buffer layer.
[0060] Step 2: using a reactive ion etching device to perform a first etching and a second etching in sequence on the deposited metal mask layer, and then using an inductively coupled plasma etching device to perform a third etching; finally forming a micro-nano structure;
[0061] The parameters of the first etching are: time 25 min; pressure 8 mtor r; power 420 W; gas composition CHF3 and CF4.
[0062] The parameters of the second etching are: time 16 min; pressure 80 mtorr; power 155 W; gas composition is CHF3 and CF4.
[0063] The parameters of the third etching are: time 6 minutes; pressure 30 mtorr; ion concentration power 600 W; bias power 30 W; gas composition is Cl2 and Ar.
[0064] Example 3
[0065] Step 1: On the cleaned target wafer, a SiO2 buffer layer with a thickness of 620 nm is first deposited by plasma enhanced chemical vapor deposition technology, and then a copper mask layer with a thickness of 180 nm is deposited on the SiO2 buffer layer.
[0066] Step 2: using a reactive ion etching device to perform a first etching and a second etching in sequence on the deposited metal mask layer, and then using an inductively coupled plasma etching device to perform a third etching; finally forming a micro-nano structure;
[0067] The parameters of the first etching are: time 30 min; pressure 6 mtor r; power 400 W; gas composition is CHF3 and O2.
[0068] The parameters of the second etching are: time 18 min; pressure 60 mtorr; power 145 W; gas composition CHF3 and O2.
[0069] The parameters of the third etching are: time 8 minutes; pressure 20 mtorr; ion concentration power 400 W; bias power 70 W; gas composition is Cl2 and O2.
[0070] Example 4
[0071] Step 1: On the cleaned target wafer, a SiO2 buffer layer with a thickness of 640 nm is first deposited by plasma enhanced chemical vapor deposition technology, and then a copper mask layer with a thickness of 190 nm is deposited on the SiO2 buffer layer.
[0072] Step 2: using a reactive ion etching device to perform a first etching and a second etching in sequence on the deposited metal mask layer, and then using an inductively coupled plasma etching device to perform a third etching; finally forming a micro-nano structure;
[0073] The parameters of the first etching are: time 35 min; pressure 4 mtor r; power 360 W; gas composition SF6 and CF4.
[0074] The parameters of the second etching are: time 19 min; pressure 40 mtorr; power 125 W; gas composition SF6 and CF4.
[0075] The parameters of the third etching are: time 10 min; pressure 10 mtorr; ion concentration power 200 W; bias power 100 W; gas composition is BC l2 and Ar.
[0076] Example 5
[0077] Step 1: On the cleaned target wafer, a SiO2 buffer layer with a thickness of 650 nm is first deposited by plasma enhanced chemical vapor deposition technology, and then a copper mask layer with a thickness of 200 nm is deposited on the SiO2 buffer layer.
[0078] Step 2: using a reactive ion etching device to perform a first etching and a second etching in sequence on the deposited metal mask layer, and then using an inductively coupled plasma etching device to perform a third etching; finally forming a micro-nano structure;
[0079] The parameters of the first etching are: time 40 min; pressure 2 mtor r; power 325 W; gas composition SF6 and O2.
[0080] The parameters of the second etching are: time 20 min; pressure 2 mtor r; power 105 W; gas composition SF6 and O2.
[0081] The parameters of the third etching are: time 12 minutes; pressure 2 mtorr; ion concentration power 40W; bias power 140W; gas composition is BC l2 and O2.
[0082] Comparative Example 1
[0083] Compared with Example 3, the only difference is that in step 2, the parameters of the second etching are pressure 6 mtor r and power 400 W, that is, the pressure parameters and power parameters are the same as those of the first etching; other operating conditions are exactly the same.
[0084] Comparative Example 2
[0085] Compared with Example 3, the only difference is that in step 2, among the parameters of the first etching, the pressure is 60mtorr; the power is 145W, that is, the pressure parameters and power parameters are the same as the pressure parameters and power parameters of the second etching; other operating conditions are exactly the same.
[0086] The micro-nano structures obtained in Examples 1-5 and Comparative Examples 1-2 were examined using a scanning electron microscope (SEM) to obtain the following: Figure 2-15From the SEM images shown, it can be seen that the micro-nano structures in Examples 1-5 and Comparative Examples 1-2 are all pyramidal structures. However, compared with the micro-nano structures in Comparative Examples 1-2, the aspect ratio of the micro-nano structures in Examples 1-5 is visually higher.
[0087] In order to further determine the aspect ratio of the micro-nano structure, the aspect ratio of the pyramidal micro-nano structure in Examples 1-5 and Comparative Examples 1-2 was tested by the following method:
[0088] First, the sample surface was characterized by SEM and the diameter of the structure was measured. Then the sample was cut and the cross section was photographed by SEM. The height of the structure was measured. The measured diameter and height were counted and the average value was calculated after removing the values with large deviations.
[0089] The detection structure is listed in Table 1, which is as follows:
[0090] Table 1
[0091] Example 1 Example 2 Example 3 Example 4 Example 5 Comparative Example 1 Comparative Example 2 Height / nm 1000 900 1200 1000 900 650 625 Diameter / nm 300 200 250 250 250 300 250 Aspect Ratio 3.33 4.5 4.8 4.0 3.6 2.17 2.5
[0092] By analyzing the data in Table 1, it can be seen that the pyramidal micro-nano structures prepared in Examples 1-5 have a higher aspect ratio than that in Comparative Examples 1-2.
[0093] Therefore, the manufacturing method of the present invention can obtain a micro-nano pyramidal structure with a high aspect ratio.
[0094] In the description of the present invention, "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0095] The above is a detailed description of an embodiment of the present invention, but the content is only a preferred embodiment of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.
Claims
1. A method for manufacturing a micro-nano pyramidal structure with a high aspect ratio, characterized in that: The following steps are involved: S1: first depositing a SiO2 buffer layer on the cleaned target wafer, and then depositing a metal mask layer on the SiO2 buffer layer; S2: using a reactive ion etching device to sequentially perform a first etching and a second etching on the deposited metal mask layer, and then using an inductively coupled plasma etching device to perform a third etching; wherein the first etching removes the metal mask layer to expose the SiO2 buffer layer; the second etching removes the SiO2 buffer layer exposed by the first etching to expose the target wafer; The third etching is performed on the target wafer exposed by the second etching to form a micro-nano structure.
2. The method for manufacturing a micro-nano pyramidal structure with a high aspect ratio according to claim 1, characterized in that: In step S1, the deposition thickness of the SiO2 buffer layer is 600-650nm.
3. The method for manufacturing a micro-nano pyramidal structure with a high aspect ratio according to claim 2, characterized in that: The SiO2 buffer layer is deposited by plasma enhanced chemical vapor deposition technology.
4. The method for manufacturing a micro-nano pyramidal structure with a high aspect ratio according to claim 1, characterized in that: In step S1, the deposition thickness of the metal mask layer is 150-200 nm.
5. The method for manufacturing a micro-nano pyramidal structure with a high aspect ratio according to claim 4, characterized in that: The metal material of the metal metal mask layer is one of aluminum, gold, silver, platinum, copper, chromium, titanium and nickel.
6. The method for manufacturing a micro-nano pyramidal structure with a high aspect ratio according to claim 1, characterized in that: In step S2, the parameters of the first etching are: time 20-40 min; pressure 2-10 mtor r; power 325-465 W; gas composition is a combination of two or more of CHF3, SF6, CF4, and O2.
7. The method for manufacturing a micro-nano pyramidal structure with a high aspect ratio according to claim 4, characterized in that: In step S2, the parameters of the second etching are: time 15-20 min; pressure 2-100 mtor r; power 105-165 W; gas composition is a combination of two or more of CHF3, SF6, CF4, and O2.
8. The method for manufacturing a micro-nano pyramidal structure with a high aspect ratio according to claim 4, characterized in that: In step S2, the parameters of the third etching are: time 4-12 min; pressure 2-40 mtor r; ion concentration power 40-800 W; bias power 2-140 W; gas composition is a combination of two or more of Cl2, BCl2, Ar, and O2.