Wiring method and device, electronic equipment and storage medium

Abstract

The invention provides a wiring method and device, electronic equipment and a storage medium, and belongs to the technical field of integrated circuits, in the wiring method, according to a pre-analysis result of each time sequence path, the logic series and / or logic resources of the time sequence path with tense time sequence are / is firstly adjusted to reduce the congestion degree and the logic series of the time sequence path, and the time sequence path with tense time sequence is obtained. And then wiring is carried out on the basis of adjustment, so that the wiring failure probability is reduced. And if a time sequence path with a non-convergent time sequence exists after wiring and a readjustment condition is satisfied, entering the step of analyzing the time sequence path again to carry out a new round of wiring adjustment until all the time sequence paths reach the time sequence convergence or do not satisfy the readjustment condition. Therefore, the problems that a time sequence pre-analysis result cannot be intervened and the congestion degree cannot be adjusted in a traditional FPGA wiring method are solved, the designed time sequence performance is improved, the risk of wiring failure is reduced, and then improvement of design efficiency and conversion of design achievements are facilitated.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a wiring method, device, electronic equipment and storage medium. Background Art

[0002] The development process of Field Programmable Gate Array (FPGA) software tools mainly includes logic synthesis, layout, routing, timing analysis and code stream generation. Among them, FPGA routing is the process of selecting a suitable path from the numerous routing resources of FPGA devices for the connection between the ports of each primitive (such as lookup table, register, etc.) in the user design netlist after layout. The purpose of FPGA routing is to select an optimal path for the connection of each primitive port to meet the timing requirements of the user design.

[0003] In the traditional FPGA routing method, after the layout of each primitive in the FPGA is completed, the available FPGA routing resources are routed for each connection starting from the output port of a primitive according to the port connection relationship and location information of the primitive, and a path to the input port of the next connected primitive that meets the timing constraints as much as possible is found. This routing method can easily make the routing result unable to meet the requirements of timing convergence, and there may even be a risk of routing failure. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a wiring method, an apparatus, an electronic device and a storage medium, so that the wiring result meets the requirements of timing convergence and greatly reduces the risk of wiring failure.

[0005] In order to achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0006] In a first aspect, the present invention provides a wiring method, the method comprising:

[0007] According to the layout results and timing constraint information, the timing path of the designed circuit is pre-analyzed to obtain the delay value and congestion of each timing path;

[0008] Determine a timing-critical path from each of the timing paths according to the delay value and the congestion degree, and adjust the logic levels and / or logic resources of the timing-critical path;

[0009] After all adjustments are completed, the designed circuit is wired;

[0010] After the wiring is completed, determining whether all the timing paths have reached timing closure;

[0011] If not, judging whether a readjustment condition is met according to the timing path whose timing has not converged;

[0012] When the readjustment condition is met, the step of performing a preliminary analysis on the timing paths of the design circuit according to the layout result and the timing constraint information to obtain the delay value and congestion degree of each timing path is returned to be executed.

[0013] Optionally, the step of determining a tight timing path from each of the timing paths according to the delay value and the congestion degree, and adjusting the logic level and / or logic resource of the tight timing path includes:

[0014] From the timing paths, select a timing path whose delay value is greater than a first convergence threshold as a timing-critical path;

[0015] For each of the timing-critical paths, lowering the logic level of the timing-critical path;

[0016] The timing-critical path whose congestion degree is greater than a congestion threshold is taken as a congested path, and logical resources of the congested path are adjusted.

[0017] Optionally, the step of reducing the logic level of the timing-critical path includes:

[0018] Determine a connection coverage area of ​​the timing-critical path, and divide the connection coverage area into a plurality of sub-areas;

[0019] Calculating the congestion and delay value of each of the sub-areas;

[0020] The sub-area in which the delay value is not greater than the second convergence threshold is used as the convergence area;

[0021] The convergence area with the minimum congestion is taken as a target area, and a first-level virtual register is inserted into the target area.

[0022] Optionally, the step of adjusting the logical resources of the congested path includes:

[0023] Selecting one of the primitives corresponding to the logical resources of the congested path as a target object;

[0024] From the timing paths of the designed circuit, a timing path whose timing still converges after the target object is inserted and whose distance to the position of the target object is the shortest is selected as a hit path;

[0025] The position of the target object is adjusted to the hit path.

[0026] Optionally, after the step of pre-analyzing the timing paths of the designed circuit according to the layout results and the timing constraint information to obtain the delay value and congestion of each timing path, and before the step of routing the designed circuit after completing all adjustments, the method further includes:

[0027] For each of the timing paths, taking the priority corresponding to the delay value of the timing path as the connection priority of each primitive of the timing path;

[0028] After all adjustments are completed, the step of performing wiring of the designed circuit includes:

[0029] After completing all adjustments, determining all primitives of the designed circuit;

[0030] According to the order of the connection priorities from high to low and the preset connection order, the primitive connections are performed using the wiring resources.

[0031] Optionally, the step of judging whether a readjustment condition is met according to the timing path whose timing has not converged includes:

[0032] From the timing paths whose timing has not converged, select the timing path with the highest current delay value as the target path;

[0033] According to the primitive of the target path, it is determined whether a readjustment condition is met.

[0034] Optionally, the step of judging whether a readjustment condition is met according to the primitive of the target path includes:

[0035] Obtaining the position and quantity of each primitive of the target path and the quantity of routing nodes of the target path;

[0036] Using a ratio of the location of the primitive to a preset timing constraint as a first factor, and using a ratio of the number of the primitives to the number of the routing nodes as a second factor;

[0037] Determine whether the first factor and the second factor are both greater than their respective corresponding adjustment thresholds;

[0038] If so, it is determined that the readjustment condition is not satisfied;

[0039] If not, it is determined that the readjustment condition is met.

[0040] In a second aspect, the present invention provides a wiring device, including a pre-analysis module, an optimization and adjustment module, a wiring module, a convergence judgment module and a polling module;

[0041] The pre-analysis module is used to pre-analyze the timing paths of the designed circuit according to the layout results and the timing constraint information to obtain the delay value and congestion degree of each timing path;

[0042] The optimization and adjustment module is used to determine a timing-critical path from each of the timing paths according to the delay value and the congestion degree, and adjust the logic levels and / or logic resources of the timing-critical path;

[0043] The wiring module is used to perform wiring of the designed circuit after all adjustments are completed;

[0044] The convergence judgment module is used to judge whether all the timing paths have reached timing convergence after the wiring is completed;

[0045] The polling module is configured to determine whether a re-adjustment condition is met according to the timing path whose timing has not converged if at least one of the timing paths has not converged;

[0046] The polling module is also used to control the pre-analysis module to return to execute the step of pre-analyzing the timing path of the designed circuit according to the layout results and timing constraint information to obtain the delay value and congestion degree of each timing path when the readjustment condition is met.

[0047] In a third aspect, the present invention provides an electronic device, comprising a processor and a memory, wherein the memory stores a computer program executable by the processor, and the processor can execute the computer program to implement the wiring method as described in the first aspect.

[0048] In a fourth aspect, the present invention provides a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the wiring method as described in the first aspect.

[0049] The wiring method, device, electronic device and storage medium provided by the embodiments of the present invention, in which the timing path of the designed circuit is pre-analyzed to obtain the delay value and congestion of each timing path, and the logic level and / or logic resource of the timing-critical path are adjusted according to the delay value and congestion. After all adjustments are completed, the designed circuit is wired, and after the wiring is completed, if it is determined that there are still timing paths that have not reached timing convergence, then if the readjustment conditions are met, the step of analyzing the delay value and congestion of the timing path is re-entered to perform a new round of wiring adjustment.

[0050] In this way, after the layout is completed, according to the pre-analysis results, the logic level and / or logic resources of the timing path with tight timing are first adjusted to reduce the congestion of the timing path and make the timing path reach timing convergence as much as possible, and then the wiring is performed on the basis of the adjustment to reduce the probability of wiring failure caused by congestion or timing non-convergence. If there are still timing paths with non-convergence in timing after wiring, and the readjustment conditions are met, the step of analyzing the timing path is re-entered to perform a new round of wiring adjustment, that is, the wiring is removed and re-routed until all timing paths reach timing convergence, or the wiring is terminated when the readjustment conditions are not met. Thereby, the problem that the traditional FPGA wiring method cannot intervene in the timing pre-analysis results and cannot adjust the congestion is solved, the timing performance of the design is improved, and the risk of wiring failure is greatly reduced, which in turn helps to improve design efficiency and realize the transformation of design results.

[0051] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 A block diagram of a development and design system provided by an embodiment of the present invention is shown.

[0054] Figure 2 A block diagram of an electronic device provided by an embodiment of the present invention is shown.

[0055] Figure 3 One of the flow charts of the wiring method provided by the embodiment of the present invention is shown.

[0056] Figure 4 Shows Figure 3 Schematic diagram of the process flow of some sub-steps of step 13.

[0057] Figure 5 Shows Figure 4 A flowchart of some sub-steps of step 133 in FIG.

[0058] Figure 6 Shows Figure 4 A flowchart of some sub-steps of step 135 in FIG.

[0059] Figure 7The second flowchart of the wiring method provided by the embodiment of the present invention is shown.

[0060] Figure 8 Shows Figure 7 Schematic diagram of the process flow of some sub-steps of step 15.

[0061] Fig. 9 Shows Figure 3 and Figure 7 Schematic diagram of the process of some sub-steps of step 19.

[0062] Fig.10 A block diagram of a wiring device provided by an embodiment of the present invention is shown.

[0063] Explanation of the reference numerals: 10 - development and design system; 110 - FPGA development board; 120 - processing device; 130 - input device; 20 - electronic device; 210 - memory; 220 - processor; 230 - communication module; 30 - wiring device; 310 - pre-analysis module; 320 - optimization and adjustment module; 330 - wiring module; 340 - convergence judgment module; 350 - polling module. DETAILED DESCRIPTION

[0064] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0065] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0066] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0067] First, several terms involved in the embodiments of the present invention are introduced and explained.

[0068] Primitives: can be understood as the abstract representation of the logic resources of FPGA, which are the basic elements that constitute the logic blocks, including the lookup table (LUT), register (registor, reg), memory and other logic resources inside the FPGA chip.

[0069] Routing nodes: During the layout phase of the FPGA design process, primitives are mapped to specific physical locations on the FPGA chip. These locations determine the distribution of routing nodes, which represent the connection points between the various logic units in the design.

[0070] Timing path: It can be understood as the logical path that the data signal passes through during the propagation process in the design. Each timing path has a corresponding starting point and end point, which covers multiple primitives.

[0071] The wiring method provided by the embodiment of the present invention can be applied to Figure 1 In the development and design system 10 shown, the development and design system 10 includes an FPGA development board 110, a processing device 120 and an input device 130. The input device 130 can be connected to the processing device 120 through a network, WiFi, Bluetooth, or a wired connection, and the processing device 120 can be connected to the FPGA development board 110 through a downloader, etc. The FPGA development board 110 includes an FPGA chip.

[0072] The processing device 120 may be installed with development tools, such as wiring and layout tools, synthesis tools, simulation tools, and debugging and verification tools.

[0073] The input device 130 is used to input design requirements or design instructions, etc. to the processing device 120 .

[0074] The processing device 120 is used to develop and design the FPGA based on the development tool in combination with the received design requirements or design instructions, and after converting the design result into a bitstream file, download the bitstream file to the FPGA chip on the FPGA development board 110. The FPGA development and design process includes: logic synthesis, layout, routing, timing analysis and bitstream generation.

[0075] The FPGA development board 110 is used to execute the bitstream file to perform hardware testing of the FPGA design.

[0076] After the layout is completed, a layout result is obtained, which includes the number of primitives covered by each timing path of the design circuit and the position of each primitive.

[0077] After the layout is completed, the processing device 120 is used to execute the steps of the wiring method provided in the embodiment of the present invention to perform FPGA wiring.

[0078] The processing device 120 may be, but is not limited to, a personal computer, a laptop computer, a tablet computer, a server, a server cluster, etc. The input device 130 may be, but is not limited to, a keyboard, a personal computer, a laptop computer, a tablet computer, a mobile phone, etc.

[0079] Please refer to Figure 2 , is a block diagram of an electronic device 20, which may be Figure 1 The processing device 120 in the development and design system 10 is shown. The electronic device 20 includes a memory 210, a processor 220, and a communication module 230. The memory 210, the processor 220, and the communication module 230 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0080] The memory 210 is used to store programs or data and can be, but not limited to, a random access memory, a read-only memory, a programmable read-only memory, an erasable read-only memory, an electrically erasable read-only memory, and the like.

[0081] The processor 220 is used to read / write data or programs stored in the memory 210 and execute corresponding functions. For example, Figure 1 In the development and design system 10 shown, the processor 220 of the processing device 120 executes the computer program stored in the memory 210 to implement the wiring method provided in the embodiment of the present invention.

[0082] The communication module 230 is used to establish a communication connection between the processing device 120 and other communication terminals, and to send and receive data. Figure 1 In the development and design system 10 shown, the communication module 230 of the processing device 120 can send and receive data with the input device 130 through the network, or send and receive data with the FPGA development board 110.

[0083] It should be understood that Figure 2 The structure shown is only a schematic diagram of the structure of the electronic device 20. The electronic device 20 may include Figure 2 More or fewer components as shown, or with Figure 2 Different configurations are shown. Figure 2 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0084] Please refer to Figure 3The embodiment of the present invention provides a wiring method, comprising steps 11 to 19, and Figure 1 In the development and design system 10 shown, the processing device 120 can Figure 2 The structure shown implements the above steps 11 to 19 when the processor 220 executes the computer program stored in the memory 210.

[0085] Step 11: Preliminary analysis is performed on the timing paths of the designed circuit according to the layout results and the timing constraint information to obtain the delay value and congestion degree of each timing path.

[0086] Step 13: determine a timing-critical path from each timing path according to the delay value and the congestion degree, and adjust the logic levels and / or logic resources of the timing-critical path.

[0087] Step 15, after completing all adjustments, proceed with the wiring of the designed circuit.

[0088] Step 17: After the routing is completed, determine whether all timing paths have reached timing closure. If not, execute step 19; if yes, terminate the routing.

[0089] Step 19, judging whether the readjustment condition is met according to the timing path whose timing has not converged. If it is determined that the readjustment condition is met, returning to the above step 11 to perform the next round of routing adjustment, if it is determined that the readjustment condition is not met, the routing is terminated.

[0090] For example, in combination Figure 1 In the development and design system 10 shown, during the process of FPGA design, the designer or user can input the project requirements into the processing device 120 through the input device 130. The designer manually performs the requirements analysis, or the processing device 120 performs the requirements analysis based on the input project requirements, and formulates the goals and requirements of the project, such as performance indicators, interface requirements, power consumption limits, etc. Then, the designer or the processing device 120 designs the system architecture and module division according to the requirements analysis results, and writes the code using the hardware description language to describe the behavior, structure, etc. of the digital circuit to be designed (hereinafter collectively referred to as the design circuit). Then, the written code is reviewed or modified by manual review or automatic review by the processing device 120. After completing the code review, the processing device 120 uses a simulation tool to simulate the reviewed code to verify the correctness of the logical function. After the verification is passed, the processing device 120 uses a synthesis tool to convert the code into a gate-level netlist, and optimizes the design according to the synthesis results to meet the goals of timing requirements, resource usage, and power consumption.

[0091] After completing the design optimization of the synthesis result, the processing device 120 maps the netlist to the physical resources of the FPGA chip in the FPGA development board 110 for layout. After the layout is completed, the processing device 120 pre-analyzes the timing path of the design circuit according to the layout results and timing constraint information to obtain the delay value and congestion of each timing path. Then, the processing device 120 adjusts the logic level and / or logic resources of the timing tight path according to the delay value and congestion, and after completing all adjustments, the design circuit is routed. Thus, after the routing is completed, if the processing device 120 determines that there are still timing paths that have not reached timing convergence, then under the condition of re-adjustment, the step of analyzing the delay value and congestion of the timing path is re-entered to perform a new round of routing adjustment. Until all timing paths reach timing convergence, or when the re-adjustment conditions are not met, the routing is terminated. After the routing is completed, the processing device 120 can continue to perform processing such as timing analysis and bitstream generation, which will not be repeated here.

[0092] In the traditional FPGA routing method, after the layout of each primitive in the FPGA is completed, the available FPGA routing resources are routed from the output port of a primitive for each connection according to the port connection relationship and the location information of the primitive, and a path to the input port of another connected primitive that meets the timing requirements as much as possible is found under the constraints of the timing requirements. This routing method has two defects: first, when the positions of the input primitives and output primitives with a connection relationship do not meet the timing requirements, there is no solution to the timing non-convergence caused by this; second, when the positions of the input primitives and output primitives with a connection relationship are close, but the layout primitives near the layout position are congested, the congested primitive connections compete fiercely for routing resources, and the traditional routing method cannot adjust the congested path, resulting in timing non-convergence.

[0093] Compared with the traditional FPGA wiring method, the wiring method provided in this embodiment, including the above steps 11 to 19, after the layout is completed, first adjusts the logic level and / or logic resources of the timing path with tight timing according to the pre-analysis results to reduce the congestion of the timing path and make the timing path reach timing convergence as much as possible, and then performs wiring on the adjusted basis to reduce the probability of wiring failure caused by congestion or timing non-convergence.

[0094] In addition, if there are still timing paths with unconverged timing after routing and the readjustment conditions are met, the step of analyzing the timing paths is re-entered to perform a new round of routing adjustments, that is, to remove the wires and re-route until all timing paths reach timing convergence or do not meet the readjustment conditions, then the routing is terminated. Thus, the problem that the traditional FPGA routing method cannot intervene in the timing pre-analysis results and cannot adjust the congestion is solved, the timing performance of the design is improved, and the risk of routing failure is greatly reduced, which helps to improve design efficiency and realize the transformation of design results.

[0095] Among them, the method of obtaining the delay value of each timing path in step 11 can be set flexibly. For example, for each timing path, the data arrival time, clock arrival time, data requirement time for establishment time, data requirement time for hold time, timing margin and clock uncertainty of the timing path can be calculated to obtain the delay value by addition and subtraction. The delay value can also be calculated using preset rules, and its implementation method is not restricted.

[0096] In order to more accurately estimate the delay value of the timing path, in step 11, for each timing path, the starting primitive and the ending primitive of the timing path are extracted from the layout results, and the relative distance between the starting primitive and the ending primitive is obtained according to the position of the starting primitive and the position of the ending primitive, and then according to the unit delay value corresponding to the unit distance pre-set in the timing constraint information, the delay value corresponding to the relative distance is calculated to estimate the delay value of the timing path.

[0097] It should be noted that the unit delay value may be a value obtained by fitting the calibration experimental data, or a value set based on experience or historical data, and the method for obtaining the value is not limited herein.

[0098] In addition, for each timing path, the number of primitives and the number of routing nodes covered by the timing path can be queried from the layout results, and the ratio of the two can be calculated to obtain the congestion degree of the timing path.

[0099] Through the above method, the delay value and congestion of the timing path can be accurately estimated before routing.

[0100] On the basis of the known delay value and congestion of each timing path, in step 13, the timing path whose delay value or congestion does not meet the corresponding threshold can be regarded as the timing tight path, and the timing path whose delay value and congestion meet the preset relationship can also be regarded as the timing tight path. The above method is only an example, and its implementation method is not limited.

[0101] In order to make the timing path reach timing closure more quickly, the idea of ​​reducing the logic level of each timing-critical path and adjusting the logic resources of the timing-critical path with excessive congestion is introduced in step 13. Figure 4 , step 13 may include steps 131 to 135.

[0102] Step 131 : Select, from among the timing paths, a timing path whose delay value is greater than a first convergence threshold as a timing-critical path.

[0103] The timing constraint information may predefine a first convergence threshold for each timing path, and the first convergence thresholds for each timing path may be the same or different. In addition, the value of the first convergence threshold may be flexibly set, for example, it may be 3ns or 5ns, which may vary depending on the required functions of the design project (i.e., the design circuit).

[0104] Step 133 , for each timing-critical path, lower the logic level of the timing-critical path.

[0105] Step 135: The timing-critical path whose congestion degree is greater than the congestion threshold is regarded as a congested path, and the logical resources of the congested path are adjusted.

[0106] In step 133, the method of reducing the logic level of the timing-critical path can be flexibly selected, for example, the logic between two registers can be evenly distributed in the timing-critical path, or the logic of the timing-critical path can be flattened. The above two methods are only examples, and their implementation methods are not limited.

[0107] In order to avoid congestion in a certain area of ​​the timing-critical path during the process of reducing the logic level, and to more reasonably reduce the logic level of the timing-critical path, the idea of ​​inserting registers in the area where the timing converges and the congestion is the lowest is introduced in step 133. Figure 5 The process of reducing the number of logic levels of the timing-critical path in step 133 may include steps 1331 to 1337 .

[0108] Step 1331, determine the connection coverage area of ​​the timing-critical path, and divide the connection coverage area into multiple sub-areas.

[0109] The connection coverage area (i.e., BoundingBox) is the area where primitives such as registers and lookup tables of the timing-critical path are located. The connection coverage area can be a regular geometric shape or an irregular shape. In addition, the way to divide the connection coverage area can be flexibly selected, for example, it can be divided into rectangles of equal area, or divided into irregular shapes of equal area, or divided according to the number of primitives, and the division method is not limited.

[0110] Each sub-area obtained after division has at least one primitive.

[0111] Step 1333, calculate the congestion and delay value of each sub-area.

[0112] Here, for each sub-area, the distribution information of the registers of the sub-area (which can be understood as the number and position of the registers, etc.) can be obtained, and the delay value and congestion degree of the sub-area can be calculated based on the distribution information. The method of calculating the delay value and congestion degree of the sub-area can be the same as the method of calculating the delay value and congestion degree of the timing path mentioned above. In addition, the number of registers can also be used as the congestion degree of the sub-area, and the method of calculating the congestion degree is not limited in this embodiment.

[0113] Step 1335: The sub-area whose delay value is not greater than the second convergence threshold is used as the convergence area.

[0114] It should be understood that the second convergence threshold is a preset value, such as a value specified in a timing constraint file. Different sub-areas may correspond to different second convergence thresholds or may have the same second convergence threshold, which is not limited in this embodiment.

[0115] Step 1337, taking the convergence area with the minimum congestion as the target area, and inserting a first-level virtual register into the target area.

[0116] Here, the virtual register may be inserted before any register in the target area, or may be inserted at a fixed position (such as an input end or an output end of the target area), and the implementation method is not limited.

[0117] Through the above steps 1331 to 1337, by analyzing the layout information of the registers in the coverage area of ​​the timing-critical path connection, a sub-area with converged timing and the lowest congestion is selected, and a first-level virtual register is inserted into the sub-area, which can reduce the logic level of the timing-critical path to reduce its delay value, and avoid inserting the virtual register into the sub-area that has not converged or has high congestion, resulting in the sub-area not converging. In this way, the logic level of the timing-critical path can be more reasonably lowered, and the adjustment speed can be increased, which helps to improve the wiring efficiency.

[0118] For a timing-critical path (i.e., a timing path with a delay value greater than the first convergence threshold), if its congestion is also greater than the preset congestion threshold (i.e., the timing-critical path is a congested path), the congestion is lowered through step 135. In order to reduce the congestion of the congested path without affecting the congestion and delay values ​​of other timing paths, the idea of ​​adjusting the position of a primitive in the congested path to the timing-converged timing path each time is introduced in step 135. Figure 6 , step 135 may include steps 1351 to 1355.

[0119] Step 1351 , select a primitive from the primitives corresponding to the logical resources of the congested path as a target object.

[0120] Step 1353 , from the timing paths of the designed circuit, select the timing path whose timing still converges after the target object is inserted and whose distance to the position of the target object is shortest as the hit path.

[0121] Here, we can first traverse the timing paths of timing convergence in order from near to far according to the distance between the connection coverage area of ​​the congested path and the connection coverage area of ​​each timing convergence. For each traversed timing path, pre-calculate the delay value after inserting a target object in the connection coverage area of ​​the timing path, and when the delay value is not greater than the corresponding first convergence threshold, take the timing path as the hit path.

[0122] When the constraint position of the target object is specified in the timing constraint file, the target object is inserted into the constraint position of the traversed timing path to calculate the delay value of the timing path after the target object is inserted.

[0123] Step 1355, adjust the position of the target object to the hit path.

[0124] The target object may be moved to any position of the hit path or to a specified position of the hit path, and the selection of the moving position is not restricted.

[0125] Through the above steps 1351 to 1355, a primitive of the congested path is inserted into a timing path that is close to the congested path and still has timing convergence after the primitive is inserted, so as to reduce the congestion of the congested path while avoiding affecting the timing convergence of the inserted timing path. Thus, it is helpful to perform routing quickly and efficiently.

[0126] On the basis of the above, in order to increase the probability of reducing the delay value of the timing path and to make the timing paths after routing have lower delay values ​​more quickly, the routing process of step 15 introduces the concept of giving priority to routing primitives of the timing paths with high congestion and no timing closure. Figure 7 , after step 11 and before step 15, step 14 may also be included.

[0127] Step 14: For each timing path, the priority corresponding to the delay value of the timing path is used as the connection priority of each primitive of the timing path.

[0128] On this basis, refer to Figure 8 In step 15, the wiring process may include the following steps 151 to 153.

[0129] Step 151, after all adjustments are completed, all primitives of the designed circuit are determined.

[0130] Step 153, according to the order of connection priority from high to low and the preset connection order, use the wiring resources to connect the primitives.

[0131] Here, the connection order of primitives can be included in the timing constraint file. Therefore, the connection of primitives with higher priority has higher selection of routing nodes, and the routing starts from the start node of the primitive with the highest connection priority, and selects the routing nodes that meet the timing constraint requirements for connection until it is connected to the end node to connect the two primitives.

[0132] For example, the primitive with the highest connection priority is selected from each unconnected primitive as the first primitive, and the primitive with the highest connection priority is selected from the remaining unconnected primitives as the second primitive. The output port of the first primitive is used as the starting point, and the input port of the second primitive is used as the end point. The wiring nodes that meet the timing constraint requirements are selected for connection. Then, the primitive with the highest connection priority is selected from the remaining unconnected primitives as the third primitive. The same principle as the connection between the first primitive and the second primitive is used to select the wiring nodes from the remaining wiring nodes to connect the output port of the second primitive and the input port of the third primitive. This cycle is repeated until all primitives are connected.

[0133] Through the above steps 151 to 153, the primitives of the timing paths with high estimated delay values ​​are given priority routing rights, that is, more routing nodes can be selected for use, so that the timing paths with high delay values ​​give priority to routing nodes that meet the timing constraints to complete the connection, thereby greatly reducing the delay value of the timing paths, so as to achieve timing convergence quickly and efficiently.

[0134] After the routing is completed through the above steps 151 to 153 , if it is determined in step 17 that at least one timing path has not reached timing closure, step 19 is executed.

[0135] In step 19, the method for judging whether the re-adjustment condition is met can be flexibly set. For example, the adjustment factor of each timing path where the timing has not converged can be calculated, and the weighted sum of each adjustment factor can be obtained to obtain a comprehensive factor, and the comparison relationship between the comprehensive factor and the adjustment threshold can be used to judge whether the re-adjustment condition is met. It is also possible to select any adjustment factor and judge whether the re-adjustment condition is met based on the comparison relationship between the adjustment factor and the adjustment threshold. It is also possible to input the primitives of each timing path where the timing has not converged into a pre-trained neural network model, and use the neural network model to generate a judgment result on whether the re-adjustment condition is met. The above methods are all examples, and their implementation methods are not limited.

[0136] In order to more accurately and quickly analyze and determine whether the readjustment condition is met, in step 19, a concept of using the primitive of the timing path with the highest delay value among the timing paths that have not reached timing closure to determine whether the readjustment condition is met is introduced.

[0137] By way of example, in step 19, a timing path with the highest current delay value is selected from among the timing paths whose timing has not converged as the target path, and it is determined whether the readjustment condition is met according to the primitive of the target path.

[0138] The readjustment condition may be determined based on whether the number of primitives or the position of primitives in the target path is greater than a corresponding threshold, or may be determined based on a preset rule. The above method is only an example, and the setting of the readjustment condition is not limited.

[0139] In order to more comprehensively judge the readjustability, the idea of ​​calculating the adjustment factor from two perspectives, namely the position of the primitive and the number of primitives, and comparing it with the corresponding threshold is introduced to realize the judgment. Fig. 9 The implementation process of step 19 may include steps 191 to 196.

[0140] Step 191 : Select the timing path with the highest current delay value from the timing paths that have not converged, as the target path.

[0141] Step 192, obtaining the position and quantity of each primitive of the target path, and the quantity of routing nodes of the target path.

[0142] Step 193 , taking the ratio of the location of the primitive to the preset timing constraint as the first factor, and taking the ratio of the number of primitives to the number of routing nodes as the second factor.

[0143] Step 194, determine whether the first factor and the second factor are both greater than their corresponding adjustment thresholds. If yes, execute step 195, if no, execute step 196.

[0144] Step 195: determine whether the readjustment condition is not met.

[0145] Step 196, determine whether the readjustment condition is met.

[0146] Through the above steps 191 to 196, the primitive of the timing path with the highest delay value among the timing paths that have not reached timing convergence is selected to determine whether the re-adjustment condition is met, thereby reducing the amount of calculation, improving the judgment speed, and also ensuring that the judgment result is representative and accurate. And through steps 192 to 196, the position of the primitive and the number of primitives are considered respectively, so that the judgment result is more comprehensive and the judgment accuracy is further improved.

[0147] Based on the same inventive concept as the above wiring method, refer to Fig.10 The embodiment of the present invention further provides a wiring device 30, which can be applied to Figure 1 In the processing device 120 of the development and design system 10 shown, the wiring apparatus 30 includes a pre-analysis module 310 , an optimization and adjustment module 320 , a wiring module 330 , a convergence judgment module 340 and a polling module 350 .

[0148] The pre-analysis module 310 is used to pre-analyze the timing paths of the designed circuit according to the layout results and the timing constraint information, and obtain the delay value and congestion degree of each timing path.

[0149] The optimization and adjustment module 320 is used to determine a timing-critical path from each timing path according to the delay value and the congestion degree, and adjust the logic levels and / or logic resources of the timing-critical path.

[0150] The wiring module 330 is used to perform wiring of the designed circuit after all adjustments are completed.

[0151] The convergence determination module 340 is used to determine whether all timing paths have reached timing convergence after routing is completed.

[0152] The polling module 350 is configured to determine whether a re-adjustment condition is satisfied based on the timing path that has not converged if at least one timing path has not converged.

[0153] The polling module 350 is also used to control the pre-analysis module 310 to return to execute the step of pre-analyzing the timing path of the design circuit according to the layout results and timing constraint information to obtain the delay value and congestion degree of each timing path when the readjustment conditions are met.

[0154] The above-mentioned wiring device 30, through the synergistic effect of the pre-analysis module 310, the optimization and adjustment module 320, the wiring module 330, the convergence judgment module 340 and the polling module 350, after the layout is completed, first adjusts the logic level and / or logic resource of the timing path with tight timing according to the pre-analysis result to reduce the congestion of the timing path and make the timing path reach timing convergence as much as possible, and then performs wiring on the adjusted basis to reduce wiring failures caused by congestion or timing non-convergence.

[0155] In addition, if there are still timing paths with unconverged timing after routing and the readjustment conditions are met, the step of analyzing the timing paths is re-entered to perform a new round of routing adjustments, that is, to remove the wires and re-route until all timing paths reach timing convergence or do not meet the readjustment conditions, then the routing is terminated. Thus, the problem that the traditional FPGA routing method cannot intervene in the timing pre-analysis results and cannot adjust the congestion is solved, the timing performance of the design is improved, and the risk of routing failure is greatly reduced, which helps to improve design efficiency and realize the transformation of design results.

[0156] For the specific implementation and effect of the wiring device 30, please refer to the description of the implementation of the wiring method above, such as, for the specific implementation and effect of the pre-analysis module 310, please refer to the description of the relevant content of step 11 above, for the specific implementation and effect of the optimization and adjustment module 320, please refer to the description of the relevant content of step 13 above, for the specific implementation and effect of the wiring module 330, please refer to the description of the relevant content of step 15 above, for the specific implementation and effect of the convergence judgment module 340, please refer to the description of the relevant content of step 17 above, for the specific implementation and effect of the polling module 350, please refer to the description of the relevant content of step 19 above, and they will not be repeated here.

[0157] In addition, each module of the wiring device 30 can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor 220 in the electronic device 20 in the form of hardware, or can be stored in the memory 210 of the electronic device 20 in the form of software, so that the processor 220 can call and execute the operations corresponding to each module to implement the wiring method provided above.

[0158] Based on the same inventive concept as the above-mentioned wiring method, an embodiment of the present invention also provides an electronic device 20, including a processor 220 and a memory 210, the memory 210 stores a computer program that can be executed by the processor 220, and the processor 220 can execute the computer program to implement the wiring method proposed in the embodiment of the present invention.

[0159] The embodiment of the present invention further provides a storage medium on which a computer program is stored. When the computer program is executed by the processor 220, the wiring method proposed in the embodiment of the present invention is implemented.

[0160] In summary, the wiring method, device, electronic device and storage medium provided by the embodiments of the present invention pre-analyze the layout results of the timing path, obtain the timing path that has not converged and the congested path that has not converged and has high congestion, and adjust the logic level and primitive position of the relevant timing path to reduce the congestion of the timing path and achieve timing convergence. It has at least the following beneficial effects:

[0161] (1) It solves the problem that the traditional FPGA wiring method cannot intervene in the timing pre-analysis results and cannot adjust the congestion degree;

[0162] (ii) It reduces the risk of wiring failure and effectively improves the wiring effect.

[0163] In several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0164] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0165] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk.

[0166] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A wiring method, characterized in that: The method comprises: According to the layout results and timing constraint information, the timing path of the designed circuit is pre-analyzed to obtain the delay value and congestion of each timing path; Determine a timing-critical path from each of the timing paths according to the delay value and the congestion degree, and adjust the logic levels and / or logic resources of the timing-critical path; After all adjustments are completed, the designed circuit is wired; After the wiring is completed, determining whether all the timing paths have reached timing closure; If not, judging whether a readjustment condition is met according to the timing path whose timing has not converged; When the readjustment condition is met, the step of performing a preliminary analysis on the timing paths of the design circuit according to the layout result and the timing constraint information to obtain the delay value and congestion degree of each timing path is returned to be executed.

2. The wiring method according to claim 1, characterized in that: The step of determining a tight timing path from each of the timing paths according to the delay value and the congestion degree, and adjusting the logic level and / or logic resource of the tight timing path comprises: From the timing paths, select a timing path whose delay value is greater than a first convergence threshold as a timing-critical path; For each of the timing-critical paths, lowering the logic level of the timing-critical path; The timing-critical path whose congestion degree is greater than a congestion threshold is taken as a congested path, and logical resources of the congested path are adjusted.

3. The wiring method according to claim 2, characterized in that: The step of reducing the logic level of the timing-critical path includes: Determine a connection coverage area of ​​the timing-critical path, and divide the connection coverage area into a plurality of sub-areas; Calculating the congestion and delay value of each of the sub-areas; The sub-area in which the delay value is not greater than the second convergence threshold is used as the convergence area; The convergence area with the minimum congestion is taken as a target area, and a first-level virtual register is inserted into the target area.

4. The wiring method according to claim 2, characterized in that: The step of adjusting the logical resources of the congested path comprises: Selecting one of the primitives corresponding to the logical resources of the congested path as a target object; From the timing paths of the designed circuit, a timing path whose timing still converges after the target object is inserted and whose distance to the position of the target object is the shortest is selected as a hit path; The position of the target object is adjusted to the hit path.

5. The wiring method according to any one of claims 1 to 4, characterized in that: After the step of pre-analyzing the timing paths of the designed circuit according to the layout results and the timing constraint information to obtain the delay value and congestion of each timing path, and before the step of routing the designed circuit after completing all adjustments, the method further includes: For each of the timing paths, taking the priority corresponding to the delay value of the timing path as the connection priority of each primitive of the timing path; After all adjustments are completed, the step of performing wiring of the designed circuit includes: After completing all adjustments, determining all primitives of the designed circuit; According to the order of the connection priorities from high to low and the preset connection order, the primitive connections are performed using the wiring resources.

6. The wiring method according to any one of claims 1 to 4, characterized in that: The step of judging whether a readjustment condition is met according to the timing path whose timing has not converged comprises: From the timing paths whose timing has not converged, select the timing path with the highest current delay value as the target path; According to the primitive of the target path, it is determined whether a readjustment condition is met.

7. The wiring method according to claim 6, characterized in that: The step of judging whether the readjustment condition is met according to the primitive of the target path comprises: Obtaining the position and quantity of each primitive of the target path and the quantity of routing nodes of the target path; Using a ratio of the location of the primitive to a preset timing constraint as a first factor, and using a ratio of the number of the primitives to the number of the routing nodes as a second factor; Determine whether the first factor and the second factor are both greater than their respective corresponding adjustment thresholds; If so, it is determined that the readjustment condition is not satisfied; If not, it is determined that the readjustment condition is met.

8. A wiring device, characterized in that: It includes pre-analysis module, optimization and adjustment module, wiring module, convergence judgment module and polling module; The pre-analysis module is used to pre-analyze the timing paths of the designed circuit according to the layout results and the timing constraint information to obtain the delay value and congestion degree of each timing path; The optimization and adjustment module is used to determine a timing-critical path from each of the timing paths according to the delay value and the congestion degree, and adjust the logic levels and / or logic resources of the timing-critical path; The wiring module is used to perform wiring of the designed circuit after all adjustments are completed; The convergence judgment module is used to judge whether all the timing paths have reached timing convergence after the wiring is completed; The polling module is configured to determine whether a re-adjustment condition is met according to the timing path whose timing has not converged if at least one of the timing paths has not converged; The polling module is also used to control the pre-analysis module to return to execute the step of pre-analyzing the timing path of the designed circuit according to the layout results and timing constraint information to obtain the delay value and congestion degree of each timing path when the readjustment condition is met.

9. An electronic device, characterized in that: The invention comprises a processor and a memory, wherein the memory stores a computer program executable by the processor, and the processor can execute the computer program to implement the wiring method according to any one of claims 1 to 7.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the wiring method according to any one of claims 1 to 7 is implemented.

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