Pixel circuit, display panel and driving method of pixel circuit

Abstract

The invention relates to a pixel circuit, a display panel and a driving method of the pixel circuit. The pixel circuit comprises a driving transistor, a threshold compensation module, a first reset module and a compensation module. The first end of the compensation module is connected with a target node, the second end of the compensation module is used for receiving a target signal, the target node comprises at least one of an intermediate node of the threshold compensation module and an intermediate node of the first reset module, and the target signal comprises a first target signal and a second target signal; the potential of the first target signal received by the second end of the compensation module in the blanking stage is higher than the potential of the second target signal received by the second end of the compensation module in the holding stage, and the pixel circuit can improve the display performance of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel circuit, a display panel, and a driving method for the pixel circuit. Background Art

[0002] As an important part of the information industry, display technology has played an important role in the development of information technology. With the development of display technology, organic light emitting diode display panels and other types of display panels have been widely used.

[0003] Currently, the display performance of display panels is poor. Summary of the invention

[0004] Based on this, it is necessary to provide a pixel circuit, a display panel and a driving method of the pixel circuit, aiming to improve the display performance of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a pixel circuit, wherein the pixel circuit comprises:

[0006] Driver transistor;

[0007] A threshold compensation module, wherein a first end of the threshold compensation module is connected to a first electrode of the driving transistor, a second end of the threshold compensation module is connected to a gate of the driving transistor, and a control end of the threshold compensation module is used to receive a first scanning signal;

[0008] a first reset module, wherein a first end of the first reset module is connected to the gate of the driving transistor, a second end of the first reset module is used to receive a first reset signal, and a control end of the first reset module is used to receive a second scanning signal;

[0009] A compensation module, wherein a first end of the compensation module is connected to a target node, and a second end of the compensation module is used to receive a target signal; wherein the target node includes at least one of an intermediate node of the threshold compensation module and an intermediate node of the first reset module, and the target signal includes a first target signal and a second target signal;

[0010] The potential of the first target signal received by the second end of the compensation module in the blanking phase is higher than the potential of the second target signal received by the second end of the compensation module in the holding phase.

[0011] In a second aspect, an embodiment of the present application further provides a display panel, which includes the pixel circuit provided in the first aspect.

[0012] In a third aspect, an embodiment of the present application further provides a method for driving a pixel circuit, which is applied to the pixel circuit provided in the first aspect; the method comprises:

[0013] In the blanking phase, providing a first target signal to the second terminal of the compensation module;

[0014] In the holding phase, providing a second target signal to the second end of the compensation module;

[0015] The potential of the first target signal is higher than the potential of the second target signal.

[0016] The pixel circuit provided in the embodiment of the present application includes a driving transistor, a threshold compensation module, a first reset module and a compensation module, wherein the first end of the threshold compensation module is connected to the first electrode of the driving transistor, the second end of the threshold compensation module is connected to the gate of the driving transistor, the control end of the threshold compensation module is used to receive a first scanning signal, the first end of the first reset module is connected to the gate of the driving transistor, the second end of the first reset module is used to receive the first reset signal, the control end of the first reset module is used to receive a second scanning signal, and the first end of the compensation module is connected to at least one of the intermediate node of the threshold compensation module and the intermediate node of the first reset module. In the present application, the pixel circuit controls the second end of the compensation module to receive a first target signal with a higher potential in the blanking stage, and controls the second end of the compensation module to receive a second target signal with a lower potential in the holding stage. The potential of the intermediate node of the threshold compensation module and / or the intermediate node of the first reset module can be raised in the holding stage to prevent the gate of the driving transistor from leaking to the intermediate node of the threshold compensation module and the intermediate node of the first reset module in the holding stage, thereby stabilizing the gate potential of the driving transistor, avoiding the flickering problem of the display panel, and improving the display performance of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a circuit structure schematic diagram of a pixel circuit in the related art;

[0018] Figure 2 A schematic diagram of a circuit structure of a pixel circuit provided in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present application;

[0020] FIG4 is a schematic diagram of a circuit structure of another pixel circuit provided in an embodiment of the present application;

[0021] FIG5 is a schematic diagram of a circuit structure of another pixel circuit provided in an embodiment of the present application;

[0022] FIG6 is a diagram showing a proportional relationship between a potential of a target signal and a display brightness value provided by an embodiment of the present application;

[0023] FIG7 is a proportional relationship diagram of another target signal potential and display brightness value provided by an embodiment of the present application;

[0024] FIG8 is a schematic diagram of a circuit structure of another pixel circuit provided in an embodiment of the present application;

[0025] FIG9 is a schematic diagram of a circuit structure of another pixel circuit provided in an embodiment of the present application;

[0026] FIG10 is a schematic flow chart of a driving method for a pixel circuit provided in an embodiment of the present application;

[0027] FIG11 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0028] Fig.12 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0029] Explanation of the reference numerals: 11 - threshold compensation module, 12 - first reset module, 13 - compensation module, 14 - data writing module, 15 - bias adjustment module, 16 - second reset module, 17 - first light-emitting control module, 18 - second light-emitting control module. DETAILED DESCRIPTION

[0030] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0032] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there may be intervening elements. Further, when a layer is referred to as being "under" another layer, it can be directly under or there may be one or more intervening elements. It is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there may be one or more intervening elements.

[0033] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0034] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0035] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately", "approximately" or "substantially" can mean within one or more standard deviations, which are not limited here.

[0036] Furthermore, in the specification, the phrase “planar distribution schematic diagram” refers to a drawing when a target portion is viewed from above, and the phrase “cross-sectional schematic diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0037] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0038] As described in the background technology section, the display panel in the related art is prone to flickering when displaying at a low frequency. The inventors found that the reason for the above phenomenon is that Figure 1 , Figure 1 It is a structural diagram of a pixel circuit in the related technology. After the first reset process and the data writing process in the refresh phase of the pixel circuit are completed, the scan signal SP1 and the scan signal SP2 will jump from a low level state to a high level state, respectively, thereby coupling the potentials of the N6 and N5 nodes high, respectively. In the subsequent blanking phase and holding phase, since the potentials of the N6 and N5 nodes are coupled high, the N6 and N5 nodes will leak to the N1 node, that is, the gate of the driving transistor M3, causing the gate potential of the driving transistor M3 to rise. As the holding phase continues, the brightness of the display panel will gradually decrease, causing the display panel to flicker.

[0039] Based on the above technical problems, the inventors have found that the flickering phenomenon of the display panel can be improved by setting a compensation module at the N6 and / or N5 nodes. Based on this, the inventors have further studied the technical solution of the embodiment of the present application. Specifically, the pixel circuit provided in the embodiment of the present application includes: a driving transistor; a threshold compensation module, a first end of the threshold compensation module is connected to the first pole of the driving transistor, a second end of the threshold compensation module is connected to the gate of the driving transistor, and a control end of the threshold compensation module is used to receive a first scanning signal; a first reset module, a first end of the first reset module is connected to the gate of the driving transistor, a second end of the first reset module is used to receive a first reset signal, and a control end of the first reset module is used to receive a second scanning signal; a compensation module, a first end of the compensation module is connected to a target node, and a second end of the compensation module is used to receive a target signal; wherein the target node includes at least one of an intermediate node of the threshold compensation module and an intermediate node of the first reset module, and the target signal includes a first target signal and a second target signal; wherein the potential of the first target signal received at the second end of the compensation module in the blanking stage is higher than the potential of the second target signal received at the second end of the compensation module in the holding stage. By adopting the above technical solution, by setting a compensation module at the intermediate node of the threshold compensation module of the pixel circuit and / or the intermediate node of the first reset module, the potential of the first end of the compensation module can be raised in the blanking stage, and the potential of the first end of the compensation module can be lowered in the holding stage, thereby avoiding leakage of the intermediate node of the threshold compensation module and the intermediate node of the first reset module to the driving transistor, thereby improving the flickering phenomenon of the display panel.

[0040] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be described clearly and completely below in conjunction with the drawings in the embodiments of this application. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0041] In an exemplary embodiment, see Figure 2 The present application provides a pixel circuit, which includes: a driving transistor T1, a threshold compensation module 11, a first reset module 12 and a compensation module 13.

[0042] The first end of the threshold compensation module 11 is connected to the first electrode of the driving transistor, the second end of the threshold compensation module 11 is connected to the gate of the driving transistor, and the control end of the threshold compensation module 11 is used to receive the first scanning signal S1. The first end of the first reset module 12 is connected to the gate of the driving transistor T1, the second end of the first reset module 12 is used to receive the first reset signal Vref1, and the control end of the first reset module 12 is used to receive the second scanning signal S2. The first end of the compensation module 13 is connected to the target node, and the second end of the compensation module 13 is used to receive the target signal SX; wherein the target node includes at least one of the intermediate node N5 of the threshold compensation module 11 and the intermediate node N6 of the first reset module 12, and the target signal SX includes the first target signal and the second target signal. wherein, the potential of the first target signal received at the second end of the compensation module 13 in the blanking stage is higher than the potential of the second target signal received at the second end of the compensation module 13 in the holding stage.

[0043] In this embodiment, the pixel circuit is an LTPS type pixel circuit, and the transistor in the pixel circuit is a P-type transistor. The pixel circuit of the present application has a refresh phase, a blanking phase, and a holding phase. In the refresh phase, the first reset module 12 is turned on so that the first reset signal Vref1 resets the gate of the driving transistor T1. After that, the first reset module 12 is turned off, and the threshold compensation module 11 is turned on to perform threshold compensation on the gate of the driving transistor T1. It can be understood that after the first reset process and the threshold compensation process are completed, the second scanning signal S2 and the first scanning signal S1 will jump from a low level to a high level respectively to turn off the first reset module 12 and the threshold compensation module 11 respectively. When the second scanning signal S2 jumps from a low level to a high level, the potential of the middle node N6 of the first reset module 12 will be coupled high. Similarly, when the first scanning signal S1 jumps from a low level to a high level, the potential of the middle node N5 of the threshold compensation module 11 will be coupled high. Since the duration of the refresh phase in the pixel circuit is greater than the duration of the blanking phase, and the duration of the holding phase is greater than the duration of the refresh phase, that is, when the potential of the middle node N6 of the first reset module 12 and the middle node N5 of the threshold compensation module 11 are coupled high, the gate of the driving transistor T1 will be mainly leaked during the holding phase. In one example, the duration of the blanking phase is less than one twentieth of the duration of the refresh phase, and the duration of the holding phase is greater than or equal to ten times the duration of the refresh phase.

[0044] Therefore, in the present application, a compensation module 13 is provided at the intermediate node N5 of the threshold compensation module 11 and / or the intermediate node N6 of the first reset module 12, and the compensation module 13 may be a capacitor. In the blanking stage of the pixel circuit, the potential of the intermediate node N5 and / or the intermediate node N6 is temporarily pulled up by the compensation module 13, and then, in the main leakage stage of the pixel circuit, that is, the holding stage, the potential of the intermediate node N5 of the threshold compensation module 11 and / or the intermediate node N6 of the first reset module 12 is pulled down by the compensation module 13, so that the intermediate node N5 and the intermediate node N6 can be prevented from leaking electricity to the gate of the driving transistor T1, and the gate potential of the driving transistor T1 is prevented from continuously rising with the leakage current, thereby preventing the display panel from flickering.

[0045] The pixel circuit provided in the embodiment of the present application includes a driving transistor, a threshold compensation module, a first reset module and a compensation module, wherein the first end of the threshold compensation module is connected to the first electrode of the driving transistor, the second end of the threshold compensation module is connected to the gate of the driving transistor, the control end of the threshold compensation module is used to receive a first scanning signal, the first end of the first reset module is connected to the gate of the driving transistor, the second end of the first reset module is used to receive the first reset signal, the control end of the first reset module is used to receive a second scanning signal, and the first end of the compensation module is connected to at least one of the intermediate node of the threshold compensation module and the intermediate node of the first reset module. In the present application, the pixel circuit controls the second end of the compensation module to receive a first target signal with a higher potential in the blanking stage, and controls the second end of the compensation module to receive a second target signal with a lower potential in the holding stage. The potential of the intermediate node of the threshold compensation module and / or the intermediate node of the first reset module can be raised in the holding stage to prevent the gate of the driving transistor from leaking to the intermediate node of the threshold compensation module and the intermediate node of the first reset module in the holding stage, thereby stabilizing the gate potential of the driving transistor, avoiding the flickering problem of the display panel, and improving the display performance of the display panel.

[0046] In an exemplary embodiment, when the voltage difference between the gate voltage of the driving transistor T1 and the first reset signal is greater than a preset threshold, the target node includes an intermediate node of the threshold compensation module or an intermediate node of the first reset module.

[0047] In the application, during the design stage of the pixel circuit, relevant technical personnel will predetermine the size of the scanning signal, reset signal, light control signal, data signal, etc. required by the pixel circuit. Therefore, during the design stage of the pixel circuit, relevant technical personnel can determine how to design the compensation module 13 in the pixel circuit based on the size of the above signals.

[0048] In one example, the relevant technicians can determine how to design the compensation module 13 in the pixel circuit according to the formula Vn1-Vref1>1 / n*(VGH-VGL), where Vn1 is the gate voltage of the driving transistor, the size of Vn1 is mainly determined by Vdata-Vth, Vdata is the data signal, Vth is the threshold voltage of the driving transistor T1, Vref1 is the first reset signal, VGH is a high level signal, VGL is a low level signal, 1 / n*(VGH-VGL) is a preset threshold, and 0<1 / n<1. In the application, the size of 1 / n can be determined by the relevant technicians as needed, as long as 0<1 / n<1 is satisfied.

[0049] When the voltage difference between the gate voltage Vn1 of the driving transistor T1 and the first reset signal Vref1 is greater than the preset threshold value 1 / n*(VGH-VGL), the compensation module 13 can be set only at the middle node N5 of the threshold compensation module or the middle node N6 of the first reset module. This is because when the voltage difference between the gate voltage of the driving transistor T1 and the first reset signal is greater than the preset threshold value, it indicates that the potential of the first reset signal Vref1 may be low. After the first reset process is completed, the middle node N5 of the threshold compensation module will not be coupled very high. If the compensation module 13 is set at the middle node N5 of the threshold compensation module and the middle node N6 of the first reset module, the potential of the middle node N6 of the first reset module is pulled down, and the gate of the driving transistor T1 may leak to the middle node N5 and the middle node N6. At this time, as the holding stage continues, the gate potential of the driving transistor T1 gradually decreases, the brightness of the light-emitting element gradually increases, and the display panel will also cause flickering. Therefore, in the present application, when the voltage difference between the gate voltage of the driving transistor T1 and the first reset signal is greater than a preset threshold, the compensation module 13 is only set at the intermediate node N5 of the threshold compensation module or the intermediate node N6 of the first reset module to alleviate the possible leakage of the gate of the driving transistor T1 to the intermediate node N5 and the intermediate node N6.

[0050] In an exemplary embodiment, see Figure 3 4 , the compensation module 13 includes a first capacitor C1, a first end of the first capacitor C1 is connected to a target node, and a second end of the first capacitor C1 is used to receive a target signal SX; wherein the target node includes an intermediate node N5 of the threshold compensation module 11 or an intermediate node N6 of the first reset module 12.

[0051] In one example, Figure 3FIG4 is a schematic diagram of a pixel circuit when the target node is the middle node N6 of the first reset module. In another example, FIG4 is a schematic diagram of a pixel circuit when the target node is the middle node N5 of the threshold compensation module. When the voltage difference between the gate voltage Vn1 of the driving transistor T1 and the first reset signal Vref1 is greater than the preset threshold 1 / n*(VGH-VGL), the first capacitor C1 can be set only at the middle node N5 of the threshold compensation module 11 or the middle node N6 of the first reset module 12 to pull down the potential of the middle node N5 or the middle node N6 in the holding stage, avoid leakage from the middle node N5 or the middle node N6 to the gate of the driving transistor T1, and alleviate the possible leakage of the gate of the driving transistor T1 to the middle node N5 and the middle node N6.

[0052] In an exemplary embodiment, when the voltage difference between the gate voltage of the driving transistor T1 and the first reset signal Vref1 is less than or equal to a preset threshold, the target node includes an intermediate node of the threshold compensation module and an intermediate node of the first reset module.

[0053] It can be understood that when the voltage difference between the gate voltage Vn1 of the driving transistor T1 and the first reset signal Vref1 is less than or equal to the preset threshold value 1 / n*(VGH-VGL), it indicates that the potential of the first reset signal Vref1 may be relatively high. After the first reset process and the threshold compensation process are completed, the intermediate node N5 of the threshold compensation module and the intermediate node N6 of the first reset module will leak to the gate of the driving transistor T1 due to the high coupling. Therefore, the compensation module 13 can be set at the intermediate node N5 of the threshold compensation module 11 and the intermediate node N6 of the first reset module 12 at the same time.

[0054] In an exemplary embodiment, referring to FIG5 , the compensation module includes a second capacitor C2 and a third capacitor C3, and the target node includes an intermediate node N5 of the threshold compensation module 11 and an intermediate node N6 of the first reset module 12. The first end of the second capacitor C2 is connected to the intermediate node N5 of the threshold compensation module 11, and the second end of the second capacitor C2 is used to receive the target signal SX. The first end of the third capacitor C3 is connected to the intermediate node N6 of the first reset module 12, and the second end of the third capacitor C3 is used to receive the target signal SX.

[0055] In one example, when the voltage difference between the gate voltage Vn1 of the driving transistor T1 and the first reset signal Vref1 is less than or equal to the preset threshold value 1 / n*(VGH-VGL), a second capacitor C2 may be set at the intermediate node N5 of the threshold compensation module 11, and a third capacitor C3 may be set at the intermediate node N6 of the first reset module 12. After the refresh phase is over, the potential of the intermediate node N5 is temporarily pulled up by the second capacitor C2, and the potential of the intermediate node N6 is temporarily pulled up by the third capacitor C3. After that, in the main leakage phase of the pixel circuit, i.e., the holding phase, the potential of the intermediate node N5 is pulled down by the second capacitor C2, and the potential of the intermediate node N6 is pulled down by the third capacitor C3, so as to avoid the intermediate nodes N5 and N6 from leaking to the gate of the driving transistor T1, so as to avoid the gate potential of the driving transistor T1 from continuously rising with the leakage current, thereby avoiding flickering of the display panel and improving the display performance of the display panel.

[0056] In an exemplary embodiment, the potential difference between the potential of the first target signal Va and the potential of the second target signal Vb is positively correlated with the display brightness value DBV of the pixel circuit.

[0057] In application, as the display brightness value (DBV) increases, the gate potential of the driving transistor T1 in the pixel circuit needs to be lower. It can be understood that the lower the gate potential of the driving transistor T1 in the pixel circuit, the easier it is for the intermediate node N5 and the intermediate node N6 to leak to the gate of the driving transistor T1, thereby reducing the brightness of the display panel. Therefore, the higher the display brightness value DBV of the pixel circuit is set in this application, the greater the potential difference (Va-Vb) between the potential of the first target signal Va and the potential of the second target signal Vb. Specifically, when the display brightness value DBV increases, the gate potential of the driving transistor T1 decreases, and the first target signal Va needs to be higher and the second target signal Vb needs to be lower; when the display brightness value DBV decreases, the gate potential of the driving transistor T1 increases, and the first target signal Va needs to be lower and the second target signal Vb needs to be higher.

[0058] In an exemplary embodiment, referring to FIG. 6 , the potential of the first target signal Va is positively correlated with the display brightness value, and the potential of the second target signal Vb is negatively correlated with the display brightness value.

[0059] As can be seen from Figure 6, the potential of the first target signal Va can be set to increase with the increase of the display brightness value, and the potential of the second target signal Vb can be set to decrease with the increase of the display brightness value, so as to ensure that the potential difference between the potential of the first target signal Va and the potential of the second target signal Vb is in positive proportion to the display brightness value DBV of the pixel circuit.

[0060] In an exemplary embodiment, referring to FIG. 7 , when the display brightness value DBV is less than the preset brightness threshold DBV~, the potential of the second target signal Vb is negatively correlated with the display brightness value. When the display brightness value is greater than or equal to the preset brightness threshold DBV~, the potential of the second target signal Vb remains unchanged. When the display brightness value DBV is greater than or equal to the preset brightness threshold DBV~, the rate of change of the potential of the first target signal Va is greater than the rate of change of the potential of the first target signal Va when the display brightness value DBV is less than the preset brightness threshold DBV~.

[0061] In another example, since the driver IC of the display panel may not be able to provide a voltage that is too low, the potential of the first target signal Va and the potential of the second target signal Vb may not change synchronously, and a preset brightness threshold DBV~ may be set. When the display brightness value DBV is less than the preset brightness threshold DBV~, the potential of the first target signal Va increases with the increase of the display brightness value, and the potential of the second target signal Vb is set to decrease with the increase of the display brightness value, so as to ensure that the potential difference between the potential of the first target signal Va and the potential of the second target signal Vb is in positive proportion to the display brightness value DBV of the pixel circuit; when the display brightness value DBV is greater than or equal to the preset brightness threshold DBV~, the potential of the second target signal Vb may be kept unchanged, and the rate of change of the potential of the first target signal Va may be increased, so as to maintain the proportional relationship between the potential difference between the potential of the first target signal Va and the potential of the second target signal Vb and the display brightness value DBV of the pixel circuit.

[0062] In an exemplary embodiment, please refer to Figure 2 5 , the threshold compensation module 11 includes: a first threshold compensation transistor T2 - 1 and a second threshold compensation transistor T2 - 2 .

[0063] The first electrode of the first threshold compensation transistor T2-1 is connected to the first electrode of the driving transistor T1, and the gate of the first threshold compensation transistor T2-1 is used to receive the first scanning signal S1. The first electrode of the second threshold compensation transistor T2-2 is connected to the second electrode of the first threshold compensation transistor T2-1, the second electrode of the second threshold compensation transistor T2-2 is connected to the gate of the driving transistor T1, and the gate of the second threshold compensation transistor T2-2 is used to receive the first scanning signal S1. Among them, the middle node N5 of the threshold compensation module 11 is the second electrode of the first threshold compensation transistor T2-1.

[0064] In the application, the refresh phase of the pixel circuit may include a threshold compensation process. When the threshold compensation process is completed, the first scanning signal S1 jumps from a low level to a high level, which will couple the potential of the intermediate node N5 of the threshold compensation module 11. By setting a compensation module 13 at the intermediate node N5 of the threshold compensation module 11, and providing a first target signal Va to the second end of the compensation module 13 in the blanking phase, and providing a second target signal Vb to the second end of the compensation module 13 in the holding phase, and controlling the potential difference between the potential of the first target signal Va and the potential of the second target signal Vb to be in positive proportion to the display brightness value DBV of the pixel circuit, the intermediate node N5 of the threshold compensation module 11 can be suppressed from leaking to the gate of the driving transistor T1, and no matter how large the display brightness value DBV of the pixel circuit is, the intermediate node N5 can be effectively suppressed from leaking to the gate of the driving transistor T1, thereby improving the display performance of the display panel.

[0065] In an exemplary embodiment, please refer to Figure 2 5 , the first reset module 12 includes: a first A reset transistor T3 - 1 and a first B reset transistor T3 - 2 .

[0066] The first electrode of the first A reset transistor T3-1 is connected to the gate of the driving transistor T1, and the gate of the first A reset transistor T3-1 is used to receive the second scanning signal S2. The first electrode of the first B reset transistor T3-2 is connected to the second electrode of the first A reset transistor T3-1, the second electrode of the first B reset transistor T3-2 is used to receive the first reset signal Vref1, and the gate of the first B reset transistor T3-2 is used to receive the second scanning signal S2. Among them, the middle node N6 of the first reset module 12 is the second electrode of the first A reset transistor T3-1.

[0067] The refresh phase of the pixel circuit may also include a first reset process. After the first reset process is completed, the second scanning signal S2 jumps from a low level to a high level, which will couple the potential of the intermediate node N6 of the first reset module 12 to a high level. By setting a compensation module 13 at the intermediate node N6 of the first reset module 12, and providing a first target signal Va to the second end of the compensation module 13 in the blanking phase, and providing a second target signal Vb to the second end of the compensation module 13 in the holding phase, and controlling the potential difference between the potential of the first target signal Va and the potential of the second target signal Vb to be in direct proportion to the display brightness value DBV of the pixel circuit, the leakage from the intermediate node N6 of the first reset module 12 to the gate of the driving transistor T1 can be suppressed, and no matter how large the display brightness value DBV of the pixel circuit is, the leakage from the intermediate node N6 of the first reset module 12 to the gate of the driving transistor T1 can be effectively suppressed, thereby improving the display performance of the display panel.

[0068] In an exemplary embodiment, referring to FIG. 8 , the pixel circuit further includes a data writing module 14 .

[0069] The first end of the data writing module 14 is connected to the second electrode of the driving transistor T1, the second end of the data writing module 14 is used to receive the data signal Vdata, and the control end of the data writing module 14 is used to receive the first scanning signal S1; wherein, in the refresh phase, the target signal also includes the data signal Vdata.

[0070] The data writing module 14 includes a data writing transistor T4, a first electrode of the data writing transistor T4 is connected to the first electrode of the driving transistor T1, a second electrode of the data writing transistor T4 is used to receive a data signal Vdata, and a gate of the data writing transistor T4 is used to receive a first scanning signal S1.

[0071] In one example, a new signal line may be added to the display panel to provide the first target signal Va to the second end of the compensation module 13 in the blanking phase, and to provide the second target signal Vb to the second end of the compensation module 13 in the holding phase. Alternatively, the data signal line in the display panel may be directly reused, and the data signal line may be controlled to provide the data signal Vdata to the pixel circuit in the refresh phase, to provide the first target signal Va to the second end of the compensation module 13 in the blanking phase, and to provide the second target signal Vb to the second end of the compensation module 13 in the holding phase.

[0072] In an exemplary embodiment, referring to FIG. 9 , the pixel circuit further includes a bias adjustment module 15 , a second reset module 16 , a first light emission control module 17 , a second light emission control module 18 and a storage capacitor Cst.

[0073] Among them, the first end of the bias adjustment module 15 is used to receive the bias adjustment signal DHV, the second end of the bias adjustment module 15 is connected to the first electrode of the driving transistor, and the control end of the bias adjustment module 15 is used to receive the third scanning signal S3. The first end of the second reset module 16 is used to receive the second reset signal Vref2, the second end of the second reset module 16 is connected to the first electrode of the light-emitting element D, and the control end of the second reset module 16 is used to receive the third scanning signal S3. The first end of the first light-emitting control module 17 is used to receive the first power supply signal PVDD, the second end of the first light-emitting control module 17 is connected to the first electrode of the driving transistor T1, and the control end of the first light-emitting control module 17 is used to receive the light-emitting control signal EM. The first end of the second light-emitting control module 18 is connected to the second electrode of the driving transistor T1, the second end of the second light-emitting control module 18 is connected to the first electrode of the light-emitting element D, and the control end of the second light-emitting control module 18 is used to receive the light-emitting control signal EM.

[0074] Specifically, the bias adjustment module 15 includes a bias adjustment transistor T5, the first electrode of the bias adjustment transistor T5 is used to receive the bias adjustment signal DHV, the second electrode of the bias adjustment transistor T5 is respectively connected to the first electrode of the data writing transistor T4 and the first electrode of the driving transistor T1, and the gate of the bias adjustment transistor T5 is used to receive the third scanning signal S3. The second reset module 16 includes a second reset transistor 16, the first electrode of the second reset transistor 16 is used to receive the second reset signal Vref2, the second electrode of the second reset transistor 16 is connected to the first electrode of the light emitting element D, and the control end of the second reset transistor 16 is used to receive the third scanning signal S3. The first light control module 17 includes a first light emitting transistor T7, the first electrode of the first light emitting transistor T7 is used to receive the first power supply signal PVDD, the second electrode of the first light emitting transistor T7 is connected to the first electrode of the driving transistor T1, and the gate of the first light emitting transistor T7 is used to receive the light control signal EM, so that the first light emitting transistor T7 is turned on or off in response to the light control signal EM. The second light emitting control module 18 includes a second light emitting transistor T8, a first electrode of the second light emitting transistor T8 is connected to the second electrode of the driving transistor T1, a second electrode of the second light emitting transistor T8 is connected to the first electrode of the light emitting element F, and a gate of the second light emitting transistor T8 is used to receive a light emitting control signal EM so that the second light emitting transistor T8 is turned on or off in response to the light emitting control signal EM.

[0075] In an exemplary embodiment, referring to FIG. 10 , the present application provides a driving method for a pixel circuit, which is applied to the pixel circuit in any of the above embodiments; the driving method includes step S1001 and step S1002.

[0076] S1001: In a blanking phase, providing a first target signal to a second end of a compensation module.

[0077] S1002: In the holding phase, providing a second target signal to the second end of the compensation module.

[0078] In a detailed embodiment, please continue to refer to 9, and take the case where the voltage difference between the gate voltage Vn1 of the driving transistor T1 in the pixel circuit and the first reset signal Vref1 is less than or equal to the preset threshold value 1 / n*(VGH-VGL), that is, the compensation module 13 is set at the middle node N5 of the threshold compensation module 11 and the middle node N6 of the first reset module 12 in the pixel circuit as an example for explanation.

[0079] The pixel circuit has a refresh phase, a blanking phase and a hold phase. In the refresh phase, the first A reset transistor T3-1 and the first B reset transistor T3-2 are turned on so that the first reset signal Vref1 resets the gate of the driving transistor T1. Thereafter, the first A reset transistor T3-1 and the first B reset transistor T3-2 are turned off, and the data writing transistor T4, the first threshold compensation transistor T2-1 and the second threshold compensation transistor T2-2 are turned on to write the data signal Vdata to the gate of the driving transistor T1. It can be understood that after the first reset process and the data writing process in the brush line stage are completed, the second scan signal S2 and the first scan signal S1 will jump from a low level to a high level respectively, so as to turn off the first A reset transistor T3-1, the first B reset transistor T3-2, the first threshold compensation transistor T2-1 and the second threshold compensation transistor T2-2 respectively. When the second scan signal S2 jumps from a low level to a high level, the potential of the intermediate node N6 will be coupled high. Similarly, when the first scan signal S1 jumps from a low level to a high level, the potential of the intermediate node N5 will be coupled high. When the potentials of the intermediate nodes N5 and N6 are coupled high, the intermediate nodes N5 and N6 will leak to the gate of the driving transistor T1. Since the duration of the refresh stage in the pixel circuit is greater than the duration of the blanking stage, and the duration of the holding stage is greater than the duration of the refresh stage, the leakage phenomenon mainly occurs in the holding stage.

[0080] The present application provides the first target signal Va to the second end of the second capacitor C2 and the third capacitor C3 respectively in the blanking stage, and provides the second target signal Vb to the second end of the second capacitor C2 and the third capacitor C3 in the holding stage, so as to lower the potential of the intermediate node N5 and the intermediate node N6, thereby preventing the intermediate node N5 and the intermediate node N6 from leaking to the gate of the driving transistor T1. In addition, the present application also sets the potential difference between the potential of the first target signal Va and the potential of the second target signal Vb to be in direct proportion to the display brightness value DBV of the pixel circuit, further ensuring that no matter the display brightness value DBV of the pixel circuit, the intermediate node N5 and the intermediate node N6 will not leak to the gate of the driving transistor T1, thereby further ensuring the display performance of the display panel.

[0081] Based on the same application concept, as shown in FIG11 , the embodiment of the present application further provides a display panel 100, the display panel 100 includes a plurality of pixels 101, and the pixel 101 includes a light-emitting element and a pixel circuit in any of the above embodiments. Therefore, the display panel 100 also has the beneficial effects of the pixel circuit in the above embodiments, and the similarities can be understood by referring to the above explanation of the pixel circuit, which will not be repeated below.

[0082] In one embodiment, Fig.12As shown, the present application also provides a display device 200, which includes the display panel 100 in the above embodiment. Therefore, the display device 200 also has the beneficial effects of the display panel 100 in the above embodiment, and the similarities can be understood by referring to the above explanation of the display panel 100, which will not be repeated below.

[0083] The display device 200 provided in the embodiment of the present application can be Fig.12 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of the present application do not specifically limit this.

[0084] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A pixel circuit, characterized in that: The pixel circuit comprises: Driver transistor; A threshold compensation module, wherein a first end of the threshold compensation module is connected to a first electrode of the driving transistor, a second end of the threshold compensation module is connected to a gate of the driving transistor, and a control end of the threshold compensation module is used to receive a first scanning signal; a first reset module, wherein a first end of the first reset module is connected to the gate of the driving transistor, a second end of the first reset module is used to receive a first reset signal, and a control end of the first reset module is used to receive a second scanning signal; A compensation module, wherein a first end of the compensation module is connected to a target node, and a second end of the compensation module is used to receive a target signal; wherein the target node includes at least one of an intermediate node of the threshold compensation module and an intermediate node of the first reset module, and the target signal includes a first target signal and a second target signal; The potential of the first target signal received by the second end of the compensation module in the blanking phase is higher than the potential of the second target signal received by the second end of the compensation module in the holding phase.

2. The pixel circuit according to claim 1, characterized in that: In the case where a voltage difference between the gate voltage of the driving transistor and the first reset signal is greater than a preset threshold, the target node includes an intermediate node of the threshold compensation module or an intermediate node of the first reset module.

3. The pixel circuit according to claim 1, characterized in that: The compensation module includes a first capacitor, a first end of the first capacitor is connected to a target node, and a second end of the first capacitor is used to receive a target signal; wherein the target node includes an intermediate node of the threshold compensation module or an intermediate node of the first reset module.

4. The pixel circuit according to claim 1, characterized in that: In a case where a voltage difference between a gate voltage of the driving transistor and the first reset signal is less than or equal to a preset threshold, the target node includes an intermediate node of the threshold compensation module and an intermediate node of the first reset module.

5. The pixel circuit according to claim 1, characterized in that: The compensation module includes a second capacitor and a third capacitor, and the target node includes an intermediate node of the threshold compensation module and an intermediate node of the first reset module; A first end of the second capacitor is connected to a middle node of the threshold compensation module, and a second end of the second capacitor is used to receive a target signal; A first end of the third capacitor is connected to the middle node of the first reset module, and a second end of the third capacitor is used to receive a target signal.

6. The pixel circuit according to claim 1, characterized in that: A potential difference between the potential of the first target signal and the potential of the second target signal is positively correlated with a display brightness value of the pixel circuit.

7. The pixel circuit according to claim 6, characterized in that: The potential of the first target signal is positively correlated with the display brightness value, and the potential of the second target signal is negatively correlated with the display brightness value.

8. The pixel circuit according to claim 6, characterized in that: When the display brightness value is less than a preset brightness threshold, the potential of the second target signal is negatively correlated with the display brightness value; When the display brightness value is greater than or equal to a preset brightness threshold, the potential of the second target signal remains unchanged.

9. The pixel circuit according to claim 6, characterized in that: When the display brightness value is greater than or equal to the preset brightness threshold, the rate of change of the potential of the first target signal is greater than the rate of change of the potential of the first target signal when the display brightness value is less than the preset brightness threshold.

10. The pixel circuit according to claim 1, characterized in that: The threshold compensation module comprises: a first threshold compensation transistor, wherein a first electrode of the first threshold compensation transistor is connected to a first electrode of the driving transistor, and a gate of the first threshold compensation transistor is used to receive a first scanning signal; a second threshold compensation transistor, wherein a first electrode of the second threshold compensation transistor is connected to a second electrode of the first threshold compensation transistor, a second electrode of the second threshold compensation transistor is connected to a gate of the driving transistor, and the gate of the second threshold compensation transistor is used to receive a first scanning signal; Wherein, the middle node of the threshold compensation module is the second electrode of the first threshold compensation transistor.

11. The pixel circuit according to claim 1, characterized in that: The first reset module includes: a first A reset transistor, wherein a first electrode of the first A reset transistor is connected to a gate of the driving transistor, and the gate of the first A reset transistor is used to receive a second scanning signal; a first B reset transistor, wherein a first electrode of the first B reset transistor is connected to a second electrode of the first A reset transistor, the second electrode of the first B reset transistor is used to receive a first reset signal, and a gate of the first B reset transistor is used to receive a second scanning signal; The middle node of the first reset module is the second electrode of the first A reset transistor.

12. The pixel circuit according to claim 1, characterized in that: The pixel circuit further comprises: A data writing module, wherein the first end of the data writing module is connected to the second electrode of the driving transistor, the second end of the data writing module is used to receive a data signal, and the control end of the data writing module is used to receive the first scanning signal; wherein, in the refresh phase, the target signal also includes the data signal.

13. The pixel circuit according to claim 12, characterized in that: The duration of the refresh phase is longer than the duration of the blanking phase, and the duration of the hold phase is longer than the duration of the refresh phase.

14. A display panel, characterized in that: The method comprises the pixel circuit as claimed in any one of claims 1 to 13.

15. A method for driving a pixel circuit, characterized in that: Applicable to a pixel circuit as claimed in any one of claims 1 to 13; the method comprising: In the blanking phase, providing a first target signal to the second terminal of the compensation module; In the holding phase, providing a second target signal to the second end of the compensation module; The potential of the first target signal is higher than the potential of the second target signal.

Images