MEMS accelerometer with low parasitic capacitance and preparation method thereof

Abstract

The invention belongs to the technical field of inertial sensors, and particularly discloses an MEMS accelerometer with low parasitic capacitance and a preparation method. According to the invention, the hollow area is formed at the position directly facing the back of the pickup electrode, so that the directly facing area between the pickup electrode and the upper cover silicon substrate is reduced, and the parasitic capacitance is reduced. In addition, a grounding polar plate is arranged between the pickup electrodes, so that the relative movement between the excitation electrode and the silicon substrate of the upper cover plate is shielded, and the influence of stray capacitance between the excitation electrode and the silicon substrate is further reduced. The hollow area is formed on the back of the pickup electrode of the MEMS accelerometer through the thin film supporting structure in combination with plasma dry etching, and the preparation method is simple in process, suitable for various capacitive MEMS accelerometers or gravimeters and good in compatibility and practicability.

Description

Technical Field

[0001] The present application belongs to the technical field of inertial sensors, and more specifically, relates to a MEMS accelerometer with low parasitic capacitance and a preparation method thereof. Background Art

[0002] MEMS (Micro Electro-Mechanical System) capacitive accelerometers, especially high-precision accelerometers with ng and sub-ng resolution, usually adopt a silicon-glass bonding structure packaging form, with a glass substrate on the top cover and a silicon substrate on the spring oscillator. However, the glass substrate is incompatible with the CMOS (Complementary Metal Oxide Semiconductor) process used in integrated circuits (ICs), which limits the integration of MEMS accelerometers and IC readout circuits and hinders the miniaturization of devices. At the same time, the glass substrate increases the difficulty of wafer-level packaging, resulting in obstacles to mass production.

[0003] The all-silicon structure (both the upper cover and the spring oscillator are made of silicon) can effectively solve the above problems, but there is a serious parasitic capacitance problem, which can lead to problems such as reduced sensitivity and increased background noise. Summary of the invention

[0004] In view of the defects of the prior art, the purpose of the present application is to provide a MEMS accelerometer with low parasitic capacitance and a preparation method, aiming to solve the serious problem of parasitic capacitance of the existing MEMS accelerometer.

[0005] To achieve the above-mentioned object, in a first aspect, the present application provides a MEMS accelerometer with low parasitic capacitance, comprising a spring oscillator structure and an upper cover plate;

[0006] The upper cover plate includes, in sequence along the direction facing the spring oscillator structure: a silicon substrate, a metal film, an insulating support film and a plurality of pickup electrodes;

[0007] A hollow area is provided on the silicon substrate and the metal film, and the hollow area faces at least one pickup electrode.

[0008] Preferably, the width of the hollow area is greater than the width of the pickup electrode.

[0009] Preferably, the hollowed-out areas on the silicon substrate and the metal film are of equal or unequal widths.

[0010] Preferably, a grounding electrode is provided between adjacent pickup electrodes, and the interval between the grounding electrode and the pickup electrode is smaller than the width of the excitation electrode in the spring oscillator structure.

[0011] Preferably, the insulating support film is a multi-layer composite structure.

[0012] To achieve the above-mentioned object, in a second aspect, the present application provides a method for preparing a MEMS accelerometer with low parasitic capacitance as described in the first aspect, comprising:

[0013] S1. Prepare the upper cover plate and the spring oscillator structure respectively;

[0014] S2. Connect the spring oscillator structure to the upper cover plate through the anchoring area.

[0015] Preferably, the preparation of the upper cover plate is as follows:

[0016] (1) Using physical vapor deposition to deposit a metal film on a silicon substrate as a stop layer for deep silicon etching;

[0017] (2) depositing a multilayer film on the metal film obtained in step (1) by chemical vapor deposition as an insulating support film;

[0018] (3) using a lift-off process to simultaneously prepare a pickup electrode and a ground electrode on the insulating support film obtained in step (2), and achieving physical isolation through layout design;

[0019] (4) performing plasma dry etching on the back of the patterned silicon wafer obtained in step (3) to form a hollow area on the back of the pickup electrode;

[0020] (5) removing the photoresist used as a dry etching mask in step (4) and the metal film located in the hollow area obtained in step (1).

[0021] Preferably, step (3) comprises:

[0022] (3.1) coating the silicon substrate obtained in step (2) with photoresist by a photoresist coating process, and transferring the metal plate pattern to the silicon wafer by an exposure method;

[0023] (3.2) placing the exposed silicon wafer in a developer for development;

[0024] (3.3) Using physical vapor deposition to deposit a metal film on the wafer, the pickup electrode and the ground electrode are prepared at the same time, and physical isolation is achieved through layout design to realize different functions;

[0025] (3.4) The silicon wafer is immersed in an acetone solution for metal stripping, cleaned with isopropyl alcohol, ethanol and deionized water, and dried with nitrogen gas.

[0026] Preferably, step (4) comprises:

[0027] (4.1) coating the back of the silicon wafer obtained in step (3) with photoresist by a photoresist coating process, and transferring the pattern to be etched onto the silicon wafer by an exposure method;

[0028] (4.2) placing the exposed silicon wafer in a developer for development;

[0029] (4.3) Plasma dry etching is performed on the back of the wafer to form a hollow area on the back of the pickup electrode.

[0030] Preferably, the spring oscillator structure and the upper cover plate are bonded by gold-tin eutectic bonding, wafer direct bonding or anodic bonding.

[0031] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the prior art:

[0032] (1) The present application provides a MEMS accelerometer with low parasitic capacitance, which reduces the parasitic capacitance by forming a hollow area at the back of the pickup electrode to reduce the facing area between the pickup electrode and the upper silicon substrate. In addition, a grounding plate is provided between the pickup electrodes to shield the relative movement between the excitation electrode and the upper silicon substrate, further reducing the influence of the parasitic capacitance between the excitation electrode and the silicon substrate.

[0033] (2) The present application provides a method for preparing a MEMS accelerometer with low parasitic capacitance. Through a thin film support structure combined with plasma dry etching, a hollow area is formed on the back of the MEMS accelerometer pickup electrode. The preparation method is simple in process and is applicable to various capacitive MEMS accelerometers or gravimeters, and has good compatibility and practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the structure of a MEMS accelerometer with low parasitic capacitance provided in an embodiment of the present application.

[0035] Figure 2 It is a specific process flow chart of the upper cover plate provided in the embodiment of the present application.

[0036] Figure 3 It is a specific process flow chart of the spring oscillator structure provided in the embodiment of the present application.

[0037] Figure 4 It is a schematic diagram of the key dimensions of the upper cover plate provided in the embodiment of the present application.

[0038] Throughout the drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0039] 101-frame, 102-support beam, 103-movable mass block, 104-silicon oxide, 105-ground plane, 106-silicon oxide, excitation electrodes-107, 108, 109, 110, 201-anchoring area, 202-silicon substrate, 203-metal film, 204-support film, pickup electrodes-205, 206, 207-ground electrode, 208-hollow area. DETAILED DESCRIPTION

[0040] For ease of understanding, the English abbreviations and related technical terms involved in the embodiments of the present application are explained and described below.

[0041] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0042] like Figure 1 As shown, the present application provides a MEMS accelerometer with low parasitic capacitance, including: a spring oscillator structure and an upper cover plate.

[0043] The spring oscillator structure is integrally processed and includes a frame 101, a support beam 102, a movable mass block 103, silicon oxides 104 and 106, a ground plane 105, and excitation electrodes 107-110;

[0044] The movable mass block 103 is connected to the frame 101 through the support beam 102, and silicon oxide 104 is deposited on the movable mass block 103 to achieve electrical isolation between the ground plane 105 and the movable mass block 103. Silicon oxide 106 is deposited on the ground plane 105 to achieve electrical isolation between the excitation electrodes 107~110 and the ground plane 105, wherein the excitation electrodes 107 and 109 are connected to an external forward voltage, and the excitation electrodes 108 and 110 are connected to an external reverse voltage.

[0045] The support beam 102 includes but is not limited to a spring. The movable mass block 103 can move left and right, and the moving range is several tens of μm. In addition to silicon oxide, 104 and 106 can also be silicon nitride, and the materials of the two can be the same or different.

[0046] The upper cover plate includes: a silicon substrate 202 , a metal film 203 , a support film 204 , pickup electrodes 205 and 206 , a ground electrode 207 and a hollow region 208 .

[0047] The metal film 203 is located between the silicon substrate 202 and the supporting film 204 , the pickup electrodes 205 and 206 are located on the supporting film, the ground electrode 207 is located between the pickup electrodes 205 and 206 , and there is a hollow area 208 above the pickup electrodes 205 and 206 .

[0048] It should be noted that when the width of the hollow area is slightly larger than the width of the pickup electrode 205 , the integrated capacitance reduction effect is better, which generally refers to being larger by more than 10 microns.

[0049] It should be noted that the height of the hollow area is greater than 10 microns, and the greater the height, the better the integrated capacitance reduction effect.

[0050] The pickup electrode 205 is located between the excitation electrodes 107 and 108 to form a pair of differential capacitors, and the pickup electrode 206 is located between the excitation electrodes 109 and 110 to form another pair of differential capacitors. Figure 1 Only two pairs of differential capacitors are schematically drawn in the figure. In fact, the MEMS accelerometer contains 10 to 80 pairs of differential capacitors.

[0051] The spring oscillator structure is connected to the upper cover plate via the anchoring region 201 , and the connection methods include but are not limited to wafer direct bonding, anodic bonding and eutectic bonding.

[0052] In the sensing process of the all-silicon structure accelerometer, the voltage change generated by the pickup electrode can be described by the following equation:

[0053]

[0054] Among them, C x , C y represents the sensing capacitance between the excitation electrodes 107, 108 and the pickup electrode 205, C p3 represents the parasitic capacitance between the pickup electrode 205 and the upper cover silicon substrate 202, C p4 represents the parasitic capacitance between the upper cover silicon substrate 202 and the spring oscillator frame 101, C p5 , C p6 They represent the parasitic capacitance between the excitation electrodes 107, 108 and the upper cover silicon substrate 202, C p7 represents the parasitic capacitance between the pickup electrode 205 and the ground electrode 206 .

[0055] Parasitic capacitance C p3 , C p5 , C p6 The biggest influence on the sensing process is C p3 Depending on the facing area between the pickup electrode 205 and the upper cover silicon substrate 202, C p5 , C p6 Depending on the relative movement between the excitation electrodes 107, 108 and the upper cover silicon substrate 202 during the movement, C p5 ≠C p6 .

[0056] The upper cover plate forms a hollow area 208 on the back of the pickup electrode 205 to reduce the facing area between the pickup electrode and the upper cover silicon substrate 202 to reduce the parasitic capacitance. The grounding plate 207 shields the relative movement between the excitation electrodes 107, 108 and the upper cover silicon substrate 202 during the movement, so that C p5 =C p6 , thereby reducing parasitic capacitance.

[0057] like Figure 2 As shown, the specific process flow of the upper cover plate provided in this application is:

[0058] S1: depositing a metal film 203 on a silicon substrate by physical vapor deposition, the material of which is Ti and the thickness of which is 200 nm, as a stop layer for deep silicon etching;

[0059] S2: using a chemical vapor deposition method, depositing a silicon oxide / silicon nitride / silicon oxide three-layer film 204 with a thickness of 500nm / 500nm / 2500nm on the metal film obtained in S1 as a support structure for the pickup electrodes 205 and 206;

[0060] S3: Pickup electrodes 205, 206 and ground electrode 207 are simultaneously prepared on the insulating layer film obtained in S2 by using a lift-off process. The material is Cr / Au with a thickness of 40nm / 200nm. They are physically isolated through layout design to achieve different functions.

[0061] S4: performing plasma dry etching on the back of the patterned silicon wafer obtained in S3 to form a hollow region 208 on the back of the pickup electrode;

[0062] S5: removing the photoresist used as a dry etching mask in S4 and the metal film located in the hollow area obtained in S1.

[0063] Further, S1 specifically includes the following steps:

[0064] S101: The silicon substrate is organically cleaned with acetone, isopropanol, ethanol and deionized water in sequence, and dried with nitrogen gas to complete preliminary cleaning;

[0065] S102: further performing oxygen plasma cleaning on the silicon wafer after preliminary cleaning;

[0066] S103: depositing a metal Ti film with a thickness of 200 nm on the cleaned silicon substrate by physical vapor deposition.

[0067] The metal material can be selected from titanium, aluminum or chrome and other easily removable metals.

[0068] Further, S2 specifically includes the following steps: using a chemical vapor deposition method to deposit a three-layer film of silicon oxide / silicon nitride / silicon oxide on the metal film obtained in S1 as a support structure of the pickup electrode, with a thickness of 500nm / 500nm / 2500nm.

[0069] The support structure can be a single-layer film or a multi-layer film, including silicon oxide, silicon nitride or other films with support capabilities. Multi-layer films can achieve stress compensation to a certain extent and control the warping of silicon wafers, so they are more commonly used.

[0070] Further, S3 specifically includes the following steps:

[0071] S3.1: The silicon substrate obtained in S2 is coated with photoresist by using a photoresist coating process, and the metal plate pattern is transferred to the silicon wafer by using an exposure method;

[0072] S3.2: placing the exposed silicon wafer in a developer for development;

[0073] S3.3: Use physical vapor deposition to deposit Cr40nm / Au200nm thin film on the wafer, prepare the pickup electrode and ground electrode at the same time, and achieve physical isolation through layout design to realize different functions;

[0074] S3.4: Soak the silicon wafer in acetone solution for metal stripping, clean it with isopropyl alcohol, ethanol and deionized water, and blow dry it with nitrogen gas.

[0075] It should be pointed out here that the distance between the ground electrode and the pickup electrode needs to be smaller than the width of the excitation electrode to ensure that the ground electrode can shield the relative movement between the excitation electrode and the upper cover silicon substrate.

[0076] Further, S4 specifically includes the following steps:

[0077] S4.1: coating the back of the silicon wafer obtained in S3 with photoresist by using a photoresist coating process, and transferring the pattern to be etched onto the silicon wafer by using an exposure method;

[0078] S4.2: placing the exposed silicon wafer in a developer for development;

[0079] S4.3: Plasma dry etching is performed on the back of the wafer to form a hollow area on the back of the pickup electrode.

[0080] It should be pointed out here that the width of the hollowed-out area on the back of the pickup electrode should be greater than the width of the pickup electrode, thereby reducing the facing area between the pickup electrode and the upper silicon substrate, thereby achieving the purpose of reducing parasitic capacitance.

[0081] Further, S5 specifically includes the following steps:

[0082] S5.1: Clean the silicon wafer using oxygen plasma to remove the photoresist hardened by dry etching;

[0083] S5.2: Dissolve the photoresist using acetone solution, and then wash with isopropanol, ethanol and deionized water;

[0084] S5.3: Soak the silicon wafer in a metal etching solution to remove the metal in the hollowed-out area obtained in S1 after S4; wash it with deionized water and dry it with nitrogen.

[0085] like Figure 3 As shown, the specific process flow of the spring oscillator structure provided by the present application is as follows:

[0086] S6: using a lift-off process to prepare a ground plane 105 on a silicon substrate with a 300 nm oxide layer, the material of which is Ti / Au with a thickness of 40 nm / 200 nm;

[0087] S7: using a chemical vapor deposition method, depositing a silicon oxide film 106 with a thickness of 1700 nm on the ground plane prepared in S6, as an insulating layer between the excitation electrode and the ground plane;

[0088] S8: using a reactive ion etching method to open a deep silicon etching window on the silicon oxide film deposited in S7;

[0089] S9: using a lift-off process to prepare excitation electrodes 107-110 on the silicon wafer obtained in S8, the material of which is Ti / Au and the thickness is 40nm / 200nm;

[0090] S10: The silicon wafer obtained in S9 is subjected to plasma dry etching to obtain a spring oscillator structure.

[0091] The spring oscillator structure is connected to the upper cover plate through the anchoring area 201 by gold-tin eutectic bonding.

[0092] Example

[0093] like Figure 4 As shown, the dimensions of the key parts of the upper cover include: the thickness of the silicon wafer is 500 microns, the width of the hollow area is 80μm, the width of the pickup electrode is 60μm, the width of the grounding plate metal is 30μm, the thickness of the metal film is 20nm, and the thickness of the insulating support film is 3500nm, specifically a three-layer film of silicon oxide 500nm-silicon nitride 500nm-silicon oxide 2500nm.

[0094] In this embodiment, the thickness of the silicon wafer used in S6 is 500 μm, and during the gold-tin eutectic bonding, the bonding temperature is 300° C. and lasts for 5 minutes.

[0095] After the preparation is completed, the parasitic capacitance between the pickup electrode and the ground electrode is tested by an LCR meter. When the present application is not used, the parasitic capacitance is 924pF, and when the present application is used, the parasitic capacitance is 70pF, and the parasitic capacitance is reduced by 13.2 times.

[0096] The scale factor of the all-silicon accelerometer was tested. When the present application was not used, the scale factor of the accelerometer was 1407V / g. When the present application was used, the scale factor of the accelerometer was 9336V / g, which was increased by 6.63 times. Among them, the scale factor was 6300V / g when there was no ground electrode, and the use of the ground electrode increased the scale factor by 1.48 times.

[0097] It should be understood that expressions such as "including" and "may include" that may be used in the present application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In the present application, terms such as "including" and / or "having" may be interpreted as indicating specific characteristics, numbers, operations, constituent elements, components, or combinations thereof, but may not be interpreted as excluding the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0098] In addition, in the present application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0099] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. Among them, "fixed connection" means that the relative position relationship after connection remains unchanged. "Rotational connection" means that the two are connected to each other and can rotate relative to each other after connection. "Sliding connection" means that the two are connected to each other and can slide relative to each other after connection. The directional terms mentioned in the embodiments of the present application, such as "top", "bottom", "inside", "outside", "left", "right", etc., are only reference directions of the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0100] In addition, in the embodiments of the present application, the mathematical concepts mentioned are symmetry, equality, parallelism, verticality, etc. These limitations are all for the current state of the art, rather than being absolutely strict definitions in a mathematical sense, and allow a small amount of deviation, approximation to symmetry, approximation to equality, approximation to parallelism, approximation to verticality, etc. are all possible. For example, A and B are parallel, which means that A and B are parallel or approximately parallel, and the angle between A and B can be between 0 and 10 degrees. A and B are perpendicular, which means that A and B are perpendicular or approximately perpendicular, and the angle between A and B can be between 80 and 100 degrees.

[0101] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A MEMS accelerometer with low parasitic capacitance, characterized in that: It includes a spring vibrator structure and an upper cover plate; The upper cover plate includes, in sequence along the direction facing the spring oscillator structure: a silicon substrate, a metal film, an insulating support film and a plurality of pickup electrodes; A hollow area is provided on the silicon substrate and the metal film, and the hollow area faces at least one pickup electrode.

2. The MEMS accelerometer according to claim 1, wherein: The width of the hollow area is greater than the width of the pickup electrode.

3. The MEMS accelerometer according to claim 1, wherein: The hollowed-out areas on the silicon substrate and the metal film have equal or unequal widths.

4. The MEMS accelerometer according to any one of claims 1 to 3, characterized in that: A grounding electrode is provided between adjacent pickup electrodes, and the interval between the grounding electrode and the pickup electrode is smaller than the width of the excitation electrode in the spring oscillator structure.

5. The MEMS accelerometer according to any one of claims 1 to 3, characterized in that: The insulating support film is a multi-layer composite structure.

6. A method for preparing a MEMS accelerometer with low parasitic capacitance according to any one of claims 1 to 5, characterized in that: include: S1. Prepare the upper cover plate and the spring oscillator structure respectively; S2. Connect the spring oscillator structure to the upper cover plate through the anchoring area.

7. The preparation method according to claim 6, characterized in that: The preparation of the upper cover plate is specifically as follows: (1) Using physical vapor deposition to deposit a metal film on a silicon substrate as a stop layer for deep silicon etching; (2) depositing a multilayer film on the metal film obtained in step (1) by chemical vapor deposition as an insulating support film; (3) using a lift-off process to simultaneously prepare a pickup electrode and a ground electrode on the insulating support film obtained in step (2), and achieving physical isolation through layout design; (4) performing plasma dry etching on the back of the patterned silicon wafer obtained in step (3) to form a hollow area on the back of the pickup electrode; (5) removing the photoresist used as a dry etching mask in step (4) and the metal film located in the hollow area obtained in step (1).

8. The preparation method according to claim 7, characterized in that: Step (3) includes: (3.1) coating the silicon substrate obtained in step (2) with photoresist by a photoresist coating process, and transferring the metal plate pattern to the silicon wafer by an exposure method; (3.2) placing the exposed silicon wafer in a developer for development; (3.3) Using physical vapor deposition to deposit a metal film on the wafer, the pickup electrode and the ground electrode are prepared at the same time, and physical isolation is achieved through layout design to realize different functions; (3.4) The silicon wafer is immersed in an acetone solution for metal stripping, cleaned with isopropyl alcohol, ethanol and deionized water, and dried with nitrogen gas.

9. The preparation method according to claim 7, characterized in that: Step (4) comprises: (4.1) coating the back of the silicon wafer obtained in step (3) with photoresist by a photoresist coating process, and transferring the pattern to be etched onto the silicon wafer by an exposure method; (4.2) placing the exposed silicon wafer in a developer for development; (4.3) Plasma dry etching is performed on the back of the wafer to form a hollow area on the back of the pickup electrode.

10. The preparation method according to claim 6, characterized in that: The spring oscillator structure and the upper cover plate are bonded by gold-tin eutectic bonding, wafer direct bonding or anode bonding.

Images