Neural network training method suitable for memristor type brain-like chip hardware deployment

Abstract

The invention discloses a neural network training method suitable for memristor type brain-like chip hardware deployment. According to the method, a cross array equivalent circuit is extracted through a partial element equivalent circuit method in a training stage, and a time domain transient simulation solving process of the equivalent circuit of the cross array is integrated into gradient propagation, so that the network can learn and adapt to the output characteristics of the cross array in the training process; furthermore, an unstructured dynamic pruning method based on a weight threshold is introduced, the memristor proportion in a low resistance state is effectively reduced, sneaking paths in the cross array are inhibited, and meanwhile, the operation cost of the cross array is reduced. Compared with a traditional training method, the method provided by the invention can significantly enhance the stability and precision of the neural network during hardware deployment, has wide applicability, and can be used for neural network training and deployment optimization of various advanced memory devices.

Description

Technical Field

[0001] The present invention relates to an offline training method in the field of brain-like chips, and specifically to a neural network training method suitable for hardware deployment of memristive brain-like chips. Background Art

[0002] The proposal of brain-like chips aims to overcome the "memory wall" bottleneck of the traditional von Neumann circuit architecture and solve the problem that traditional chips cannot meet the chip performance and computing power requirements of the artificial intelligence industry. Memristor-type brain-like chips are a major circuit architecture of brain-like chips. They use emerging electronic devices, memristors, to simulate artificial neural synapses and use cross-interconnect lines as signal transmission channels to achieve storage and computing simulation of the human brain.

[0003] Memristive brain-like chips have advantages such as simple structure, high device density, and low manufacturing cost, but their hardware implementation has signal integrity issues such as sneak paths, resistance voltage drops, and parasitic effects, which often lead to poor signal transmission quality. However, traditional neural network training methods ignore the non-ideal characteristics of such hardware implementations. When traditional training methods are deployed on actual memristive brain-like chips, model performance is often greatly reduced due to ignoring these non-ideal factors.

[0004] At present, researchers have tried to reduce the impact of these circuit non-ideal characteristics on the performance of neural networks by adjusting the architecture of neural networks or optimizing algorithms, such as by increasing the redundancy of the network or using fault-tolerant training algorithms. However, such methods usually lead to increased computational complexity and computing resources, and often require a compromise between the accuracy and efficiency of the model.

[0005] Therefore, it is necessary to develop a neural network training method that is more suitable for the hardware deployment of memristive brain-like chips. Summary of the invention

[0006] In view of the shortcomings of existing brain-like chip training methods, the present invention provides a neural network training method suitable for the hardware deployment of memristive brain-like chips. The present invention takes into account the non-ideal circuit factors in the memristor cross array during the training stage, and reduces the performance loss during the deployment process by combining the non-ideal characteristics of the hardware circuit and the dynamic pruning strategy. Compared with the traditional method, the method proposed by the present invention can significantly improve the performance of the neural network when the memristive brain-like chip hardware is deployed.

[0007] The technical method of the present invention is as follows:

[0008] 1. A neural network training method suitable for hardware deployment of memristive brain-like chips

[0009] Step 1: Construct the equivalent circuit of the neuromorphic memristor crossbar array;

[0010] Step 2: Encode each sample in the training set into a voltage vector and send it to the equivalent circuit of the neuromorphic memristor cross array, and then obtain the voltage and current signals output by the neuromorphic memristor cross array through circuit simulation; calculate the loss function based on the voltage and current signals output by the neuromorphic memristor cross array and complete the back propagation of the gradient;

[0011] Step 3: After the back propagation of the gradient is completed, the dynamic pruning method is used to increase the sparsity of the network weights in the neuromorphic memristor crossbar array, thereby updating the network weights;

[0012] Step 4: Based on the updated network weights, repeat steps 2 and 3, and use the remaining samples in the training set to continuously train the neuromorphic memristor cross array until the loss function converges, completing the training of the neural network.

[0013] In the step 1, the equivalent circuit of the neuromorphic memristor crossbar array is constructed using a partial element equivalent circuit method, which specifically includes the following steps:

[0014] First, the neuromorphic memristor crossbar array is divided into multiple basic units. Then, the equivalent resistance of each basic unit is calculated. Then, an equivalent inductance model is constructed. Finally, the equivalent capacitance of each basic unit is extracted to obtain the equivalent circuit of the neuromorphic memristor crossbar array.

[0015] The method of obtaining the voltage and current signals output by the neuromorphic memristor crossbar array by means of circuit simulation includes:

[0016] First, the steady-state value output of the neuromorphic memristor cross array is calculated, and then the steady-state value output and the dynamic time domain simulation of the cross array are combined to determine the steady-state moment of the network output; then the steady-state output values ​​corresponding to the voltage and current of the neuromorphic memristor cross array are calculated by the circuit equation of the connection matrix A and the resistance matrix R of the equivalent circuit. The calculation formula is as follows:

[0017]

[0018] Among them, V s and I s are the steady-state node voltage and branch current to be solved, V r represents the read voltage applied in the neuromorphic memristor crossbar array, X i represents the input voltage vector, ⊙ represents the Hadamard product, and T represents the transpose;

[0019] Finally, the transient output values ​​of the voltage and current of the neuromorphic memristor cross array are obtained by simulating the time domain waveform of the circuit through the partial element equivalent circuit method. The formula is as follows:

[0020]

[0021] Among them, V n represents the node voltage at the nth moment, I n represents the branch current at the nth moment, M U , M L and M P They respectively represent the upper triangular matrix, lower triangular matrix and permutation matrix obtained after the circuit structure matrix is ​​decomposed by LU.

[0022] The method of calculating the loss function based on the voltage and current signals output by the neuromorphic memristor crossbar array and completing the back propagation of the gradient includes:

[0023] Based on the voltage and current signals output by the neuromorphic memristor crossbar array, the real response S of the neuromorphic memristor crossbar array is obtained. xbar and the ideal response S ideal ; Then use the following formula to calculate the modified network response S:

[0024] S=S ideal +(S xbar -S ideal )·(1-β epoch )

[0025] Among them, β is the adjustment factor and epoch is the round of training.

[0026] The method of increasing the sparsity of network weights in a neuromorphic memristor crossbar array by using a dynamic pruning method includes:

[0027] By adjusting the pruning ratio, the proportion of high-resistance states of memristors in the neuromorphic memristor cross array is controlled, so that the sparsity of network weights is increased. The formula is as follows:

[0028]

[0029] Among them, W(i,j) and Wpruned(i,j) represent the weight value at position (i,j) in the weight matrix before pruning and the weight matrix after pruning, respectively. r represents the pruning threshold, and || represents the absolute value.

[0030] 2. A neural network training device suitable for hardware deployment of memristive brain-like chips

[0031] An equivalent circuit generation unit for constructing an equivalent circuit of a neuromorphic memristor crossbar array;

[0032] A circuit simulation unit, used to encode each sample in the training set into a voltage vector and send it into the equivalent circuit of the neuromorphic memristor crossbar array, and obtain the voltage and current signals output by the neuromorphic memristor crossbar array by means of circuit simulation;

[0033] A first training unit, for calculating a loss function and back-propagating a gradient according to voltage and current signals output by the neuromorphic memristor crossbar array;

[0034] The second training unit is used to increase the sparsity of network weights in the neuromorphic memristor crossbar array and update the network weights by using a dynamic pruning method.

[0035] 3. A computer device

[0036] The device includes a memory and a processor, the memory stores a computer program, and the processor implements the steps of a neural network training method suitable for hardware deployment of a memristive brain-like chip when executing the computer program.

[0037] 4. A computer-readable storage medium

[0038] The medium stores a computer program, which, when executed by a processor, implements the steps of a neural network training method suitable for hardware deployment of a memristive brain-like chip.

[0039] 5. A computer program product

[0040] The product includes a computer program / instruction, which, when executed by a processor, implements the steps of a neural network training method suitable for hardware deployment of a memristive brain-like chip.

[0041] The present invention models the cross array through the partial element equivalent circuit method, trains the network in combination with the ideal response and actual response of the circuit, and uses the unstructured dynamic pruning method to suppress sneak paths in the cross array. The training results can be imported into the memristive brain-like chip for implementation and verification.

[0042] Compared with the traditional brain-like chip training method, the method proposed in the present invention has the following beneficial effects:

[0043] 1. The dynamic pruning method of the present invention optimizes the structure of the neural network by adaptively adjusting the weight connections of the memristor network, reduces the proportion of low-resistance memristors in the reasoning process, and thus reduces the network operation cost.

[0044] 2. The present invention integrates the non-ideal circuit factors of memristive brain-like chips in the neural network training process to optimize training, which can significantly improve the stability and accuracy of the network during actual hardware deployment. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Schematic diagram of a neural network structure based on sparse pruning in an embodiment of the present invention;

[0046] Figure 2 A schematic diagram of a memristive brain-like chip used in an embodiment of the present invention;

[0047] Figure 3 is a schematic diagram of a crossbar array circuit information embedding process in an embodiment of the present invention;

[0048] Figure 4 The ideal test flow and the test flow chart based on the actual memristor simulation;

[0049] Figure 5 A 3D schematic diagram of modeling a crossbar array equivalent circuit in the implementation of the present invention;

[0050] Figure 6 This is a comparison chart of the recognition accuracy of the present invention and the traditional training method when deployed in an actual cross array. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the method of the present invention and to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments.

[0052] According to the inventive content of the present invention, the complete implementation examples are as follows:

[0053] The task targeted by this example is handwritten digit recognition, and the dataset used is a large handwritten digit database (MNIST) collected and compiled by the National Institute of Standards and Technology of the United States. The dataset is preprocessed by a computer. The dataset contains 10,000 training set images, each of which consists of 28×28 binary pixels. This example implements the proposed neural network training method for memristive brain-like chips based on this dataset, and verifies the effectiveness of the present invention by comparing it with the traditional training method that does not consider the non-ideal characteristics of the circuit. The three-layer network used is as follows: Figure 1 As shown in Figure 1, it includes input layer, output layer and softmax classification layer. The corresponding memristor-type brain-like chip is shown in Figure 1. Figure 2 As shown, the realization Figure 1 The mapping from the input layer to the output layer in , which is the core reasoning part of the network.

[0054] The training method proposed in the present invention combines the unstructured dynamic pruning strategy and the non-ideal characteristics of the integrated hardware circuit. Figure 3As shown. During the network training process, the present invention dynamically adjusts the connection weights according to the importance and activity of each neuron, that is, based on the set pruning ratio, the smaller values ​​in the weight matrix are discarded, and unimportant connections are pruned, thereby improving the sparsity and operational efficiency of the network. Furthermore, during the training process, the present invention combines the non-ideal circuit factors of the memristive brain-like chip to modify the gradient descent and back propagation algorithms, so that the neural network can adapt to the circuit characteristics during the learning process, so as to adapt to and compensate for the non-ideal matrix multiplication characteristics of the memristive brain-like chip, and then the neural network improves the performance of being deployed in a cross array.

[0055] The specific process of the method proposed by the present invention is as follows:

[0056] Step 1: The neuromorphic memristor crossbar array is composed of multiple memristors arranged in rows and columns according to the neural network chip architecture. Construct the equivalent circuit of the neuromorphic memristor crossbar array;

[0057] The partial element equivalent circuit method is a numerical calculation technology of electromagnetic fields based on circuit theory. It simulates electromagnetic effects by discretizing the conductor into a series of discrete units and assigning circuit elements such as resistance, inductance and capacitance to these discrete units. The partial element equivalent circuit method does not require discretization of the spatial medium, so it can simplify the model and significantly reduce the calculation time. It is particularly suitable for analyzing large-scale circuit systems with complex structures.

[0058] The equivalent circuit of the neuromorphic memristor crossbar array is constructed using the partial element equivalent circuit method, which specifically includes the following steps:

[0059] First, the dense but periodic neuromorphic memristor crossbar array is divided into multiple basic units, such as Figure 5 As shown, this can significantly reduce the workload of extracting parasitic circuits;

[0060] Next, calculate the equivalent resistance of each basic unit using the following formula:

[0061]

[0062] in, R is the equivalent resistance value, ρ is the resistivity of the material, l is the conductor length, S is the cross-sectional area of ​​the conductor.

[0063] Then, an equivalent inductance model is constructed; specifically, the self-inductance of the word line and the bit line and the mutual inductance of the adjacent word line and bit line are extracted respectively through the inductance analytical calculation formula. These inductance values ​​reflect the induced voltage generated by the interaction of the magnetic field when the current flows.

[0064] Finally, the equivalent capacitance of each basic unit is extracted to obtain the equivalent circuit of the neuromorphic memristor cross array. The extraction process of the equivalent capacitance of each basic unit is as follows:

[0065] The self-capacitance of word lines and bit lines, the mutual capacitance between adjacent word lines and bit lines, and the capacitance between word lines and bit lines are extracted respectively. The short-circuit capacitance matrix is ​​quickly extracted by calculating the potential coefficient matrix, and then the capacitance value of each basic unit is obtained.

[0066] In the simulation, transient simulation can be performed by combining the modified node analysis method to verify the effectiveness of the proposed circuit model.

[0067] Step 2: Encode each sample in the training set into a voltage vector and send it to the equivalent circuit of the neuromorphic memristor cross array, and then perform time domain simulation and steady-state value simulation by circuit simulation to obtain the voltage and current signals output by the neuromorphic memristor cross array. The present invention integrates non-ideal factors in the memristor such as sneak path and resistance drop into the normal network training and reverse gradient propagation process in an active training mode by means of circuit simulation, allowing the network to adapt to and learn the output characteristics of the cross array during training; calculate the loss function and reversely propagate the gradient based on the voltage and current signals output by the neuromorphic memristor cross array, and the loss function adopts the cross entropy loss function;

[0068] Among them, the time domain simulation and steady-state value simulation are performed by circuit simulation to obtain the voltage and current signals output by the neuromorphic memristor cross array, including:

[0069] First, the steady-state value output of the neuromorphic memristor cross array is calculated, and then the steady-state value output and the dynamic time domain simulation of the cross array are combined to determine the steady-state moment of the network output in order to help the peripheral circuit read the moment n. The expression for determining the reading moment of the memristor cross array through dynamic time domain simulation and circuit steady-state value is:

[0070]

[0071] Among them, I n and I s They represent the transient current value and steady-state current value at the nth moment in the transient simulation of the crossbar array, ε represents the allowable error, and k is the number of sampling points required to determine convergence;

[0072] Then, the steady-state output values ​​corresponding to the voltage and current of the neuromorphic memristor crossbar array are calculated by the circuit equations of the connection matrix A and the resistance matrix R of the equivalent circuit. The calculation formula is as follows:

[0073]

[0074] Among them, V s and I s are the steady-state node voltage and branch current to be solved, V r represents the read voltage applied in the neuromorphic memristor crossbar array, X i represents the input voltage vector, ⊙ represents the Hadamard product, and T represents the transpose.

[0075] Finally, the transient output values ​​of the voltage and current of the neuromorphic memristor cross array are obtained by simulating the time domain waveform of the circuit through the partial element equivalent circuit method. The formula is as follows:

[0076]

[0077] Among them, V n represents the node voltage at the nth moment, I n represents the branch current at the nth moment, M U , M L and M P They represent the upper triangular matrix, lower triangular matrix and permutation matrix obtained after the circuit structure matrix is ​​decomposed by LU. The circuit structure matrix is ​​composed of the connection matrix A, resistance matrix R, inductance matrix L and capacitance matrix C corresponding to the equivalent circuit, which respectively store the connection relationship between each node in the circuit, the resistance value of each resistor element, the inductance value of each inductor element and the capacitance value of each capacitor element.

[0078] The loss function is calculated and the gradient is back-propagated based on the voltage and current signals output by the neuromorphic memristor crossbar array, including:

[0079] Based on the voltage and current signals output by the neuromorphic memristor crossbar array, the real response S of the neuromorphic memristor crossbar array is obtained. xbar (i.e., the actual crossbar array simulation result obtained through circuit simulation) and the ideal response S ideal (i.e., the ideal matrix multiplication result); and then use the following formula to calculate the modified network response S (i.e., the modified matrix multiplication result):

[0080] S=f(S ideal， S xbar )=S ideal +(S xbar -S ideal ), (1-β epoch )

[0081] Among them, β is the adjustment factor used to control the correction ratio; f(S ideal , S xbar ) is the correction function, and epoch is the round of training.

[0082] Among them, the real response S of the neuromorphic memristor crossbar array is xbar It is obtained by inversely mapping the value range of the matrix multiplication of the memristor so that it can be used in the correction of the ideal matrix multiplication. The formula is as follows:

[0083]

[0084] Among them, G on and G o f f are the conductance values ​​corresponding to the low resistance state and high resistance state of the memristor, V r Indicates the read voltage, I s is the steady-state current value.

[0085] Ideal response S ideal The calculation method is:

[0086] S ideal =W·X i

[0087] Among them, W is the weight of training in the current batch, X i represents the input voltage vector.

[0088] Step 3: After the back propagation of the gradient is completed, the dynamic pruning method is used to increase the sparsity of the network weights in the neuromorphic memristor crossbar array, thereby updating the network weights;

[0089] Among them, the dynamic pruning method is used to increase the sparsity of network weights in the neuromorphic memristor crossbar array, including:

[0090] The proportion of high-resistance states of memristors in the neuromorphic memristor crossbar array is controlled by adjusting the proportion of pruning, that is, adjusting the distribution of weights and limiting the weights to positive values, so that the sparsity of network weights increases. The formula is as follows:

[0091]

[0092] Among them, W(i,j) and Wpruned(i,j) represent the weight value at position (i,j) in the weight matrix before pruning and the weight matrix after pruning, respectively, and || means taking the absolute value.

[0093] The number of weights to be deleted is determined by setting a fixed pruning ratio P, and the pruning threshold T is adjusted dynamically. r , in order to adapt to the changes in weight distribution during training. For example, after each back propagation, all weight values ​​W will be updated and their distribution will change accordingly. Then find a threshold T according to the set pruning ratio P r , so that it is less than T rThe proportion of the number of weights in the total number of weights is equal to the specified P. Since the weight distribution changes with the training process, T r It also needs to be adjusted dynamically to ensure that the correct number of weights is always deleted.

[0094] Step 4: Based on the updated network weights, repeat steps 2 and 3, and use the remaining samples in the training set to continuously train the neuromorphic memristor cross array until the loss function converges, completing the training of the neural network.

[0095] Figure 4 The flowchart of the ideal performance test in the computer and the simulation test in the crossbar array is shown. The difference between the two test methods is that the ideal performance test in the computer performs matrix multiplication, while the performance test in the crossbar array requires first mapping the training weights to the memristor conductance range and then testing according to its circuit structure. According to the circuit architecture of the memristor brain-like chip, the present invention adopts Figure 5 The equivalent circuit model shown is tested. Figure 6 As shown, the recognition rates of the training method based on the present invention when the unit interconnection resistance is 0.1Ω, 0.5Ω, 0.7Ω and 1.0Ω are 97.1%, 97.3%, 96.6% and 95.0% respectively, which are improved by 4.5%, 26.3%, 32.5% and 38.5% respectively after being deployed in the memristor array compared with the traditional training method, which proves the effectiveness of the present invention.

[0096] The above embodiments are implementation modes of the present invention, but the implementation modes of the present invention are not limited by the embodiments. Any other changes, modifications, substitutions, combinations and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement modes and shall be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope defined by the claims.

Claims

1. A neural network training method suitable for hardware deployment of memristive brain-like chips, characterized in that: include: Step 1: Construct the equivalent circuit of the neuromorphic memristor crossbar array; Step 2: Encode each sample in the training set into a voltage vector and send it to the equivalent circuit of the neuromorphic memristor cross array, and then obtain the voltage and current signals output by the neuromorphic memristor cross array through circuit simulation; calculate the loss function based on the voltage and current signals output by the neuromorphic memristor cross array and complete the back propagation of the gradient; Step 3: After the back propagation of the gradient is completed, the dynamic pruning method is used to increase the sparsity of the network weights in the neuromorphic memristor crossbar array, thereby updating the network weights; Step 4: Based on the updated network weights, repeat steps 2 and 3, and use the remaining samples in the training set to continuously train the neuromorphic memristor cross array until the loss function converges, completing the training of the neural network.

2. A neural network training method suitable for hardware deployment of memristive brain-like chips according to claim 1, characterized in that: In the step 1, the equivalent circuit of the neuromorphic memristor crossbar array is constructed using a partial element equivalent circuit method, which specifically includes the following steps: First, the neuromorphic memristor crossbar array is divided into multiple basic units. Then, the equivalent resistance of each basic unit is calculated. Then, an equivalent inductance model is constructed. Finally, the equivalent capacitance of each basic unit is extracted to obtain the equivalent circuit of the neuromorphic memristor crossbar array.

3. A neural network training method suitable for hardware deployment of memristive brain-like chips according to claim 1, characterized in that: The method of obtaining the voltage and current signals output by the neuromorphic memristor crossbar array by means of circuit simulation includes: First, the steady-state value output of the neuromorphic memristor cross array is calculated, and then the steady-state value output and the dynamic time domain simulation of the cross array are combined to determine the steady-state moment of the network output; then the steady-state output values ​​corresponding to the voltage and current of the neuromorphic memristor cross array are calculated by the circuit equation of the connection matrix A and the resistance matrix R of the equivalent circuit. The calculation formula is as follows: Among them, V s and I s are the steady-state node voltage and branch current to be solved, V r represents the read voltage applied in the neuromorphic memristor crossbar array, X i represents the input voltage vector, ⊙ represents the Hadamard product, T represents the transpose; Finally, the transient output values ​​of the voltage and current of the neuromorphic memristor cross array are obtained by simulating the time domain waveform of the circuit through the partial element equivalent circuit method. The formula is as follows: Among them, V n represents the node voltage at the nth moment, I n represents the branch current at the nth moment, M U , M L and M P They respectively represent the upper triangular matrix, lower triangular matrix and permutation matrix obtained after the circuit structure matrix is ​​decomposed by LU.

4. A neural network training method suitable for hardware deployment of memristive brain-like chips according to claim 1, characterized in that: The method of calculating the loss function based on the voltage and current signals output by the neuromorphic memristor crossbar array and completing the back propagation of the gradient includes: Based on the voltage and current signals output by the neuromorphic memristor crossbar array, the real response S of the neuromorphic memristor crossbar array is obtained. xbar and the ideal response S ideal ; Then use the following formula to calculate the modified network response S: S=S ideal +(S xbar -S ideal )·(1-β epoch ) Among them, β is the adjustment factor and epoch is the round of training.

5. A neural network training method suitable for hardware deployment of memristive brain-like chips according to claim 1, characterized in that: The method of increasing the sparsity of network weights in a neuromorphic memristor crossbar array by using a dynamic pruning method includes: By adjusting the pruning ratio, the proportion of high-resistance states of memristors in the neuromorphic memristor cross array is controlled, so that the sparsity of network weights is increased. The formula is as follows: Among them, W(i, j) and W prumed (i, j) represents the weight value at position (i, j) in the weight matrix before pruning and the weight matrix after pruning, respectively. r represents the pruning threshold, and || represents the absolute value.

6. A neural network training device suitable for hardware deployment of memristive brain-like chips, characterized in that: include: An equivalent circuit generation unit for constructing an equivalent circuit of a neuromorphic memristor crossbar array; A circuit simulation unit, used to encode each sample in the training set into a voltage vector and send it into the equivalent circuit of the neuromorphic memristor crossbar array, and obtain the voltage and current signals output by the neuromorphic memristor crossbar array by means of circuit simulation; A first training unit, for calculating a loss function and back-propagating a gradient according to voltage and current signals output by the neuromorphic memristor crossbar array; The second training unit is used to increase the sparsity of network weights in the neuromorphic memristor crossbar array and update the network weights by using a dynamic pruning method.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, the steps of a neural network training method suitable for hardware deployment of a memristive brain-like chip as described in any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of a neural network training method suitable for hardware deployment of a memristive brain-like chip as described in any one of claims 1 to 5 are implemented.

9. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of a neural network training method suitable for hardware deployment of a memristive brain-like chip as described in any one of claims 1 to 5 are implemented.

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