Large-area perovskite / silicon-based laminated cell structure and preparation method thereof

Abstract

The invention relates to the technical field of solar cells, in particular to a large-area perovskite / silicon-based laminated cell structure and a preparation method thereof. The large-area perovskite / silicon-based laminated cell structure comprises: a silicon-based cell; the first transmission layer is positioned on one side of the silicon substrate battery; the perovskite layer is positioned on one side, far away from the silicon substrate battery, of the first transmission layer; the second transmission layer is positioned on one side, far away from the silicon substrate battery, of the perovskite layer; the buffer layer is located on one side, away from the silicon-based battery, of the second transmission layer; the transparent conducting layer is located on the side, away from the silicon substrate battery, of the buffer layer and comprises at least one first transparent conducting layer and at least one second transparent conducting layer, the first transparent conducting layer is located between the buffer layer and the second transparent conducting layer, and the density of the first transparent conducting layer is smaller than that of the second transparent conducting layer; and the electrode is formed on one side, far away from the silicon substrate battery, of the transparent conductive layer through silk-screen printing or ink-jet printing.

Description

Technical Field

[0001] The present disclosure relates to the technical field of solar cells, and in particular to a large-area perovskite / silicon-based stacked cell structure and a preparation method thereof. Background Art

[0002] The perovskite / silicon-based tandem cell structure is a device that directly converts solar energy into electrical energy. The perovskite / silicon-based tandem cell structure has broad application prospects in modern society due to its high photoelectric conversion efficiency, green environmental protection, and wide range of applications. Commonly used perovskite / silicon tandem cell process preparation routes: 1. Provide a silicon bottom cell, such as an N-type silicon bottom cell; 2. Prepare a composite layer or tunnel junction on the silicon bottom cell to connect the silicon bottom cell + perovskite top cell in series; 3. Prepare a hole transport layer, a perovskite light absorption layer, a passivation layer, an electron transport layer, a buffer layer, a transparent conductive layer, and a metal electrode on the composite layer from bottom to top. The commonly used method for preparing electrodes for perovskite / silicon tandem cells in the industry is basically achieved through evaporation, rather than screen printing used in traditional solar cells. For example, the mainstream solution for the preparation of laboratory electrodes for small-area perovskite / silicon tandem cells in the laboratory is to evaporate Ag to prepare the electrodes for the tandem cell, and there is no good way to achieve large areas (such as 166mm 2 *166mm 2 ). This is because when evaporating Ag, a mask is needed to prepare the gate line. At present, it is almost impossible to prepare a mask for the appropriate gate line. For example, if the gate line is too thin, it will block the hole, and if it sags, it will form a shadow, and if the gate line is too wide, it will block the light. These problems will affect the current collection of the stacked battery, and the evaporation equipment has extremely poor material utilization and a long equipment cycle time, which does not match the cost-first characteristic of the photovoltaic industry.

[0003] With the development of the industry, the size requirements for perovskite / silicon-based tandem cells are getting larger and larger. The mainstream method of preparing electrodes by evaporation is no longer suitable for industrialization. However, the conventional electrode preparation method for preparing large-area perovskite / silicon-based tandem cells is screen printing, which prepares Ag grid lines by printing Ag slurry and high-temperature sintering and curing. However, this faces new problems. Perovskite / silicon tandem cells are very sensitive to temperature. At high temperatures, perovskite materials are easily denatured and the battery fails. Therefore, perovskite / silicon heterojunction tandem cells cannot use room temperature screen printing to prepare electrodes. Ultra-low temperature metallization technology is required to prepare electrodes.

[0004] Therefore, improving the heat resistance of large-area perovskite / silicon tandem cells is crucial to the road to industrialization and is an issue that urgently needs to be addressed. Summary of the invention

[0005] Based on this, it is necessary to provide a large-area perovskite / silicon-based tandem battery structure and a preparation method thereof to address the problem of poor heat resistance of large-area perovskite / silicon-based tandem batteries in the prior art.

[0006] In order to achieve the above objectives, on the one hand, a large-area perovskite / silicon-based stacked cell structure is provided, comprising:

[0007] Silicon substrate cells;

[0008] A first transmission layer, located on one side of the silicon substrate cell;

[0009] A perovskite layer, located on a side of the first transmission layer away from the silicon substrate cell;

[0010] A second transmission layer is located on a side of the perovskite layer away from the silicon substrate cell;

[0011] A buffer layer, located on a side of the second transmission layer away from the silicon substrate cell;

[0012] A transparent conductive layer, located on a side of the buffer layer away from the silicon substrate cell, and the transparent conductive layer includes at least one first transparent conductive layer and at least one second transparent conductive layer, the first transparent conductive layer is located between the buffer layer and the second transparent conductive layer, and the density of the first transparent conductive layer is less than the density of the second transparent conductive layer;

[0013] The electrode is formed on the side of the transparent conductive layer away from the silicon substrate battery by screen printing or inkjet printing.

[0014] In one embodiment, the large-area perovskite / silicon-based tandem battery structure further includes:

[0015] The thickness of the first transparent conductive layer accounts for 5%-50% of the thickness of the entire transparent conductive layer.

[0016] In one embodiment, the large-area perovskite / silicon-based tandem battery structure further includes:

[0017] The buffer layer includes at least one first buffer layer and at least one second buffer layer, the first buffer layer is located between the second transmission layer and the second buffer layer, and the density of the first buffer layer is greater than the density of the second buffer layer.

[0018] In one of the embodiments, the thickness of the first buffer layer is greater than 50% of the thickness of the buffer layer.

[0019] In one embodiment, the materials of the first buffer layer and the second buffer layer include at least tin oxide, and the material of the supplementary buffer layer includes at least one of tin oxide, zinc oxide, tin oxide, chromium oxide, and titanium oxide.

[0020] In one embodiment, the first transport layer is an electron transport layer, and the second transport layer is a hole transport layer, or the first transport layer is a hole transport layer, and the second transport layer is an electron transport layer.

[0021] In one embodiment, at least one tunnel junction or composite layer is included between the first transport layer and the silicon substrate cell, and / or at least one passivation layer is included between the second transport layer and the perovskite layer.

[0022] On the one hand, a method for preparing a large-area perovskite / silicon-based stacked battery structure is provided, comprising the following steps:

[0023] Provide silicon substrate cells;

[0024] forming a first transmission layer on one side of the silicon substrate cell;

[0025] forming a perovskite layer on the first transport layer;

[0026] forming a second transport layer on the perovskite layer;

[0027] forming a buffer layer on the second transmission layer;

[0028] forming a transparent conductive layer on the buffer layer, wherein the transparent conductive layer includes at least one first transparent conductive layer and at least one second transparent conductive layer, the first transparent conductive layer is located between the buffer layer and the second transparent conductive layer, and the density of the first transparent conductive layer is less than the density of the second transparent conductive layer;

[0029] An electrode is formed on the transparent conductive layer, and a heat treatment process needs to be performed on the electrode after the electrode is formed.

[0030] In one embodiment, the thickness of the first transparent conductive layer accounts for 5%-50% of the thickness of the entire transparent conductive layer.

[0031] In one embodiment, the buffer layer includes at least one first buffer layer and at least one second buffer layer, the first buffer layer is located between the second transmission layer and the second buffer layer, and the density of the first buffer layer is greater than the density of the second buffer layer.

[0032] In one of the embodiments, the thickness of the first buffer layer is greater than 50% of the thickness of the buffer layer.

[0033] In one embodiment, forming an electrode on the transparent conductive layer includes:

[0034] The electrode is formed on the side of the transparent conductive layer away from the silicon substrate battery by screen printing or inkjet printing, and the heat treatment temperature is in the range of 80° C. to 150° C.

[0035] In one embodiment, the first transport layer is an electron transport layer, and the second transport layer is a hole transport layer, or the first transport layer is a hole transport layer, and the second transport layer is an electron transport layer.

[0036] In one embodiment, before forming the first transmission layer on one side of the silicon substrate cell, the method includes:

[0037] Forming at least one tunneling junction or composite layer on the silicon substrate cell;

[0038] and / or,

[0039] Before forming the second transmission layer on the perovskite layer, the method comprises:

[0040] At least one passivation layer is formed on the perovskite layer.

[0041] The large-area perovskite / silicon-based laminated cell structure and its preparation method of the present specification have the following beneficial effects:

[0042] In the process of preparing large-area perovskite / silicon-based stacking, electrodes are formed by screen printing or inkjet printing, and the transparent conductive layer located on the side of the buffer layer away from the silicon-based battery is set to at least a two-layer structure, and the first transparent conductive layer close to the silicon-based battery is set to a transparent conductive layer with a lower density, and the second transparent conductive layer away from the silicon-based battery is set to a transparent conductive layer with a higher density. The overall performance of the transparent conductive layer set in the stack needs to take into account both optical and electrical properties, and meet the characteristics of high mobility, high transmittance, and low resistance. During thermal annealing, in the process of stress release of the transparent conductive layer, the first transparent conductive layer can relieve the stress and reduce the effect of stress on the compression of the buffer layer / second transmission layer, thereby reducing the risk of interface peeling between the buffer layer and the second transmission layer, and improving the heat resistance of large-area perovskite / silicon-based stacking.

[0043] Furthermore, the large-area perovskite / silicon-based stacked battery structure of the present specification has further improved the buffer layer, by setting the buffer layer located on the side of the transmission layer away from the silicon-based battery to at least a two-layer structure, setting the first buffer layer close to the silicon-based battery side to a buffer layer with a higher density, and setting the second buffer layer away from the silicon-based battery side to a buffer layer with a lower density. During thermal annealing, in the process of stress release of the buffer layer, the second buffer layer can relieve the stress released from the top transparent conductive layer, reduce the compression of the second transmission layer, thereby reducing the risk of interface peeling between the buffer layer and the second transmission layer, and further improving the heat resistance of the large-area perovskite / silicon-based stacked battery structure; at the same time, since the first buffer layer is in contact with the second transmission layer, the first buffer layer needs to be prepared into a film layer with a higher density, which combines with the second transmission layer to play a better interface conduction and carrier transport role. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 A flow chart of a method for preparing a large-area perovskite / silicon-based tandem battery structure provided in one embodiment;

[0046] Figure 2 A schematic diagram of a large-area perovskite / silicon-based tandem battery structure provided in one embodiment;

[0047] Figure 3 A schematic diagram of a large-area perovskite / silicon-based tandem battery structure provided in another embodiment.

[0048] Explanation of the reference numerals: large-area perovskite / silicon-based stacked cell structure-100; silicon-based cell-101; composite layer / tunnel junction-102; first transmission layer-103; perovskite layer-104; passivation layer-105; second transmission layer-106; buffer layer-107; first buffer layer-1071; second buffer layer-1072; transparent conductive layer-108; first transparent conductive layer-1081; second transparent conductive layer-1082; top electrode-110; bottom electrode-111.

[0049] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood. DETAILED DESCRIPTION

[0050] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0052] In each embodiment, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in each embodiment can be understood according to the specific situation.

[0053] It should be understood that when an element or layer is referred to as being "on, adjacent to, or connected to other elements or layers, it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, or directly connected to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present embodiment, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0054] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0055] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] Embodiments of the embodiments are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present specification, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, the embodiments of the present specification should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present embodiments.

[0057] See also Figure 1 In one embodiment, a method for preparing a large-area perovskite / silicon-based laminated battery structure 100 is provided. The size of the large-area perovskite / silicon-based laminated battery structure 100 provided in this application can be no less than 166 cm 2 *166cm 2 The cross-sectional schematic diagram of the large-area perovskite / silicon-based stacked cell structure 100 is shown in FIG. Figure 2 and Figure 3 The method for preparing the large-area perovskite / silicon-based stacked battery structure 100 may include the following steps:

[0058] Step S100: providing a silicon substrate cell 101 .

[0059] Step S200 : forming a first transmission layer 103 on one side of the silicon substrate cell 101 .

[0060] Step S300 : forming a perovskite layer 104 on the first transmission layer 103 .

[0061] Step S400 : forming a second transmission layer 106 on the perovskite layer 104 .

[0062] Step S500 : forming a buffer layer 107 on the second transmission layer 106 .

[0063] Step S600: forming a transparent conductive layer 108 on the buffer layer 107, wherein the transparent conductive layer 108 includes at least one first transparent conductive layer 1081 and at least one second transparent conductive layer 1082, the first transparent conductive layer 1081 is located between the buffer layer 107 and the second transparent conductive layer 1082, and the density of the first transparent conductive layer 1081 is less than the density of the second transparent conductive layer 1082.

[0064] Step S700 : forming electrodes on the transparent conductive layer 108 , and performing a heat treatment process on the electrodes after the electrodes are formed.

[0065] In step S100, the silicon substrate cell 101 may include a silicon bottom cell, and the silicon bottom cell may include a tunnel oxide passivating contact (Tunnel Oxide Passivating Contact, TOPCon) cell, a heterojunction (Heterojunction Technology, HJT) cell, an interdigitated back contact (Interdigitated Back Contact, IBC) cell, and a heterojunction back contact (Heterojunction Back Contact, HBC) cell, etc.

[0066] In step S200, a first transport layer 103 may be formed on one side of the silicon substrate cell 101. The material of the first transport layer 103 may include carbon 60, etc. The first transport layer 103 may include a hole transport layer or an electron transport layer.

[0067] Of course, before forming the first transmission layer 103, at least one composite layer / tunnel junction 102 may be formed on the silicon substrate battery 101. The tunnel junction is conducive to the tunneling movement of carriers, thereby improving the overall effect of the large-area perovskite / silicon-based stacked battery structure 100.

[0068] In step S300, a perovskite layer 104 may be formed on the first transmission layer 103. The perovskite layer 104 may be used to absorb sunlight and generate carriers to achieve photoelectric conversion.

[0069] In step S400, a second transport layer 106 may be formed on the perovskite layer 104. Specifically, when the first transport layer 103 is an electron transport layer, the second transport layer 106 is a hole transport layer. Alternatively, when the first transport layer 103 is a hole transport layer, the second transport layer 106 is an electron transport layer. As an example, in the case where a hole transport layer is first formed on one side of the silicon-based battery 101, this step may form an electron transport layer, and in the case where an electron transport layer is first formed on one side of the silicon-based battery 101, this step may form a hole transport layer. That is, the large-area perovskite / silicon-based stacked battery structure 100 provided in the present application may be a nip structure or a pin structure.

[0070] In step S500, a buffer layer 107 may be formed on a side of the second transmission layer 106 away from the silicon substrate cell 101. As an example, the material of the buffer layer 107 may include Atomic Layer Deposition SnO x , Ald-SnO x )wait.

[0071] As an example, the material of the buffer layer 107 may include SnO2, and its thickness is between 5nm and 30nm. In one possible example, a layer of SnO2 prepared by atomic layer deposition (ALD) may be used as the buffer layer 107. The refractive index of the buffer layer 107 may be between 1.5 and 2.0.

[0072] Of course, before forming the buffer layer 107 on the second transmission layer, at least one passivation layer 105 may be formed on the perovskite layer 104. The passivation layer 105 can improve the conversion efficiency of the battery, and can also protect the large-area perovskite / silicon-based stacked battery structure 100 and extend the service life of the large-area perovskite / silicon-based stacked battery structure 100.

[0073] In step S600, a transparent conductive layer 108 may be formed on a side of the buffer layer 107 away from the silicon substrate battery 101. The transparent conductive layer 108 may include at least one first transparent conductive layer 1081 and at least one second transparent conductive layer 1082, wherein the first transparent conductive layer 1081 is located between the buffer layer 107 and the second transparent conductive layer 1082, and the density of the first transparent conductive layer 108 is less than that of the second transparent conductive layer 1082. It can be understood that the density of the film layer can be used to indicate the number of pores and defects in the film layer. In this embodiment, the first transparent conductive layer 1081 has a smaller density, which indicates that the first transparent conductive layer 1081 has more pores, and the second transparent conductive layer 1082 has a larger density, which indicates that the second transparent conductive layer 1082 has a more compact structure and fewer pores and defects.

[0074] Specifically, the texture of the first transparent conductive layer 1081 may be relatively loose, or the first transparent conductive layer 1081 may have a relatively low refractive index. This embodiment does not specifically limit the density or refractive index of the first transparent conductive layer 1081. The material of the first transparent conductive layer 1081 may include, but is not limited to, indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), aluminum-doped zinc oxide (Aluminum-doped Zinc Oxide, AZO), indium tungsten oxide (Indium Tungsten Oxide, IWO), molybdenum-doped indium oxide (Molybdenum-doped Indium Oxide, IMO), etc. The thickness of the first transparent conductive layer 1081 may be in the range of 1nm-50nm.

[0075] This embodiment does not limit the preparation method of the first transparent conductive layer 1081. In the first example, the first transparent conductive layer 1081 can be formed on the side of the buffer layer away from the silicon substrate battery 101 by thermal evaporation, with an evaporation rate in the range of 0.1A / s-10A / s and a vacuum pressure of 1*10e -6 Pa-1*10e -2 In the second example, the first transparent conductive layer 1081 can be formed on the side of the buffer layer away from the silicon substrate battery 101 by physical vapor deposition, and the vacuum pressure is 1Pa~1*10e 3 In the third example, the first transparent conductive layer 1081 can be formed on the side of the buffer layer away from the silicon substrate battery 101 by reactive plasma deposition, and the vacuum pressure is between 1Pa and 1*10e 3 In the fourth example, the first transparent conductive layer 1081 can be formed on the side of the buffer layer away from the silicon substrate cell 101 by spin coating, and the annealing temperature is in the range of 80°C-120°C.

[0076] Accordingly, the texture of the second transparent conductive layer 1082 can be relatively dense. Further, the density of the first transparent conductive layer 1081 is less than that of the second transparent conductive layer 1082, or the refractive index of the first transparent conductive layer 1081 is less than that of the second transparent conductive layer 1082. This embodiment does not specifically limit the density or refractive index of the second transparent conductive layer 1082.

[0077] The material of the second transparent conductive layer 1082 may include ITO, IZO, AZO, IWO, IMO, etc. The thickness of the second transparent conductive layer 1082 may be in the range of 1nm-50nm. As an example, the material of the second transparent conductive layer 1082 may be consistent with the material of the first transparent conductive layer 1081, and the thickness of the second transparent conductive layer 1082 is consistent with the thickness of the first transparent conductive layer 1081. Further, the thickness of the first transparent conductive layer 1081 accounts for 5%-50% of the thickness of the entire transparent conductive layer. While ensuring the conductive performance of the large-area perovskite / silicon-based stacked battery structure 100, the first transparent conductive layer 1081 can also relieve the stress of the film layers on both sides without affecting the overall electrical and optical properties of the transparent conductive layer.

[0078] This embodiment does not limit the preparation method of the second transparent conductive layer 1082. In one example, the second transparent conductive layer 1082 can be formed on the side of the first transparent conductive layer 1081 away from the silicon substrate battery 101 by physical vapor deposition, and the vacuum pressure is 1Pa. -4 ~1*10e -1 Pa. Furthermore, both the first transparent conductive layer 1081 and the second transparent conductive layer 1082 can be formed by physical vapor deposition to simplify the process.

[0079] As an example, the common carrier mobility of the first transparent conductive layer 1081 and the second transparent conductive layer 1082 may be less than 30 cm 2 / Vs, the square resistance can be less than 200Ω / □, and the absolute transmittance in the visible light band can be less than 95%.

[0080] In step S700, an electrode may be formed on the transparent conductive layer (second transparent conductive layer 1082). Specifically, the electrode may be formed by screen printing or inkjet printing. In addition, a heat treatment process needs to be performed on the electrode after the electrode is formed. As an example, the heat treatment may include drying, curing, etc. The curing temperature is in the range of 80°C to 150°C.

[0081] As an example, electrodes can be prepared on the P-side and / or N-side of the large-area perovskite / silicon-based laminated battery structure 100. The electrodes may include a top electrode 110 and a bottom electrode 111. The materials of the electrodes include, but are not limited to, Ag, Cu, Au or other metal materials and mixtures. The electrode preparation methods include, but are not limited to, evaporation, screen printing, PVD, etc. Since the size of the laminated battery structure is large, preferably, screen printing or inkjet printing can be used to prepare the Ag electrode, the curing temperature is between 90°C and 150°C, and the curing time can be between 5min and 20min.

[0082] In the related art, the material of the second transport layer 106 (eg, electron transport layer) is often carbon 60, and the material of the buffer layer is often Ald-SnO x , the material of the transparent conductive layer is often IZO. At this time, when preparing the perovskite / silicon stacked battery, the thermal efficiency of the battery is seriously attenuated. The inventors found that this is because the interface tensile strength between the second transport layer and the buffer layer is very low (fracture energy is about 1.2 J / m 2 ), peeling is likely to occur between the two. Moreover, when preparing the transparent conductive layer on the side of the buffer layer away from the transport layer, physical vapor deposition (PVD) sputtering is often used. In this process, the bombardment of the buffer layer by PVD sputtering will affect the transport layer through the buffer layer, increasing the possibility of interface peeling between the second transport layer and the buffer layer. Furthermore, after annealing at a certain temperature, the stress inside the transparent conductive layer is released, and the squeezing of the second transport layer and the buffer layer will be more serious, thereby further worsening the interface delamination and peeling between the second transport layer and the buffer layer, and the carrier conduction effect through the interface becomes worse. Therefore, the efficiency of the perovskite / silicon-based stacked battery structure is seriously attenuated (for example, after heating, the fill factor (Fill Factor, FF) of the perovskite / silicon-based stacked battery structure will decrease significantly).

[0083] In this embodiment, during the preparation process of the large-area perovskite / silicon-based stacked battery structure 100, the electrodes are formed by screen printing or inkjet printing. By setting the transparent conductive layer 108 located on the side of the buffer layer 107 away from the silicon-based battery 101 to at least a two-layer structure, the first transparent conductive layer 1081 close to the silicon-based battery 101 is set as a transparent conductive layer with a lower density, and the second transparent conductive layer 1082 away from the silicon-based battery 101 is set as a transparent conductive layer with a higher density. The overall performance of the transparent conductive layer 108 with such a stacked configuration can take into account both optical and electrical properties, and meet the characteristics of high mobility, high transmittance, and low resistance. During thermal annealing, in the process of stress release of the transparent conductive layer 108, the first transparent conductive layer 1081 can relieve the stress and reduce the influence of the stress on the compression of the buffer layer 107 / the second transmission layer, thereby reducing the risk of interface peeling between the buffer layer 107 and / the second transmission layer, and improving the heat resistance of the large-area perovskite / silicon-based stacked battery structure 100.

[0084] Specifically, in this embodiment, the conductive performance of the large-area perovskite / silicon-based stacked battery structure 100 is ensured by the second transparent conductive layer 1082 with a higher density. However, the stress released by the second transparent conductive layer 1082 is relatively high, which has a greater squeezing effect on the lower film layer (buffer layer 107 / second transmission layer), so that the lower film layer is prone to peeling. Therefore, this embodiment also buffers the stress generated by the heat treatment process of the second transparent conductive layer 1082 through the first transparent conductive layer 1081 with a lower density, thereby reducing the squeezing effect of the lower film layer (buffer layer 107 / second transmission layer) and reducing the risk of peeling of the buffer layer 107 / second transmission layer.

[0085] In addition, as mentioned in the background technology, the common method for preparing electrodes of perovskite / silicon tandem cells in the industry is basically achieved by evaporation, rather than screen printing used in traditional solar cells. The inventors further found that at the curing temperature of ultra-low temperature metallization technology, low-temperature slurry cannot obtain a good curing effect, and cannot obtain a low contact density and line density, which limits the improvement of the efficiency of large-area perovskite / silicon-based tandem cell structures. Moreover, large-area perovskite / silicon-based tandem cell structures will also cause efficiency attenuation when heated (annealed) at a certain temperature, further limiting the preparation of large-area perovskite / silicon-based tandem cell structure components.

[0086] In this embodiment, by setting a first transparent conductive layer 1081 with a lower density, the stress generated by the heat treatment process of the second transparent conductive layer 1082 is buffered, the heat resistance of the large-area perovskite / silicon-based laminated battery structure 100 is improved, and it is more conducive to the use of silk screen printing to prepare electrodes. After many experiments, the inventor found that in the preparation method of the large-area perovskite / silicon-based laminated battery structure 100 provided in this embodiment, the silk screen curing temperature can be increased from 100°C to 130°C, and the efficiency FF gain of the large-area perovskite / silicon-based laminated battery structure 100 can also be obtained. Moreover, in the large-area perovskite / silicon-based laminated battery structure 100, the efficiency of the large-area perovskite / silicon-based laminated battery structure 100 after lamination can be improved from a decrease of 5%-6% to a decrease of 1%-2%.

[0087] In one embodiment, the buffer layer 107 includes at least one first buffer layer 1071 and at least one second buffer layer 1072 , the first buffer layer 1071 is located between the second transmission layer and the second buffer layer 1072 , and the density of the first buffer layer 1071 is greater than that of the second buffer layer 1072 .

[0088] The second buffer layer 1072 may be located between the first buffer layer 1071 and the transparent conductive layer 108. Moreover, the density of the second buffer layer 1072 is less than that of the first buffer layer 1071, or the refractive index of the second buffer layer 1072 is less than that of the first buffer layer 1071. This embodiment does not specifically limit the density or refractive index of the first buffer layer 1071 and the second buffer layer 1072.

[0089] As an example, the material of the second buffer layer 1072 may include at least one of tin oxide, zinc oxide, tin oxide, chromium oxide, and titanium oxide, or the material of the second buffer layer 1072 may include a mixture of the above metal oxides, etc. Of course, the material of the first buffer layer 1071 may be consistent with the material of the second buffer layer 1072, that is, the material of the first buffer layer 1071 may also include other metal oxides.

[0090] The thickness of the second buffer layer 1072 may be in the range of 5nm-30nm. As an example, the thickness of the second buffer layer 1072 may be consistent with the thickness of the first buffer layer 1071. The thickness of the second buffer layer 1072 may be between 1nm-30nm, and the refractive index may be between 1.8-2.4. As an example, the thickness of the first buffer layer 1071 may be greater than 50% of the thickness of the buffer layer 107, for example, the thickness of the first buffer layer 1071 is 50%, 60%, 70%, 80%, 90%, 100% of the thickness of the buffer layer 107, preferably, 50%-90%, thereby ensuring the transmission of electrical properties between the first buffer layer 1071 and the second transmission layer, thereby ensuring the performance of the large-area perovskite / silicon-based stacked battery structure 100.

[0091] In an actual embodiment, the first buffer layer 1071 and the second buffer layer 1072 can be prepared using the same process. In this case, the two can be fused into one layer to further block the influence of ion migration caused by crystallization after annealing of the transparent conductive layer. For example, the preparation method includes but is not limited to chemical vapor deposition (CVD), ALD, evaporation, PVD, RPD or water bath method. In addition, if the first buffer layer 1071 and the second buffer layer 1072 are prepared using different methods, the preparation method of the second buffer layer 1072 includes but is not limited to evaporation, ALD, PVD, RPD or solution method.

[0092] In this embodiment, the buffer layer 107 located on the side of the second transmission layer away from the silicon substrate battery 101 is set to at least a two-layer structure, the first buffer layer 1071 close to the side of the silicon substrate battery 101 is set to a buffer layer with a higher density, and the second buffer layer 1072 away from the side of the silicon substrate battery 101 is set to a buffer layer with a lower density. During thermal annealing, in the process of stress release of the buffer layer 107, the second buffer layer 1072 can relieve the stress released from the top transparent conductive layer 108, reduce the compression of the second transmission layer, thereby reducing the risk of interface peeling between the buffer layer 107 and the second transmission layer, and further improving the heat resistance of the large-area perovskite / silicon-based stacked battery structure 100. At the same time, since the first buffer layer 1071 is in contact with the second transmission layer, the first buffer layer 1071 needs to be prepared as a film layer with a higher density, which combines with the second transmission layer to play a better interface conduction and carrier transport role. Furthermore, the energy levels of the first buffer layer 1071 and the second buffer layer 1072 are close, which can further block the influence of ion migration caused by crystallization of the transparent conductive layer 108 after annealing, thereby preventing the efficiency of the large-area perovskite / silicon-based stacked battery structure 100 from decreasing.

[0093] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0094] Based on the same inventive concept, in one embodiment, a large-area perovskite / silicon-based stacked battery structure 100 is provided. The large-area perovskite / silicon-based stacked battery structure 100 may include a silicon substrate battery 101, a first transmission layer 103, a perovskite layer 104, a second transmission layer 106, a buffer layer 107, a transparent conductive layer 108, and an electrode 110.

[0095] The silicon base cell 101 may include a silicon base cell, and the silicon base cell may include a TOPCon cell, a HJT cell, an IBC cell, a HBC cell, and the like.

[0096] The material of the transport layer may include carbon 60, etc. The first transport layer 103 and the second transport layer 106 may include a hole transport layer and an electron transport layer, respectively. As an example, when the first transport layer 103 is a hole transport layer, the second transport layer 106 may be an electron transport layer, and when the first transport layer 103 is an electron transport layer, the second transport layer 106 may be a hole transport layer. That is, the large-area perovskite / silicon-based stacked battery structure 100 of the present application may be a nip structure or a pin structure.

[0097] The material of the buffer layer 107 may include Ald-SnO x As an example, the material of the buffer layer 107 may include SnO2, and its thickness may be between 5nm and 30nm. The refractive index of the buffer layer 107 may be between 1.5 and 2.0.

[0098] The transparent conductive layer 108 includes at least one first transparent conductive layer 1081 and at least one second transparent conductive layer 1082 . The first transparent conductive layer 1081 is located between the buffer layer 107 and the second transparent conductive layer 1082 . The density of the first transparent conductive layer 1081 is less than that of the second transparent conductive layer 1082 .

[0099] The texture of the first transparent conductive layer 1081 may be loose, and the texture of the second transparent conductive layer 1082 may be dense. Further, the density of the first transparent conductive layer 1081 is smaller than that of the second transparent conductive layer 1082, or the refractive index of the first transparent conductive layer 108 is smaller than that of the second transparent conductive layer 1082.

[0100] The material of the second transparent conductive layer 1082 may include ITO, IZO, AZO, IWO, IMO, etc. The thickness of the second transparent conductive layer 1082 may be in the range of 1nm-50nm. The material of the first transparent conductive layer 1081 may include, but is not limited to, ITO, IZO, AZO, IWO, IMO, etc. The thickness of the first transparent conductive layer 1081 may be in the range of 1nm-50nm. As an example, the thickness of the first transparent conductive layer 1081 accounts for 5%-50% of the thickness of the entire transparent conductive layer. While ensuring the conductive performance of the large-area perovskite / silicon-based stacked battery structure 100, the first transparent conductive layer 1081 can also relieve the stress of the film layers on both sides.

[0101] In this embodiment, by setting the transparent conductive layer 108 located on the side of the buffer layer 107 away from the silicon substrate battery 101 to at least a two-layer structure, the first transparent conductive layer 1081 close to the side of the silicon substrate battery 101 is set to a transparent conductive layer with a lower density, and the second transparent conductive layer 1082 away from the side of the silicon substrate battery 101 is set to a transparent conductive layer with a higher density. The overall performance of the transparent conductive layer of this stacked arrangement can take into account both optical and electrical properties and meet the characteristics of high mobility, high transmittance, and low resistance. During thermal annealing, in the process of stress release of the transparent conductive layer 108, the first transparent conductive layer 1081 can relieve the stress and reduce the influence of the stress on the compression of the buffer layer 107 / the second transmission layer, thereby reducing the risk of interface peeling between the buffer layer 107 / the second transmission layer, and improving the heat resistance of the large-area perovskite / silicon-based stacked battery structure 100.

[0102] In one embodiment, the buffer layer 107 includes at least one first buffer layer 1071 and at least one second buffer layer 1072 , the first buffer layer 1071 is located between the second transmission layer and the second buffer layer 1072 , and the density of the first buffer layer 1071 is greater than that of the second buffer layer 1072 .

[0103] The density of the second buffer layer 1072 is smaller than that of the first buffer layer 1071, or the refractive index of the second buffer layer 1072 is smaller than that of the first buffer layer 1071. The present embodiment does not impose any specific limitation on the density or refractive index of the second buffer layer 1072.

[0104] The material of the second buffer layer 1072 may include at least one of tin oxide, zinc oxide, tin oxide, chromium oxide, and titanium oxide, or a mixture of the above metal oxides. Of course, the material of the first buffer layer 1071 may be consistent with that of the second buffer layer 1072.

[0105] The thickness of the second buffer layer 1072 may be in the range of 5nm-30nm. As an example, the thickness of the second buffer layer 1072 may be consistent with the thickness of the first buffer layer 1071. The thickness of the second buffer layer 1072 may be between 1nm-30nm, and the refractive index may be between 1.8-2.4. As an example, the thickness of the first buffer layer 1071 is greater than 50% of the thickness of the buffer layer 107. Preferably, the thickness of the first buffer layer 1071 is 50%-90% of the thickness of the buffer layer 107, thereby ensuring the transmission of electrical properties between the first buffer layer 1071 and the second transmission layer, thereby ensuring the performance of the large-area perovskite / silicon-based stacked battery structure 100.

[0106] In this embodiment, the buffer layer 107 located on the side of the transmission layer away from the silicon substrate battery 101 is set to at least a two-layer structure, the first buffer layer 1071 close to the side of the silicon substrate battery 101 is set to a buffer layer with a higher density, and the second buffer layer 1072 away from the side of the silicon substrate battery 101 is set to a buffer layer with a lower density. During thermal annealing, in the process of stress release of the buffer layer 107, the second buffer layer 1072 can relieve the stress released from the top transparent conductive layer 108, reduce the compression of the second transmission layer, thereby reducing the risk of interface peeling between the buffer layer 107 and the second transmission layer, and further improving the heat resistance of the large-area perovskite / silicon-based stacked battery structure 100. At the same time, since the first buffer layer 1071 is in contact with the second transmission layer, the first buffer layer 1071 needs to be prepared into a film layer with a higher density, which combines with the second transmission layer to play a better interface conduction and carrier transport role. Furthermore, the energy levels of the first buffer layer 1071 and the second buffer layer 1072 are close, which can further block the influence of ion migration caused by crystallization of the transparent conductive layer 108 after annealing, thereby preventing the efficiency of the large-area perovskite / silicon-based stacked battery structure 100 from decreasing.

[0107] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that "this embodiment" or "one embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification may not necessarily refer to the same embodiment.

[0108] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The embodiments described above only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all fall within the scope of protection of the present application. Therefore, the scope of protection of the patent of the present application shall be subject to the attached claims. The above description is only a preferred implementation method of the present disclosure, and does not limit the scope of the patent of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure specification and drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the scope of protection of the patent of the present disclosure.

Claims

1. A large-area perovskite / silicon-based tandem battery structure, characterized in that: include: Silicon substrate cells; A first transmission layer, located on one side of the silicon substrate cell; A perovskite layer, located on a side of the first transmission layer away from the silicon substrate cell; A second transmission layer is located on a side of the perovskite layer away from the silicon substrate cell; A buffer layer, located on a side of the second transmission layer away from the silicon substrate cell; A transparent conductive layer, located on a side of the buffer layer away from the silicon substrate cell, and the transparent conductive layer includes at least one first transparent conductive layer and at least one second transparent conductive layer, the first transparent conductive layer is located between the buffer layer and the second transparent conductive layer, and the density of the first transparent conductive layer is less than the density of the second transparent conductive layer; The electrode is formed on the side of the transparent conductive layer away from the silicon substrate battery by screen printing or inkjet printing.

2. The large-area perovskite / silicon-based tandem battery structure according to claim 1, characterized in that: The thickness of the first transparent conductive layer accounts for 5%-50% of the thickness of the entire transparent conductive layer.

3. The large-area perovskite / silicon-based tandem battery structure according to claim 1, characterized in that: The large-area perovskite / silicon-based stacked cell structure further includes: The buffer layer includes at least one first buffer layer and at least one second buffer layer, the first buffer layer is located between the second transmission layer and the second buffer layer, and the density of the first buffer layer is greater than the density of the second buffer layer.

4. The large-area perovskite / silicon-based tandem battery structure according to claim 3, characterized in that: The thickness of the first buffer layer is greater than 50% of the thickness of the buffer layer.

5. The large-area perovskite / silicon-based tandem battery structure according to claim 3, characterized in that: The material of the first buffer layer and the second buffer layer includes at least one of tin oxide, zinc oxide, chromium oxide, and titanium oxide.

6. The large-area perovskite / silicon-based tandem battery structure according to claim 1, characterized in that: The first transport layer is an electron transport layer, and the second transport layer is a hole transport layer, or the first transport layer is a hole transport layer, and the second transport layer is an electron transport layer.

7. The large-area perovskite / silicon-based tandem battery structure according to claim 1, characterized in that: At least one tunnel junction or composite layer is further provided between the first transmission layer and the silicon substrate cell, and / or at least one passivation layer is further provided between the second transmission layer and the perovskite layer.

8. A method for preparing a large-area perovskite / silicon-based stacked battery structure, characterized in that: The steps include: Provide silicon substrate cells; forming a first transmission layer on one side of the silicon substrate cell; forming a perovskite layer on the first transport layer; forming a second transport layer on the perovskite layer; forming a buffer layer on the second transmission layer; forming a transparent conductive layer on the buffer layer, wherein the transparent conductive layer includes at least one first transparent conductive layer and at least one second transparent conductive layer, the first transparent conductive layer is located between the buffer layer and the second transparent conductive layer, and the density of the first transparent conductive layer is less than the density of the second transparent conductive layer; An electrode is formed on the transparent conductive layer, and a heat treatment process needs to be performed on the electrode after the electrode is formed.

9. The method for preparing a large-area perovskite / silicon-based laminated battery structure according to claim 8, characterized in that: The thickness of the first transparent conductive layer accounts for 5%-50% of the thickness of the entire transparent conductive layer.

10. The method for preparing a large-area perovskite / silicon-based laminated battery structure according to claim 8, characterized in that: The buffer layer includes at least one first buffer layer and at least one second buffer layer, the first buffer layer is located between the second transmission layer and the second buffer layer, and the density of the first buffer layer is greater than the density of the second buffer layer.

11. The method for preparing a large-area perovskite / silicon-based tandem battery structure according to claim 10, characterized in that: The thickness of the first buffer layer is greater than 50% of the thickness of the buffer layer.

12. The method for preparing a large-area perovskite / silicon-based tandem battery structure according to claim 8, characterized in that: The step of forming an electrode on the transparent conductive layer comprises: The electrode is formed on the side of the transparent conductive layer away from the silicon substrate battery by screen printing or inkjet printing, and the heat treatment temperature is in the range of 80° C. to 150° C.

13. The method for preparing a large-area perovskite / silicon-based laminated battery structure according to claim 8, characterized in that: The first transport layer is an electron transport layer, and the second transport layer is a hole transport layer, or the first transport layer is a hole transport layer, and the second transport layer is an electron transport layer.

14. The method for preparing a large-area perovskite / silicon-based tandem battery structure according to claim 8, characterized in that: Before forming the first transmission layer on one side of the silicon substrate cell, the method includes: Forming at least one tunneling junction or composite layer on the silicon substrate cell; and / or, Before forming the second transmission layer on the perovskite layer, the method comprises: At least one passivation layer is formed on the perovskite layer.

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