Preparation method of high-density three-dimensional programmable memory

Abstract

The invention discloses a preparation method of a high-density three-dimensional programmable memory, and relates to a preparation technology of memorizers, and the method comprises the steps: forming a basic structure body; grooving the basic structure body; arranging each storage medium layer required by a preset storage structure on the inner wall of the segmentation groove layer by layer; filling a core medium in the segmentation groove to form a core medium layer; etching a deep hole along the segmentation groove filled with the core medium by adopting an under-mask etching process, and cutting off the core medium in the segmentation groove by the deep hole; and filling an insulating medium in the deep hole. The method is low in cost, and the highest storage density can be obtained.

Description

[0001] The present invention is a divisional application of the invention named “Method for preparing high-density three-dimensional programmable memory”, in which the application number of the parent case is 202110233574.3 and the application date is 2021.06.25. Technical Field

[0002] The present application relates to the field of memory preparation, and in particular to a method for preparing a high-density three-dimensional programmable memory. Background Art

[0003] Existing technologies include various digital storage technologies such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, NAND-flash memory, hard disk, compact disk (CD), digital versatile disk (DVD), Blu-ray disc registered by the Blu-ray Disc Association, etc., which have been widely used for data storage for more than 50 years. However, the life of the storage medium is usually less than 5 to 10 years. The anti-fuse storage technology developed for big data storage cannot meet the needs of massive data storage because it is very expensive and has low storage density.

[0004] Chinese patent application 201811117240.4 discloses a method for preparing a three-dimensional programmable memory, in which a number of independent strip grooves are first opened in step 2), and after the storage medium is deposited on the inner wall of the groove and filled with the core medium, the independent strip grooves are connected into a curve by isolation grooves. This method has shortcomings: the basic structure is composed of alternating overlapping conductive dielectric layers and insulating dielectric layers. Under certain process conditions, the material used to etch the conductive dielectric layer and the material used to etch the insulating dielectric layer may be different, and different etching materials need to be repeatedly replaced, that is, the cost of etching the stacked structure is relatively high. This technology realizes the etching of the stacked structure in step 2), and etches the stacked structure again in step 5), which is not cost-effective. An overly cumbersome process not only reduces production efficiency, but may also lead to a reduction in yield.

[0005] Similarly, Chinese patent application 201910136928.1 discloses a non-volatile storage device and a method for manufacturing the same, which also suffers from the problems of complicated process and insufficient yield. Summary of the invention

[0006] The purpose of the present application is to provide a method for preparing a high-density three-dimensional programmable memory, which has the characteristics of low cost and high yield.

[0007] To achieve the above objectives, this application provides the following solutions:

[0008] The present application provides a method for preparing a high-density high-density three-dimensional programmable memory, comprising:

[0009] Arranging a predetermined number of conductive medium layers and insulating medium layers in a staggered and overlapping manner to form a basic structure;

[0010] A curved dividing groove is provided on the basic structure body, which runs through from the top layer to the bottom layer, so as to divide the basic structure body into two interlaced and mutually separated finger-fork structures; wherein the dividing groove comprises a transverse rectangular groove group and a longitudinal rectangular groove group, wherein the transverse rectangular grooves in the transverse rectangular groove group are parallel to each other, wherein the longitudinal rectangular grooves in the longitudinal groove group are parallel to each other, wherein the transverse rectangular grooves are perpendicular to the longitudinal rectangular grooves, wherein the longitudinal rectangular grooves are cross-arranged with the transverse rectangular grooves and connected end to end to form a complete curved dividing groove; wherein each finger-fork structure comprises a common connecting strip and a plurality of finger strips connected to the common connecting strip, wherein the two finger-fork structures are cross-intersected with each other; wherein the transverse rectangular groove is parallel to the finger strips, and wherein the longitudinal rectangular groove is parallel to the common connecting strip;

[0011] The storage medium layers required for the preset memory structure are arranged layer by layer on the inner wall of the dividing groove, and then the storage medium layers in the bottom area of ​​the dividing groove are etched until the basic structure is penetrated; wherein the preset memory structure is one of the following structures: a PN junction semiconductor memory structure, a Schottky semiconductor memory structure, and a memory medium memory structure;

[0012] Filling the dividing grooves with a core medium to form a core medium layer;

[0013] A mask-under-etching process is adopted to etch deep holes along the dividing grooves filled with the core medium, and the core medium layer and the storage medium layer in the dividing grooves are cut off by the deep holes to form a predetermined number of core medium blocks which are distributed along the direction of the dividing grooves and are independent of each other; each core medium block is still connected to the two interdigitated structures through the storage medium layer;

[0014] The etched deep holes are filled with insulating dielectric.

[0015] The present application also provides a method for preparing a high-density high-density three-dimensional programmable memory, comprising:

[0016] Arranging a predetermined number of conductive medium layers and insulating medium layers in a staggered and overlapping manner to form a basic structure;

[0017] A curved dividing groove is provided on the basic structure body, which runs through from the top layer to the bottom layer, so as to divide the basic structure body into two interlaced and mutually separated finger-fork structures; wherein the dividing groove comprises a transverse rectangular groove group and a longitudinal rectangular groove group, wherein the transverse rectangular grooves in the transverse rectangular groove group are parallel to each other, wherein the longitudinal rectangular grooves in the longitudinal groove group are parallel to each other, wherein the transverse rectangular grooves are perpendicular to the longitudinal rectangular grooves, wherein the longitudinal rectangular grooves are cross-arranged with the transverse rectangular grooves and connected end to end to form a complete curved dividing groove; wherein each finger-fork structure comprises a common connecting strip and a plurality of finger strips connected to the common connecting strip, wherein the two finger-fork structures are cross-intersected with each other; wherein the transverse rectangular groove is parallel to the finger strips, and wherein the longitudinal rectangular groove is parallel to the common connecting strip;

[0018] The storage medium layers required for the preset memory structure are arranged layer by layer on the inner wall of the dividing groove; wherein the preset memory structure is one of the following structures: a PN junction semiconductor memory structure, a Schottky semiconductor memory structure, and a memory medium memory structure;

[0019] Filling the dividing grooves with a core medium to form a core medium layer;

[0020] A mask-under-etching process is adopted to etch deep holes along the dividing grooves filled with the core medium, and the core medium layer and the storage medium layer in the dividing grooves are cut off by the deep holes to form a predetermined number of core medium blocks which are distributed along the direction of the dividing grooves and are independent of each other; each core medium block is still connected to the two interdigitated structures through the storage medium layer;

[0021] The etched deep holes are filled with insulating dielectrics, and then the filling dielectrics and underlying circuits are powered on to break down the storage dielectric layers in the bottom area of ​​the dividing grooves.

[0022] According to the specific embodiments provided by the present application, the present application has the following technical effects: the semiconductor memory prepared by the present application has high storage density, low process cost and high yield rate. The present application completes all required multi-layer etching in one multi-layer etching process step, which greatly simplifies the process flow, reduces costs and improves the yield rate. In addition, the present application also has the following characteristics: multi-layer 2bitsOTP storage cells are formed from deep grooves through deep well dielectric isolation; only two deep well etching and filling are required, and cell isolation and left and right finger isolation are completed in one step; the cell isolation self-aligned rectangular deep hole cell aperture can be made to the latest size to obtain the highest storage density; the process is relatively easy to control. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 It is a three-dimensional schematic diagram of a basic structure arranged on a substrate and underlying circuits.

[0025] Figure 2 A three-dimensional schematic diagram of the basic structure.

[0026] Figure 3 It is a top view schematic diagram of the prototype structure of the present invention.

[0027] Figure 4 It is a schematic diagram of the front view of the prototype structure of the present invention.

[0028] Figure 5 This is a schematic diagram of the top view of the prototype structure after the processing in step 2) of the present invention.

[0029] Figure 6 This is a schematic cross-sectional view of the prototype structure in the A--A' direction after the processing in step 2).

[0030] Figure 7 This is a schematic diagram of the top view of the prototype structure after processing in step 3 of the present invention.

[0031] Figure 8 This is a schematic cross-sectional view of the prototype structure in the A--A' direction after the processing in step 3).

[0032] Fig. 9 This is a schematic cross-sectional view of the prototype structure in the A--A' direction after etching through.

[0033] Fig.10 Schematic diagram of the top view of the prototype structure after step 4).

[0034] Fig.11 This is a schematic cross-sectional view of the prototype structure in the A--A' direction after the processing in step 4).

[0035] Fig.12 Schematic diagram of the top view of the prototype structure after step 5).

[0036] Fig.13 Schematic diagram of the top view of the prototype structure after step 6).

[0037] Fig.14 This is a schematic diagram of the memory structure of the first implementation mode.

[0038] Fig.15 Schematic diagram of the memory structure of the second implementation mode. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] In order to make the purpose, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0041] A method for preparing a high-density three-dimensional programmable memory comprises the following steps:

[0042] 1) Forming the basic structure: see Figure 1 to Figure 4 , a predetermined number of conductive dielectric layers and insulating dielectric layers are arranged in a staggered and overlapping manner to form a basic structure. In the actual process, the basic structure is arranged on the substrate and the bottom circuit, such as Figure 1 and Figure 4 shown. Figure 4 In the figure, 41 is a conductive dielectric layer, 42 is an insulating dielectric layer; or 42 is an insulating dielectric layer, 41 is a conductive dielectric layer, 43 is a bottom circuit, and 44 is a substrate.

[0043] 2) Slotting the base structure: see Figure 5 , Figure 6 , a curved dividing groove is opened on the basic structure, which runs from the top layer to the bottom layer, and the dividing groove divides the basic structure into two interlaced and mutually separated interdigitated structures; Figure 6 for Figure 5 A--A' sectional view schematically shown.

[0044] 3) See Figure 7-Figure 8 , the storage medium layers required for the preset memory structure are arranged layer by layer on the inner wall of the dividing groove. This step can be carried out by a deposition process, and after deposition, a bottom storage medium area will be formed in the bottom area of ​​the dividing groove. The bottom storage medium layer will insulate the core medium of the subsequent step from the bottom circuit, so a "penetration" step is required to form a conductive connection between the core medium layer and the bottom circuit.

[0045] As a first penetration method, the penetration step may be to etch a through hole in the storage medium area of ​​the bottom area after step 3) is completed and before step 4). Fig. 9, so the core medium filled in step 4) can be in direct contact with the bottom circuit; or after step 6), the core medium and the bottom circuit can be powered to break through the bottom storage medium area to form a conductive connection, which is the second penetration method.

[0046] 4) See Fig.10 , Fig.11 , filling the dividing groove with core medium to form a core medium layer.

[0047] 5) See Fig.12 , using the mask-under-etching process, deep holes are etched along the dividing grooves filled with the core medium, and the core medium and the storage medium in the dividing grooves are cut off by the deep holes to form multiple core medium blocks that are distributed along the direction of the dividing grooves and are independent of each other; each core medium block is still connected to the two interdigital structures through the storage medium layer.

[0048] 6) Fill the deep holes etched in step 5) with insulating medium, such as Fig.13 .

[0049] In the step 3), the preset memory structure is one of the following structures: a PN junction semiconductor memory structure, a Schottky semiconductor memory structure, a resistive memory structure, a magnetic memory structure, a phase change memory structure, and a ferroelectric memory structure.

[0050] by Fig.15 Taking the PN junction semiconductor memory structure shown in the figure as an example, it includes a P-type conductive area, an N-type conductive area and an insulating dielectric area arranged between the two. The present invention grows each storage dielectric layer layer by layer in the order of "P-type conductive area - insulating dielectric area - N-type conductive area". When the conductive dielectric layer of the basic structure itself is made of P-type conductive material, it is not necessary to set a P-type semiconductor again, and its core medium is an N-type semiconductor. In the preparation process of this embodiment, the storage dielectric layer of step 3) is an insulating dielectric layer, see Fig.15 .

[0051] Each storage medium layer arranged in the dividing groove can be a partial structural layer constituting the memory, or can be a complete structural layer constituting the memory, which is determined by the material type of the conductive medium layer and the core medium layer in the basic structure. For example, if the conductive medium layer of the basic structure is a P-type material, then only the insulating medium layer and the N-type material can be arranged on the inner wall of the dividing groove; if the material of the conductive medium layer and the material of the core medium layer are both conductors, then all the structural layers of the memory need to be deposited layer by layer on the groove wall, and the conductive medium layer and the core medium layer only serve as lead wires.

[0052] The first implementation method: dividing the three layers of medium in the groove. This implementation method includes the following steps:

[0053] 1. Forming a basic structure on the substrate and the underlying circuit: a predetermined number of conductive medium layers and insulating medium layers are arranged in a staggered and overlapping manner (for example, by a deposition process) to form a basic structure.

[0054] 2. Grooving the base structure: Using mask definition and deep well etching process, a split groove is etched on the base structure to split the base structure into two interlaced and separated interdigitated structures.

[0055] 3. Using the ALD process, a first dielectric layer 101 is deposited on the inner wall of the dividing groove; and then using the ALD process, a second dielectric layer 102 is deposited on the surface of the first dielectric layer 101 .

[0056] 4. Filling the core dielectric in the cavity of the dividing groove provided with the first dielectric layer and the second dielectric layer to form a core dielectric layer.

[0057] 5. Using the mask-under-etching process, deep holes are etched along the dividing grooves filled with the core medium. The core medium and the storage medium in the dividing grooves are cut off by the deep holes to form multiple core medium blocks distributed along the dividing grooves and independent of each other, which are called core medium block sequences. Each core medium block is still connected to the two interdigitated structures through the storage medium layer.

[0058] 6) Fill the deep hole with insulating dielectric material.

[0059] In this embodiment, the storage medium layer includes a first medium layer and a second medium layer. The combinations of the media involved are shown in the following table. Each combination is an embodiment. Fig.14 .

[0060] Table 1

[0061]

[0062] The thickness of the insulating medium in the above table is preferably 0.5-5 nm, and the first dielectric layer and the second dielectric layer are both storage dielectric layers.

[0063] The characteristics of the present application are: forming a finger-forked structure including finger strips and common connecting strips, the two finger-forked structures intersect each other, and between the finger strips are multiple independent storage bodies isolated by insulators, and the insulators are insulating media filled in the cutting slots. In each layer of the basic structure, each storage body includes two storage units, such as Fig.14 The storage unit is composed of a first medium, a second medium, and a core medium, and the materials of each layer meet the requirements of a PN junction or a Schottky structure.

[0064] Second implementation mode: two layers of medium in the dividing groove. The difference between this implementation mode and the first implementation mode is that only two layers of medium are arranged in the dividing groove in this implementation mode, namely, the first medium and the core medium. The schematic diagram of the memory prepared by the process of this implementation mode is shown in FIG. Fig.10 . Fig.11 is an enlarged schematic diagram of a single storage body. The possible combinations of the various media involved are shown in the following table. The first medium layer in the table is the storage medium layer. Each combination is an embodiment. Fig.15 shown.

[0065] Table 2

[0066]

[0067] The memory medium is a resistive memory, a magnetic memory, a phase change memory or a ferroelectric memory.

[0068] In the present application, all dielectric layers except the core dielectric layer in the dividing groove of the basic structure are collectively referred to as "storage dielectric layers", for example: the first dielectric layer (insulating layer) in Table 1, the second dielectric layer (buffer layer) in Table 1, and the first dielectric layer in Table 2. In the present application, the above layers are all referred to as storage dielectric layers.

[0069] The process steps of the present invention are very concise and can be summarized into the following five steps:

[0070] (1) Grooving the base structure to form an interdigitated structure.

[0071] (2) A storage medium layer is provided on the inner wall of the groove.

[0072] (3) Filling the core medium.

[0073] (4) Divide the core medium.

[0074] (5) Fill with insulating medium.

[0075] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A method for preparing a high-density three-dimensional programmable memory, characterized in that: Methods include: Arranging a predetermined number of conductive medium layers and insulating medium layers in a staggered and overlapping manner to form a basic structure; A curved dividing groove is provided on the basic structure body, which runs through from the top layer to the bottom layer, so as to divide the basic structure body into two interlaced and mutually separated finger-fork structures; wherein the dividing groove comprises a transverse rectangular groove group and a longitudinal rectangular groove group, wherein the transverse rectangular grooves in the transverse rectangular groove group are parallel to each other, wherein the longitudinal rectangular grooves in the longitudinal groove group are parallel to each other, wherein the transverse rectangular grooves are perpendicular to the longitudinal rectangular grooves, wherein the longitudinal rectangular grooves are cross-arranged with the transverse rectangular grooves and connected end to end to form a complete curved dividing groove; wherein each finger-fork structure comprises a common connecting strip and a plurality of finger strips connected to the common connecting strip, wherein the two finger-fork structures are cross-intersected with each other; wherein the transverse rectangular groove is parallel to the finger strips, and wherein the longitudinal rectangular groove is parallel to the common connecting strip; The storage medium layers required for the preset memory structure are arranged layer by layer on the inner wall of the dividing groove, and then the storage medium layers in the bottom area of ​​the dividing groove are etched until the basic structure is penetrated; wherein the preset memory structure is one of the following structures: a PN junction semiconductor memory structure, a Schottky semiconductor memory structure, and a memory medium memory structure; Filling the dividing grooves with a core medium to form a core medium layer; A mask-under-etching process is adopted to etch deep holes along the dividing grooves filled with the core medium, and the core medium layer and the storage medium layer in the dividing grooves are cut off by the deep holes to form a predetermined number of core medium blocks which are distributed along the direction of the dividing grooves and are independent of each other; each core medium block is still connected to the two interdigitated structures through the storage medium layer; The etched deep holes are filled with insulating dielectric.

2. The method for preparing a high-density three-dimensional programmable memory according to claim 1, characterized in that: When the preset memory structure is a PN junction semiconductor memory structure, it includes a P-type conductive area, an N-type conductive area and an insulating dielectric area arranged therebetween; wherein the conductive dielectric layer is a P-type semiconductor and the core dielectric layer is an N-type semiconductor; or the conductive dielectric layer is an N-type semiconductor and the core dielectric layer is a P-type semiconductor; The method further includes: providing an insulating layer inside the dividing groove.

3. The method for preparing a high-density three-dimensional programmable memory according to claim 1, characterized in that: When the preset memory structure is a Schottky diode memory structure, it includes a semiconductor conductive region, a metal conductive region and an insulating dielectric region arranged therebetween; wherein the conductive dielectric layer is a semiconductor required to form a Schottky diode structure, and the core dielectric layer is a metal required to form a Schottky diode structure; or, the conductive dielectric layer is a metal required to form a Schottky diode structure, and the core dielectric layer is a semiconductor required to form a Schottky diode structure.

4. The method for preparing a high-density three-dimensional programmable memory according to claim 1, characterized in that: When the preset memory structure is a memory medium memory structure, the memory medium memory structure is a resistive memory structure, a magnetic memory structure, a phase change memory structure or a ferroelectric memory structure; wherein the conductive medium layer and the core medium layer are made of metal or polysilicon; The method further includes: disposing a memory medium layer inside the dividing groove.

5. The method for preparing a high-density three-dimensional programmable memory according to claim 1, characterized in that: When the preset memory structure is a PN junction semiconductor memory structure, it includes a P-type conductive region, an N-type conductive region and an insulating dielectric region disposed therebetween; Wherein, when the conductive medium layer is a P+ type semiconductor and the core medium is an N+ type semiconductor or conductor, the method further comprises: providing an insulating layer inside the dividing groove; providing a low-doped N-type semiconductor layer on the inner wall of the insulating layer; filling the core medium in the cavity of the dividing groove provided with the insulating layer and the low-doped N-type semiconductor layer; When the conductive medium layer is an N+ type semiconductor or conductor and the core medium is a P+ type semiconductor, the method further includes: setting a low-doped N-type semiconductor layer inside the dividing groove; setting an insulating layer on the inner wall of the low-doped N-type semiconductor layer; and filling the core medium in the cavity of the dividing groove where the low-doped N-type semiconductor layer and the insulating layer are set.

6. The method for preparing a high-density three-dimensional programmable memory according to claim 1, characterized in that: When the preset memory structure is a Schottky-type semiconductor memory structure, it includes a metal conductive region, a semiconductor conductive region and an insulating dielectric region disposed therebetween; The method further includes: providing an insulating layer inside the dividing groove; providing a semiconductor layer on the inner wall of the insulating layer; filling a core dielectric in the cavity of the dividing groove provided with the insulating layer and the conductor layer; The conductive medium layer is a metal that meets the requirements of a Schottky diode, the semiconductor layer is a semiconductor that meets the requirements of a Schottky diode, and the core medium is a conductor.

7. A method for preparing a high-density three-dimensional programmable memory, characterized in that: Methods include: Arranging a predetermined number of conductive medium layers and insulating medium layers in a staggered and overlapping manner to form a basic structure; A curved dividing groove is provided on the basic structure body, which runs through from the top layer to the bottom layer, so as to divide the basic structure body into two interlaced and mutually separated finger-fork structures; wherein the dividing groove comprises a transverse rectangular groove group and a longitudinal rectangular groove group, wherein the transverse rectangular grooves in the transverse rectangular groove group are parallel to each other, wherein the longitudinal rectangular grooves in the longitudinal groove group are parallel to each other, wherein the transverse rectangular grooves are perpendicular to the longitudinal rectangular grooves, wherein the longitudinal rectangular grooves are cross-arranged with the transverse rectangular grooves and connected end to end to form a complete curved dividing groove; wherein each finger-fork structure comprises a common connecting strip and a plurality of finger strips connected to the common connecting strip, wherein the two finger-fork structures are cross-intersected with each other; wherein the transverse rectangular groove is parallel to the finger strips, and wherein the longitudinal rectangular groove is parallel to the common connecting strip; The storage medium layers required for the preset memory structure are arranged layer by layer on the inner wall of the dividing groove; wherein the preset memory structure is one of the following structures: a PN junction semiconductor memory structure, a Schottky semiconductor memory structure, and a memory medium memory structure; Filling the dividing grooves with a core medium to form a core medium layer; A mask-under-etching process is adopted to etch deep holes along the dividing grooves filled with the core medium, and the core medium layer and the storage medium layer in the dividing grooves are cut off by the deep holes to form a predetermined number of core medium blocks which are distributed along the direction of the dividing grooves and are independent of each other; each core medium block is still connected to the two interdigitated structures through the storage medium layer; The etched deep holes are filled with insulating dielectrics, and then the filling dielectrics and underlying circuits are powered on to break down the storage dielectric layers in the bottom area of ​​the dividing grooves.

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